intel-iommu.c 108.6 KB
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/*
 * Copyright (c) 2006, Intel Corporation.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
 * version 2, as published by the Free Software Foundation.
 *
 * This program is distributed in the hope it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 *
 * You should have received a copy of the GNU General Public License along with
 * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
 * Place - Suite 330, Boston, MA 02111-1307 USA.
 *
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 * Copyright (C) 2006-2008 Intel Corporation
 * Author: Ashok Raj <ashok.raj@intel.com>
 * Author: Shaohua Li <shaohua.li@intel.com>
 * Author: Anil S Keshavamurthy <anil.s.keshavamurthy@intel.com>
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 * Author: Fenghua Yu <fenghua.yu@intel.com>
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 */

#include <linux/init.h>
#include <linux/bitmap.h>
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#include <linux/debugfs.h>
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#include <linux/export.h>
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#include <linux/slab.h>
#include <linux/irq.h>
#include <linux/interrupt.h>
#include <linux/spinlock.h>
#include <linux/pci.h>
#include <linux/dmar.h>
#include <linux/dma-mapping.h>
#include <linux/mempool.h>
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#include <linux/timer.h>
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#include <linux/iova.h>
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#include <linux/iommu.h>
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#include <linux/intel-iommu.h>
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#include <linux/syscore_ops.h>
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#include <linux/tboot.h>
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#include <linux/dmi.h>
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#include <linux/pci-ats.h>
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#include <linux/memblock.h>
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#include <asm/irq_remapping.h>
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#include <asm/cacheflush.h>
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#include <asm/iommu.h>
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#include "irq_remapping.h"

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#define ROOT_SIZE		VTD_PAGE_SIZE
#define CONTEXT_SIZE		VTD_PAGE_SIZE

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#define IS_GFX_DEVICE(pdev) ((pdev->class >> 16) == PCI_BASE_CLASS_DISPLAY)
#define IS_ISA_DEVICE(pdev) ((pdev->class >> 8) == PCI_CLASS_BRIDGE_ISA)
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#define IS_AZALIA(pdev) ((pdev)->vendor == 0x8086 && (pdev)->device == 0x3a3e)
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#define IOAPIC_RANGE_START	(0xfee00000)
#define IOAPIC_RANGE_END	(0xfeefffff)
#define IOVA_START_ADDR		(0x1000)

#define DEFAULT_DOMAIN_ADDRESS_WIDTH 48

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#define MAX_AGAW_WIDTH 64

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#define __DOMAIN_MAX_PFN(gaw)  ((((uint64_t)1) << (gaw-VTD_PAGE_SHIFT)) - 1)
#define __DOMAIN_MAX_ADDR(gaw) ((((uint64_t)1) << gaw) - 1)

/* We limit DOMAIN_MAX_PFN to fit in an unsigned long, and DOMAIN_MAX_ADDR
   to match. That way, we can use 'unsigned long' for PFNs with impunity. */
#define DOMAIN_MAX_PFN(gaw)	((unsigned long) min_t(uint64_t, \
				__DOMAIN_MAX_PFN(gaw), (unsigned long)-1))
#define DOMAIN_MAX_ADDR(gaw)	(((uint64_t)__DOMAIN_MAX_PFN(gaw)) << VTD_PAGE_SHIFT)
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#define IOVA_PFN(addr)		((addr) >> PAGE_SHIFT)
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#define DMA_32BIT_PFN		IOVA_PFN(DMA_BIT_MASK(32))
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#define DMA_64BIT_PFN		IOVA_PFN(DMA_BIT_MASK(64))
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/* page table handling */
#define LEVEL_STRIDE		(9)
#define LEVEL_MASK		(((u64)1 << LEVEL_STRIDE) - 1)

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/*
 * This bitmap is used to advertise the page sizes our hardware support
 * to the IOMMU core, which will then use this information to split
 * physically contiguous memory regions it is mapping into page sizes
 * that we support.
 *
 * Traditionally the IOMMU core just handed us the mappings directly,
 * after making sure the size is an order of a 4KiB page and that the
 * mapping has natural alignment.
 *
 * To retain this behavior, we currently advertise that we support
 * all page sizes that are an order of 4KiB.
 *
 * If at some point we'd like to utilize the IOMMU core's new behavior,
 * we could change this to advertise the real page sizes we support.
 */
#define INTEL_IOMMU_PGSIZES	(~0xFFFUL)

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static inline int agaw_to_level(int agaw)
{
	return agaw + 2;
}

static inline int agaw_to_width(int agaw)
{
	return 30 + agaw * LEVEL_STRIDE;
}

static inline int width_to_agaw(int width)
{
	return (width - 30) / LEVEL_STRIDE;
}

static inline unsigned int level_to_offset_bits(int level)
{
	return (level - 1) * LEVEL_STRIDE;
}

static inline int pfn_level_offset(unsigned long pfn, int level)
{
	return (pfn >> level_to_offset_bits(level)) & LEVEL_MASK;
}

static inline unsigned long level_mask(int level)
{
	return -1UL << level_to_offset_bits(level);
}

static inline unsigned long level_size(int level)
{
	return 1UL << level_to_offset_bits(level);
}

static inline unsigned long align_to_level(unsigned long pfn, int level)
{
	return (pfn + level_size(level) - 1) & level_mask(level);
}
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static inline unsigned long lvl_to_nr_pages(unsigned int lvl)
{
	return  1 << ((lvl - 1) * LEVEL_STRIDE);
}

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/* VT-d pages must always be _smaller_ than MM pages. Otherwise things
   are never going to work. */
static inline unsigned long dma_to_mm_pfn(unsigned long dma_pfn)
{
	return dma_pfn >> (PAGE_SHIFT - VTD_PAGE_SHIFT);
}

static inline unsigned long mm_to_dma_pfn(unsigned long mm_pfn)
{
	return mm_pfn << (PAGE_SHIFT - VTD_PAGE_SHIFT);
}
static inline unsigned long page_to_dma_pfn(struct page *pg)
{
	return mm_to_dma_pfn(page_to_pfn(pg));
}
static inline unsigned long virt_to_dma_pfn(void *p)
{
	return page_to_dma_pfn(virt_to_page(p));
}

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/* global iommu list, set NULL for ignored DMAR units */
static struct intel_iommu **g_iommus;

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static void __init check_tylersburg_isoch(void);
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static int rwbf_quirk;

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/*
 * set to 1 to panic kernel if can't successfully enable VT-d
 * (used when kernel is launched w/ TXT)
 */
static int force_on = 0;

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/*
 * 0: Present
 * 1-11: Reserved
 * 12-63: Context Ptr (12 - (haw-1))
 * 64-127: Reserved
 */
struct root_entry {
	u64	val;
	u64	rsvd1;
};
#define ROOT_ENTRY_NR (VTD_PAGE_SIZE/sizeof(struct root_entry))
static inline bool root_present(struct root_entry *root)
{
	return (root->val & 1);
}
static inline void set_root_present(struct root_entry *root)
{
	root->val |= 1;
}
static inline void set_root_value(struct root_entry *root, unsigned long value)
{
	root->val |= value & VTD_PAGE_MASK;
}

static inline struct context_entry *
get_context_addr_from_root(struct root_entry *root)
{
	return (struct context_entry *)
		(root_present(root)?phys_to_virt(
		root->val & VTD_PAGE_MASK) :
		NULL);
}

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/*
 * low 64 bits:
 * 0: present
 * 1: fault processing disable
 * 2-3: translation type
 * 12-63: address space root
 * high 64 bits:
 * 0-2: address width
 * 3-6: aval
 * 8-23: domain id
 */
struct context_entry {
	u64 lo;
	u64 hi;
};
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static inline bool context_present(struct context_entry *context)
{
	return (context->lo & 1);
}
static inline void context_set_present(struct context_entry *context)
{
	context->lo |= 1;
}

static inline void context_set_fault_enable(struct context_entry *context)
{
	context->lo &= (((u64)-1) << 2) | 1;
}

static inline void context_set_translation_type(struct context_entry *context,
						unsigned long value)
{
	context->lo &= (((u64)-1) << 4) | 3;
	context->lo |= (value & 3) << 2;
}

static inline void context_set_address_root(struct context_entry *context,
					    unsigned long value)
{
	context->lo |= value & VTD_PAGE_MASK;
}

static inline void context_set_address_width(struct context_entry *context,
					     unsigned long value)
{
	context->hi |= value & 7;
}

static inline void context_set_domain_id(struct context_entry *context,
					 unsigned long value)
{
	context->hi |= (value & ((1 << 16) - 1)) << 8;
}

static inline void context_clear_entry(struct context_entry *context)
{
	context->lo = 0;
	context->hi = 0;
}
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/*
 * 0: readable
 * 1: writable
 * 2-6: reserved
 * 7: super page
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 * 8-10: available
 * 11: snoop behavior
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 * 12-63: Host physcial address
 */
struct dma_pte {
	u64 val;
};

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static inline void dma_clear_pte(struct dma_pte *pte)
{
	pte->val = 0;
}

static inline void dma_set_pte_readable(struct dma_pte *pte)
{
	pte->val |= DMA_PTE_READ;
}

static inline void dma_set_pte_writable(struct dma_pte *pte)
{
	pte->val |= DMA_PTE_WRITE;
}

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static inline void dma_set_pte_snp(struct dma_pte *pte)
{
	pte->val |= DMA_PTE_SNP;
}

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static inline void dma_set_pte_prot(struct dma_pte *pte, unsigned long prot)
{
	pte->val = (pte->val & ~3) | (prot & 3);
}

static inline u64 dma_pte_addr(struct dma_pte *pte)
{
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#ifdef CONFIG_64BIT
	return pte->val & VTD_PAGE_MASK;
#else
	/* Must have a full atomic 64-bit read */
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	return  __cmpxchg64(&pte->val, 0ULL, 0ULL) & VTD_PAGE_MASK;
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#endif
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}

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static inline void dma_set_pte_pfn(struct dma_pte *pte, unsigned long pfn)
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{
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	pte->val |= (uint64_t)pfn << VTD_PAGE_SHIFT;
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}

static inline bool dma_pte_present(struct dma_pte *pte)
{
	return (pte->val & 3) != 0;
}
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static inline bool dma_pte_superpage(struct dma_pte *pte)
{
	return (pte->val & (1 << 7));
}

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static inline int first_pte_in_page(struct dma_pte *pte)
{
	return !((unsigned long)pte & ~VTD_PAGE_MASK);
}

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/*
 * This domain is a statically identity mapping domain.
 *	1. This domain creats a static 1:1 mapping to all usable memory.
 * 	2. It maps to each iommu if successful.
 *	3. Each iommu mapps to this domain if successful.
 */
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static struct dmar_domain *si_domain;
static int hw_pass_through = 1;
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/* devices under the same p2p bridge are owned in one domain */
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#define DOMAIN_FLAG_P2P_MULTIPLE_DEVICES (1 << 0)
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/* domain represents a virtual machine, more than one devices
 * across iommus may be owned in one domain, e.g. kvm guest.
 */
#define DOMAIN_FLAG_VIRTUAL_MACHINE	(1 << 1)

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/* si_domain contains mulitple devices */
#define DOMAIN_FLAG_STATIC_IDENTITY	(1 << 2)

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/* define the limit of IOMMUs supported in each domain */
#ifdef	CONFIG_X86
# define	IOMMU_UNITS_SUPPORTED	MAX_IO_APICS
#else
# define	IOMMU_UNITS_SUPPORTED	64
#endif

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struct dmar_domain {
	int	id;			/* domain id */
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	int	nid;			/* node id */
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	DECLARE_BITMAP(iommu_bmp, IOMMU_UNITS_SUPPORTED);
					/* bitmap of iommus this domain uses*/
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	struct list_head devices; 	/* all devices' list */
	struct iova_domain iovad;	/* iova's that belong to this domain */

	struct dma_pte	*pgd;		/* virtual address */
	int		gaw;		/* max guest address width */

	/* adjusted guest address width, 0 is level 2 30-bit */
	int		agaw;

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	int		flags;		/* flags to find out type of domain */
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	int		iommu_coherency;/* indicate coherency of iommu access */
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	int		iommu_snooping; /* indicate snooping control feature*/
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	int		iommu_count;	/* reference count of iommu */
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	int		iommu_superpage;/* Level of superpages supported:
					   0 == 4KiB (no superpages), 1 == 2MiB,
					   2 == 1GiB, 3 == 512GiB, 4 == 1TiB */
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	spinlock_t	iommu_lock;	/* protect iommu set in domain */
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	u64		max_addr;	/* maximum mapped address */
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};

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/* PCI domain-device relationship */
struct device_domain_info {
	struct list_head link;	/* link to domain siblings */
	struct list_head global; /* link to global list */
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	int segment;		/* PCI domain */
	u8 bus;			/* PCI bus number */
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	u8 devfn;		/* PCI devfn number */
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	struct pci_dev *dev; /* it's NULL for PCIe-to-PCI bridge */
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	struct intel_iommu *iommu; /* IOMMU used by this device */
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	struct dmar_domain *domain; /* pointer to domain */
};

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static void flush_unmaps_timeout(unsigned long data);

DEFINE_TIMER(unmap_timer,  flush_unmaps_timeout, 0, 0);

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#define HIGH_WATER_MARK 250
struct deferred_flush_tables {
	int next;
	struct iova *iova[HIGH_WATER_MARK];
	struct dmar_domain *domain[HIGH_WATER_MARK];
};

static struct deferred_flush_tables *deferred_flush;

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/* bitmap for indexing intel_iommus */
static int g_num_of_iommus;

static DEFINE_SPINLOCK(async_umap_flush_lock);
static LIST_HEAD(unmaps_to_do);

static int timer_on;
static long list_size;

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static void domain_remove_dev_info(struct dmar_domain *domain);

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#ifdef CONFIG_INTEL_IOMMU_DEFAULT_ON
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int dmar_disabled = 0;
#else
int dmar_disabled = 1;
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#endif /*CONFIG_INTEL_IOMMU_DEFAULT_ON*/
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int intel_iommu_enabled = 0;
EXPORT_SYMBOL_GPL(intel_iommu_enabled);

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static int dmar_map_gfx = 1;
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static int dmar_forcedac;
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static int intel_iommu_strict;
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static int intel_iommu_superpage = 1;
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int intel_iommu_gfx_mapped;
EXPORT_SYMBOL_GPL(intel_iommu_gfx_mapped);

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#define DUMMY_DEVICE_DOMAIN_INFO ((struct device_domain_info *)(-1))
static DEFINE_SPINLOCK(device_domain_lock);
static LIST_HEAD(device_domain_list);

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static struct iommu_ops intel_iommu_ops;

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static int __init intel_iommu_setup(char *str)
{
	if (!str)
		return -EINVAL;
	while (*str) {
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		if (!strncmp(str, "on", 2)) {
			dmar_disabled = 0;
			printk(KERN_INFO "Intel-IOMMU: enabled\n");
		} else if (!strncmp(str, "off", 3)) {
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			dmar_disabled = 1;
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			printk(KERN_INFO "Intel-IOMMU: disabled\n");
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		} else if (!strncmp(str, "igfx_off", 8)) {
			dmar_map_gfx = 0;
			printk(KERN_INFO
				"Intel-IOMMU: disable GFX device mapping\n");
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		} else if (!strncmp(str, "forcedac", 8)) {
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			printk(KERN_INFO
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				"Intel-IOMMU: Forcing DAC for PCI devices\n");
			dmar_forcedac = 1;
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		} else if (!strncmp(str, "strict", 6)) {
			printk(KERN_INFO
				"Intel-IOMMU: disable batched IOTLB flush\n");
			intel_iommu_strict = 1;
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		} else if (!strncmp(str, "sp_off", 6)) {
			printk(KERN_INFO
				"Intel-IOMMU: disable supported super page\n");
			intel_iommu_superpage = 0;
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		}

		str += strcspn(str, ",");
		while (*str == ',')
			str++;
	}
	return 0;
}
__setup("intel_iommu=", intel_iommu_setup);

static struct kmem_cache *iommu_domain_cache;
static struct kmem_cache *iommu_devinfo_cache;
static struct kmem_cache *iommu_iova_cache;

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static inline void *alloc_pgtable_page(int node)
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{
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	struct page *page;
	void *vaddr = NULL;
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	page = alloc_pages_node(node, GFP_ATOMIC | __GFP_ZERO, 0);
	if (page)
		vaddr = page_address(page);
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	return vaddr;
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}

static inline void free_pgtable_page(void *vaddr)
{
	free_page((unsigned long)vaddr);
}

static inline void *alloc_domain_mem(void)
{
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	return kmem_cache_alloc(iommu_domain_cache, GFP_ATOMIC);
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}

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static void free_domain_mem(void *vaddr)
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{
	kmem_cache_free(iommu_domain_cache, vaddr);
}

static inline void * alloc_devinfo_mem(void)
{
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	return kmem_cache_alloc(iommu_devinfo_cache, GFP_ATOMIC);
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}

static inline void free_devinfo_mem(void *vaddr)
{
	kmem_cache_free(iommu_devinfo_cache, vaddr);
}

struct iova *alloc_iova_mem(void)
{
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	return kmem_cache_alloc(iommu_iova_cache, GFP_ATOMIC);
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}

void free_iova_mem(struct iova *iova)
{
	kmem_cache_free(iommu_iova_cache, iova);
}

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static int __iommu_calculate_agaw(struct intel_iommu *iommu, int max_gaw)
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{
	unsigned long sagaw;
	int agaw = -1;

	sagaw = cap_sagaw(iommu->cap);
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	for (agaw = width_to_agaw(max_gaw);
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	     agaw >= 0; agaw--) {
		if (test_bit(agaw, &sagaw))
			break;
	}

	return agaw;
}

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/*
 * Calculate max SAGAW for each iommu.
 */
int iommu_calculate_max_sagaw(struct intel_iommu *iommu)
{
	return __iommu_calculate_agaw(iommu, MAX_AGAW_WIDTH);
}

/*
 * calculate agaw for each iommu.
 * "SAGAW" may be different across iommus, use a default agaw, and
 * get a supported less agaw for iommus that don't support the default agaw.
 */
int iommu_calculate_agaw(struct intel_iommu *iommu)
{
	return __iommu_calculate_agaw(iommu, DEFAULT_DOMAIN_ADDRESS_WIDTH);
}

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/* This functionin only returns single iommu in a domain */
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static struct intel_iommu *domain_get_iommu(struct dmar_domain *domain)
{
	int iommu_id;

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	/* si_domain and vm domain should not get here. */
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	BUG_ON(domain->flags & DOMAIN_FLAG_VIRTUAL_MACHINE);
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	BUG_ON(domain->flags & DOMAIN_FLAG_STATIC_IDENTITY);
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	iommu_id = find_first_bit(domain->iommu_bmp, g_num_of_iommus);
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	if (iommu_id < 0 || iommu_id >= g_num_of_iommus)
		return NULL;

	return g_iommus[iommu_id];
}

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static void domain_update_iommu_coherency(struct dmar_domain *domain)
{
	int i;

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	i = find_first_bit(domain->iommu_bmp, g_num_of_iommus);

	domain->iommu_coherency = i < g_num_of_iommus ? 1 : 0;
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	for_each_set_bit(i, domain->iommu_bmp, g_num_of_iommus) {
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		if (!ecap_coherent(g_iommus[i]->ecap)) {
			domain->iommu_coherency = 0;
			break;
		}
	}
}

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static void domain_update_iommu_snooping(struct dmar_domain *domain)
{
	int i;

	domain->iommu_snooping = 1;

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	for_each_set_bit(i, domain->iommu_bmp, g_num_of_iommus) {
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		if (!ecap_sc_support(g_iommus[i]->ecap)) {
			domain->iommu_snooping = 0;
			break;
		}
	}
}

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static void domain_update_iommu_superpage(struct dmar_domain *domain)
{
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	struct dmar_drhd_unit *drhd;
	struct intel_iommu *iommu = NULL;
	int mask = 0xf;
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	if (!intel_iommu_superpage) {
		domain->iommu_superpage = 0;
		return;
	}

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	/* set iommu_superpage to the smallest common denominator */
	for_each_active_iommu(iommu, drhd) {
		mask &= cap_super_page_val(iommu->cap);
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		if (!mask) {
			break;
		}
	}
	domain->iommu_superpage = fls(mask);
}

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/* Some capabilities may be different across iommus */
static void domain_update_iommu_cap(struct dmar_domain *domain)
{
	domain_update_iommu_coherency(domain);
	domain_update_iommu_snooping(domain);
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	domain_update_iommu_superpage(domain);
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}

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static struct intel_iommu *device_to_iommu(int segment, u8 bus, u8 devfn)
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{
	struct dmar_drhd_unit *drhd = NULL;
	int i;

	for_each_drhd_unit(drhd) {
		if (drhd->ignored)
			continue;
657 658
		if (segment != drhd->segment)
			continue;
659

660
		for (i = 0; i < drhd->devices_cnt; i++) {
D
Dirk Hohndel 已提交
661 662
			if (drhd->devices[i] &&
			    drhd->devices[i]->bus->number == bus &&
663 664
			    drhd->devices[i]->devfn == devfn)
				return drhd->iommu;
665 666
			if (drhd->devices[i] &&
			    drhd->devices[i]->subordinate &&
667
			    drhd->devices[i]->subordinate->number <= bus &&
668
			    drhd->devices[i]->subordinate->busn_res.end >= bus)
669 670
				return drhd->iommu;
		}
671 672 673 674 675 676 677 678

		if (drhd->include_all)
			return drhd->iommu;
	}

	return NULL;
}

W
Weidong Han 已提交
679 680 681 682 683 684 685
static void domain_flush_cache(struct dmar_domain *domain,
			       void *addr, int size)
{
	if (!domain->iommu_coherency)
		clflush_cache_range(addr, size);
}

686 687 688 689 690 691 692 693 694 695 696 697 698
/* Gets context entry for a given bus and devfn */
static struct context_entry * device_to_context_entry(struct intel_iommu *iommu,
		u8 bus, u8 devfn)
{
	struct root_entry *root;
	struct context_entry *context;
	unsigned long phy_addr;
	unsigned long flags;

	spin_lock_irqsave(&iommu->lock, flags);
	root = &iommu->root_entry[bus];
	context = get_context_addr_from_root(root);
	if (!context) {
699 700
		context = (struct context_entry *)
				alloc_pgtable_page(iommu->node);
701 702 703 704
		if (!context) {
			spin_unlock_irqrestore(&iommu->lock, flags);
			return NULL;
		}
F
Fenghua Yu 已提交
705
		__iommu_flush_cache(iommu, (void *)context, CONTEXT_SIZE);
706 707 708 709 710 711 712 713 714 715 716 717 718 719 720 721 722 723 724 725 726 727 728
		phy_addr = virt_to_phys((void *)context);
		set_root_value(root, phy_addr);
		set_root_present(root);
		__iommu_flush_cache(iommu, root, sizeof(*root));
	}
	spin_unlock_irqrestore(&iommu->lock, flags);
	return &context[devfn];
}

static int device_context_mapped(struct intel_iommu *iommu, u8 bus, u8 devfn)
{
	struct root_entry *root;
	struct context_entry *context;
	int ret;
	unsigned long flags;

	spin_lock_irqsave(&iommu->lock, flags);
	root = &iommu->root_entry[bus];
	context = get_context_addr_from_root(root);
	if (!context) {
		ret = 0;
		goto out;
	}
729
	ret = context_present(&context[devfn]);
730 731 732 733 734 735 736 737 738 739 740 741 742 743 744
out:
	spin_unlock_irqrestore(&iommu->lock, flags);
	return ret;
}

static void clear_context_table(struct intel_iommu *iommu, u8 bus, u8 devfn)
{
	struct root_entry *root;
	struct context_entry *context;
	unsigned long flags;

	spin_lock_irqsave(&iommu->lock, flags);
	root = &iommu->root_entry[bus];
	context = get_context_addr_from_root(root);
	if (context) {
745
		context_clear_entry(&context[devfn]);
746 747 748 749 750 751 752 753 754 755 756 757 758 759 760 761 762 763 764 765 766 767 768 769 770 771 772 773 774
		__iommu_flush_cache(iommu, &context[devfn], \
			sizeof(*context));
	}
	spin_unlock_irqrestore(&iommu->lock, flags);
}

static void free_context_table(struct intel_iommu *iommu)
{
	struct root_entry *root;
	int i;
	unsigned long flags;
	struct context_entry *context;

	spin_lock_irqsave(&iommu->lock, flags);
	if (!iommu->root_entry) {
		goto out;
	}
	for (i = 0; i < ROOT_ENTRY_NR; i++) {
		root = &iommu->root_entry[i];
		context = get_context_addr_from_root(root);
		if (context)
			free_pgtable_page(context);
	}
	free_pgtable_page(iommu->root_entry);
	iommu->root_entry = NULL;
out:
	spin_unlock_irqrestore(&iommu->lock, flags);
}

775
static struct dma_pte *pfn_to_dma_pte(struct dmar_domain *domain,
776
				      unsigned long pfn, int target_level)
777
{
778
	int addr_width = agaw_to_width(domain->agaw) - VTD_PAGE_SHIFT;
779 780
	struct dma_pte *parent, *pte = NULL;
	int level = agaw_to_level(domain->agaw);
781
	int offset;
782 783

	BUG_ON(!domain->pgd);
784
	BUG_ON(addr_width < BITS_PER_LONG && pfn >> addr_width);
785 786 787 788 789
	parent = domain->pgd;

	while (level > 0) {
		void *tmp_page;

790
		offset = pfn_level_offset(pfn, level);
791
		pte = &parent[offset];
792
		if (!target_level && (dma_pte_superpage(pte) || !dma_pte_present(pte)))
793 794
			break;
		if (level == target_level)
795 796
			break;

797
		if (!dma_pte_present(pte)) {
798 799
			uint64_t pteval;

800
			tmp_page = alloc_pgtable_page(domain->nid);
801

802
			if (!tmp_page)
803
				return NULL;
804

805
			domain_flush_cache(domain, tmp_page, VTD_PAGE_SIZE);
806
			pteval = ((uint64_t)virt_to_dma_pfn(tmp_page) << VTD_PAGE_SHIFT) | DMA_PTE_READ | DMA_PTE_WRITE;
807 808 809 810 811 812 813
			if (cmpxchg64(&pte->val, 0ULL, pteval)) {
				/* Someone else set it while we were thinking; use theirs. */
				free_pgtable_page(tmp_page);
			} else {
				dma_pte_addr(pte);
				domain_flush_cache(domain, pte, sizeof(*pte));
			}
814
		}
815
		parent = phys_to_virt(dma_pte_addr(pte));
816 817 818 819 820 821
		level--;
	}

	return pte;
}

822

823
/* return address's pte at specific level */
824 825
static struct dma_pte *dma_pfn_level_pte(struct dmar_domain *domain,
					 unsigned long pfn,
826
					 int level, int *large_page)
827 828 829 830 831 832 833
{
	struct dma_pte *parent, *pte = NULL;
	int total = agaw_to_level(domain->agaw);
	int offset;

	parent = domain->pgd;
	while (level <= total) {
834
		offset = pfn_level_offset(pfn, total);
835 836 837 838
		pte = &parent[offset];
		if (level == total)
			return pte;

839 840
		if (!dma_pte_present(pte)) {
			*large_page = total;
841
			break;
842 843 844 845 846 847 848
		}

		if (pte->val & DMA_PTE_LARGE_PAGE) {
			*large_page = total;
			return pte;
		}

849
		parent = phys_to_virt(dma_pte_addr(pte));
850 851 852 853 854 855
		total--;
	}
	return NULL;
}

/* clear last level pte, a tlb flush should be followed */
856
static int dma_pte_clear_range(struct dmar_domain *domain,
857 858
				unsigned long start_pfn,
				unsigned long last_pfn)
859
{
860
	int addr_width = agaw_to_width(domain->agaw) - VTD_PAGE_SHIFT;
861
	unsigned int large_page = 1;
862
	struct dma_pte *first_pte, *pte;
863
	int order;
864

865
	BUG_ON(addr_width < BITS_PER_LONG && start_pfn >> addr_width);
866
	BUG_ON(addr_width < BITS_PER_LONG && last_pfn >> addr_width);
867
	BUG_ON(start_pfn > last_pfn);
868

869
	/* we don't need lock here; nobody else touches the iova range */
870
	do {
871 872
		large_page = 1;
		first_pte = pte = dma_pfn_level_pte(domain, start_pfn, 1, &large_page);
873
		if (!pte) {
874
			start_pfn = align_to_level(start_pfn + 1, large_page + 1);
875 876
			continue;
		}
877
		do {
878
			dma_clear_pte(pte);
879
			start_pfn += lvl_to_nr_pages(large_page);
880
			pte++;
881 882
		} while (start_pfn <= last_pfn && !first_pte_in_page(pte));

883 884
		domain_flush_cache(domain, first_pte,
				   (void *)pte - (void *)first_pte);
885 886

	} while (start_pfn && start_pfn <= last_pfn);
887 888 889

	order = (large_page - 1) * 9;
	return order;
890 891 892 893
}

/* free page table pages. last level pte should already be cleared */
static void dma_pte_free_pagetable(struct dmar_domain *domain,
894 895
				   unsigned long start_pfn,
				   unsigned long last_pfn)
896
{
897
	int addr_width = agaw_to_width(domain->agaw) - VTD_PAGE_SHIFT;
898
	struct dma_pte *first_pte, *pte;
899 900
	int total = agaw_to_level(domain->agaw);
	int level;
901
	unsigned long tmp;
902
	int large_page = 2;
903

904 905
	BUG_ON(addr_width < BITS_PER_LONG && start_pfn >> addr_width);
	BUG_ON(addr_width < BITS_PER_LONG && last_pfn >> addr_width);
906
	BUG_ON(start_pfn > last_pfn);
907

908
	/* We don't need lock here; nobody else touches the iova range */
909 910
	level = 2;
	while (level <= total) {
911 912
		tmp = align_to_level(start_pfn, level);

913
		/* If we can't even clear one PTE at this level, we're done */
914
		if (tmp + level_size(level) - 1 > last_pfn)
915 916
			return;

917
		do {
918 919 920 921
			large_page = level;
			first_pte = pte = dma_pfn_level_pte(domain, tmp, level, &large_page);
			if (large_page > level)
				level = large_page + 1;
922 923 924 925
			if (!pte) {
				tmp = align_to_level(tmp + 1, level + 1);
				continue;
			}
926
			do {
927 928 929 930
				if (dma_pte_present(pte)) {
					free_pgtable_page(phys_to_virt(dma_pte_addr(pte)));
					dma_clear_pte(pte);
				}
931 932
				pte++;
				tmp += level_size(level);
933 934 935
			} while (!first_pte_in_page(pte) &&
				 tmp + level_size(level) - 1 <= last_pfn);

936 937 938
			domain_flush_cache(domain, first_pte,
					   (void *)pte - (void *)first_pte);
			
939
		} while (tmp && tmp + level_size(level) - 1 <= last_pfn);
940 941 942
		level++;
	}
	/* free pgd */
943
	if (start_pfn == 0 && last_pfn == DOMAIN_MAX_PFN(domain->gaw)) {
944 945 946 947 948 949 950 951 952 953 954
		free_pgtable_page(domain->pgd);
		domain->pgd = NULL;
	}
}

/* iommu handling */
static int iommu_alloc_root_entry(struct intel_iommu *iommu)
{
	struct root_entry *root;
	unsigned long flags;

955
	root = (struct root_entry *)alloc_pgtable_page(iommu->node);
956 957 958
	if (!root)
		return -ENOMEM;

F
Fenghua Yu 已提交
959
	__iommu_flush_cache(iommu, root, ROOT_SIZE);
960 961 962 963 964 965 966 967 968 969 970

	spin_lock_irqsave(&iommu->lock, flags);
	iommu->root_entry = root;
	spin_unlock_irqrestore(&iommu->lock, flags);

	return 0;
}

static void iommu_set_root_entry(struct intel_iommu *iommu)
{
	void *addr;
971
	u32 sts;
972 973 974 975
	unsigned long flag;

	addr = iommu->root_entry;

976
	raw_spin_lock_irqsave(&iommu->register_lock, flag);
977 978
	dmar_writeq(iommu->reg + DMAR_RTADDR_REG, virt_to_phys(addr));

979
	writel(iommu->gcmd | DMA_GCMD_SRTP, iommu->reg + DMAR_GCMD_REG);
980 981 982

	/* Make sure hardware complete it */
	IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
983
		      readl, (sts & DMA_GSTS_RTPS), sts);
984

985
	raw_spin_unlock_irqrestore(&iommu->register_lock, flag);
986 987 988 989 990 991 992
}

static void iommu_flush_write_buffer(struct intel_iommu *iommu)
{
	u32 val;
	unsigned long flag;

993
	if (!rwbf_quirk && !cap_rwbf(iommu->cap))
994 995
		return;

996
	raw_spin_lock_irqsave(&iommu->register_lock, flag);
997
	writel(iommu->gcmd | DMA_GCMD_WBF, iommu->reg + DMAR_GCMD_REG);
998 999 1000

	/* Make sure hardware complete it */
	IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
1001
		      readl, (!(val & DMA_GSTS_WBFS)), val);
1002

1003
	raw_spin_unlock_irqrestore(&iommu->register_lock, flag);
1004 1005 1006
}

/* return value determine if we need a write buffer flush */
1007 1008 1009
static void __iommu_flush_context(struct intel_iommu *iommu,
				  u16 did, u16 source_id, u8 function_mask,
				  u64 type)
1010 1011 1012 1013 1014 1015 1016 1017 1018 1019 1020 1021 1022 1023 1024 1025 1026 1027 1028 1029
{
	u64 val = 0;
	unsigned long flag;

	switch (type) {
	case DMA_CCMD_GLOBAL_INVL:
		val = DMA_CCMD_GLOBAL_INVL;
		break;
	case DMA_CCMD_DOMAIN_INVL:
		val = DMA_CCMD_DOMAIN_INVL|DMA_CCMD_DID(did);
		break;
	case DMA_CCMD_DEVICE_INVL:
		val = DMA_CCMD_DEVICE_INVL|DMA_CCMD_DID(did)
			| DMA_CCMD_SID(source_id) | DMA_CCMD_FM(function_mask);
		break;
	default:
		BUG();
	}
	val |= DMA_CCMD_ICC;

1030
	raw_spin_lock_irqsave(&iommu->register_lock, flag);
1031 1032 1033 1034 1035 1036
	dmar_writeq(iommu->reg + DMAR_CCMD_REG, val);

	/* Make sure hardware complete it */
	IOMMU_WAIT_OP(iommu, DMAR_CCMD_REG,
		dmar_readq, (!(val & DMA_CCMD_ICC)), val);

1037
	raw_spin_unlock_irqrestore(&iommu->register_lock, flag);
1038 1039 1040
}

/* return value determine if we need a write buffer flush */
1041 1042
static void __iommu_flush_iotlb(struct intel_iommu *iommu, u16 did,
				u64 addr, unsigned int size_order, u64 type)
1043 1044 1045 1046 1047 1048 1049 1050 1051 1052 1053 1054 1055 1056 1057 1058 1059 1060 1061 1062 1063 1064 1065 1066 1067 1068 1069 1070 1071 1072 1073 1074 1075
{
	int tlb_offset = ecap_iotlb_offset(iommu->ecap);
	u64 val = 0, val_iva = 0;
	unsigned long flag;

	switch (type) {
	case DMA_TLB_GLOBAL_FLUSH:
		/* global flush doesn't need set IVA_REG */
		val = DMA_TLB_GLOBAL_FLUSH|DMA_TLB_IVT;
		break;
	case DMA_TLB_DSI_FLUSH:
		val = DMA_TLB_DSI_FLUSH|DMA_TLB_IVT|DMA_TLB_DID(did);
		break;
	case DMA_TLB_PSI_FLUSH:
		val = DMA_TLB_PSI_FLUSH|DMA_TLB_IVT|DMA_TLB_DID(did);
		/* Note: always flush non-leaf currently */
		val_iva = size_order | addr;
		break;
	default:
		BUG();
	}
	/* Note: set drain read/write */
#if 0
	/*
	 * This is probably to be super secure.. Looks like we can
	 * ignore it without any impact.
	 */
	if (cap_read_drain(iommu->cap))
		val |= DMA_TLB_READ_DRAIN;
#endif
	if (cap_write_drain(iommu->cap))
		val |= DMA_TLB_WRITE_DRAIN;

1076
	raw_spin_lock_irqsave(&iommu->register_lock, flag);
1077 1078 1079 1080 1081 1082 1083 1084 1085
	/* Note: Only uses first TLB reg currently */
	if (val_iva)
		dmar_writeq(iommu->reg + tlb_offset, val_iva);
	dmar_writeq(iommu->reg + tlb_offset + 8, val);

	/* Make sure hardware complete it */
	IOMMU_WAIT_OP(iommu, tlb_offset + 8,
		dmar_readq, (!(val & DMA_TLB_IVT)), val);

1086
	raw_spin_unlock_irqrestore(&iommu->register_lock, flag);
1087 1088 1089 1090 1091 1092

	/* check IOTLB invalidation granularity */
	if (DMA_TLB_IAIG(val) == 0)
		printk(KERN_ERR"IOMMU: flush IOTLB failed\n");
	if (DMA_TLB_IAIG(val) != DMA_TLB_IIRG(type))
		pr_debug("IOMMU: tlb flush request %Lx, actual %Lx\n",
F
Fenghua Yu 已提交
1093 1094
			(unsigned long long)DMA_TLB_IIRG(type),
			(unsigned long long)DMA_TLB_IAIG(val));
1095 1096
}

Y
Yu Zhao 已提交
1097 1098 1099 1100 1101 1102 1103 1104 1105 1106 1107 1108 1109 1110 1111 1112 1113 1114 1115 1116 1117 1118 1119 1120 1121 1122 1123 1124 1125 1126 1127 1128 1129 1130 1131 1132 1133
static struct device_domain_info *iommu_support_dev_iotlb(
	struct dmar_domain *domain, int segment, u8 bus, u8 devfn)
{
	int found = 0;
	unsigned long flags;
	struct device_domain_info *info;
	struct intel_iommu *iommu = device_to_iommu(segment, bus, devfn);

	if (!ecap_dev_iotlb_support(iommu->ecap))
		return NULL;

	if (!iommu->qi)
		return NULL;

	spin_lock_irqsave(&device_domain_lock, flags);
	list_for_each_entry(info, &domain->devices, link)
		if (info->bus == bus && info->devfn == devfn) {
			found = 1;
			break;
		}
	spin_unlock_irqrestore(&device_domain_lock, flags);

	if (!found || !info->dev)
		return NULL;

	if (!pci_find_ext_capability(info->dev, PCI_EXT_CAP_ID_ATS))
		return NULL;

	if (!dmar_find_matched_atsr_unit(info->dev))
		return NULL;

	info->iommu = iommu;

	return info;
}

static void iommu_enable_dev_iotlb(struct device_domain_info *info)
1134
{
Y
Yu Zhao 已提交
1135 1136 1137 1138 1139 1140 1141 1142 1143 1144 1145 1146 1147 1148 1149 1150 1151 1152 1153 1154 1155 1156 1157 1158 1159 1160 1161 1162 1163 1164 1165 1166 1167
	if (!info)
		return;

	pci_enable_ats(info->dev, VTD_PAGE_SHIFT);
}

static void iommu_disable_dev_iotlb(struct device_domain_info *info)
{
	if (!info->dev || !pci_ats_enabled(info->dev))
		return;

	pci_disable_ats(info->dev);
}

static void iommu_flush_dev_iotlb(struct dmar_domain *domain,
				  u64 addr, unsigned mask)
{
	u16 sid, qdep;
	unsigned long flags;
	struct device_domain_info *info;

	spin_lock_irqsave(&device_domain_lock, flags);
	list_for_each_entry(info, &domain->devices, link) {
		if (!info->dev || !pci_ats_enabled(info->dev))
			continue;

		sid = info->bus << 8 | info->devfn;
		qdep = pci_ats_queue_depth(info->dev);
		qi_flush_dev_iotlb(info->iommu, sid, qdep, addr, mask);
	}
	spin_unlock_irqrestore(&device_domain_lock, flags);
}

1168
static void iommu_flush_iotlb_psi(struct intel_iommu *iommu, u16 did,
1169
				  unsigned long pfn, unsigned int pages, int map)
1170
{
1171
	unsigned int mask = ilog2(__roundup_pow_of_two(pages));
1172
	uint64_t addr = (uint64_t)pfn << VTD_PAGE_SHIFT;
1173 1174 1175 1176

	BUG_ON(pages == 0);

	/*
1177 1178
	 * Fallback to domain selective flush if no PSI support or the size is
	 * too big.
1179 1180 1181
	 * PSI requires page size to be 2 ^ x, and the base address is naturally
	 * aligned to the size
	 */
1182 1183
	if (!cap_pgsel_inv(iommu->cap) || mask > cap_max_amask_val(iommu->cap))
		iommu->flush.flush_iotlb(iommu, did, 0, 0,
1184
						DMA_TLB_DSI_FLUSH);
1185 1186 1187
	else
		iommu->flush.flush_iotlb(iommu, did, addr, mask,
						DMA_TLB_PSI_FLUSH);
1188 1189

	/*
1190 1191
	 * In caching mode, changes of pages from non-present to present require
	 * flush. However, device IOTLB doesn't need to be flushed in this case.
1192
	 */
1193
	if (!cap_caching_mode(iommu->cap) || !map)
Y
Yu Zhao 已提交
1194
		iommu_flush_dev_iotlb(iommu->domains[did], addr, mask);
1195 1196
}

M
mark gross 已提交
1197 1198 1199 1200 1201
static void iommu_disable_protect_mem_regions(struct intel_iommu *iommu)
{
	u32 pmen;
	unsigned long flags;

1202
	raw_spin_lock_irqsave(&iommu->register_lock, flags);
M
mark gross 已提交
1203 1204 1205 1206 1207 1208 1209 1210
	pmen = readl(iommu->reg + DMAR_PMEN_REG);
	pmen &= ~DMA_PMEN_EPM;
	writel(pmen, iommu->reg + DMAR_PMEN_REG);

	/* wait for the protected region status bit to clear */
	IOMMU_WAIT_OP(iommu, DMAR_PMEN_REG,
		readl, !(pmen & DMA_PMEN_PRS), pmen);

1211
	raw_spin_unlock_irqrestore(&iommu->register_lock, flags);
M
mark gross 已提交
1212 1213
}

1214 1215 1216 1217 1218
static int iommu_enable_translation(struct intel_iommu *iommu)
{
	u32 sts;
	unsigned long flags;

1219
	raw_spin_lock_irqsave(&iommu->register_lock, flags);
1220 1221
	iommu->gcmd |= DMA_GCMD_TE;
	writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG);
1222 1223 1224

	/* Make sure hardware complete it */
	IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
1225
		      readl, (sts & DMA_GSTS_TES), sts);
1226

1227
	raw_spin_unlock_irqrestore(&iommu->register_lock, flags);
1228 1229 1230 1231 1232 1233 1234 1235
	return 0;
}

static int iommu_disable_translation(struct intel_iommu *iommu)
{
	u32 sts;
	unsigned long flag;

1236
	raw_spin_lock_irqsave(&iommu->register_lock, flag);
1237 1238 1239 1240 1241
	iommu->gcmd &= ~DMA_GCMD_TE;
	writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG);

	/* Make sure hardware complete it */
	IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
1242
		      readl, (!(sts & DMA_GSTS_TES)), sts);
1243

1244
	raw_spin_unlock_irqrestore(&iommu->register_lock, flag);
1245 1246 1247
	return 0;
}

1248

1249 1250 1251 1252 1253 1254
static int iommu_init_domains(struct intel_iommu *iommu)
{
	unsigned long ndomains;
	unsigned long nlongs;

	ndomains = cap_ndoms(iommu->cap);
M
Masanari Iida 已提交
1255
	pr_debug("IOMMU %d: Number of Domains supported <%ld>\n", iommu->seq_id,
Y
Yinghai Lu 已提交
1256
			ndomains);
1257 1258
	nlongs = BITS_TO_LONGS(ndomains);

1259 1260
	spin_lock_init(&iommu->lock);

1261 1262 1263 1264 1265 1266 1267 1268 1269 1270 1271 1272 1273 1274 1275 1276 1277 1278 1279 1280 1281 1282 1283 1284 1285 1286
	/* TBD: there might be 64K domains,
	 * consider other allocation for future chip
	 */
	iommu->domain_ids = kcalloc(nlongs, sizeof(unsigned long), GFP_KERNEL);
	if (!iommu->domain_ids) {
		printk(KERN_ERR "Allocating domain id array failed\n");
		return -ENOMEM;
	}
	iommu->domains = kcalloc(ndomains, sizeof(struct dmar_domain *),
			GFP_KERNEL);
	if (!iommu->domains) {
		printk(KERN_ERR "Allocating domain array failed\n");
		return -ENOMEM;
	}

	/*
	 * if Caching mode is set, then invalid translations are tagged
	 * with domainid 0. Hence we need to pre-allocate it.
	 */
	if (cap_caching_mode(iommu->cap))
		set_bit(0, iommu->domain_ids);
	return 0;
}


static void domain_exit(struct dmar_domain *domain);
1287
static void vm_domain_exit(struct dmar_domain *domain);
1288 1289

void free_dmar_iommu(struct intel_iommu *iommu)
1290 1291 1292
{
	struct dmar_domain *domain;
	int i;
1293
	unsigned long flags;
1294

1295
	if ((iommu->domains) && (iommu->domain_ids)) {
1296
		for_each_set_bit(i, iommu->domain_ids, cap_ndoms(iommu->cap)) {
1297 1298 1299 1300 1301 1302 1303 1304 1305 1306 1307
			domain = iommu->domains[i];
			clear_bit(i, iommu->domain_ids);

			spin_lock_irqsave(&domain->iommu_lock, flags);
			if (--domain->iommu_count == 0) {
				if (domain->flags & DOMAIN_FLAG_VIRTUAL_MACHINE)
					vm_domain_exit(domain);
				else
					domain_exit(domain);
			}
			spin_unlock_irqrestore(&domain->iommu_lock, flags);
1308
		}
1309 1310 1311 1312 1313 1314
	}

	if (iommu->gcmd & DMA_GCMD_TE)
		iommu_disable_translation(iommu);

	if (iommu->irq) {
1315
		irq_set_handler_data(iommu->irq, NULL);
1316 1317 1318 1319 1320 1321 1322 1323
		/* This will mask the irq */
		free_irq(iommu->irq, iommu);
		destroy_irq(iommu->irq);
	}

	kfree(iommu->domains);
	kfree(iommu->domain_ids);

W
Weidong Han 已提交
1324 1325 1326 1327 1328 1329 1330 1331 1332 1333 1334
	g_iommus[iommu->seq_id] = NULL;

	/* if all iommus are freed, free g_iommus */
	for (i = 0; i < g_num_of_iommus; i++) {
		if (g_iommus[i])
			break;
	}

	if (i == g_num_of_iommus)
		kfree(g_iommus);

1335 1336 1337 1338
	/* free context mapping */
	free_context_table(iommu);
}

1339
static struct dmar_domain *alloc_domain(void)
1340 1341 1342 1343 1344 1345 1346
{
	struct dmar_domain *domain;

	domain = alloc_domain_mem();
	if (!domain)
		return NULL;

1347
	domain->nid = -1;
1348
	memset(domain->iommu_bmp, 0, sizeof(domain->iommu_bmp));
1349 1350 1351 1352 1353 1354 1355 1356 1357 1358 1359 1360
	domain->flags = 0;

	return domain;
}

static int iommu_attach_domain(struct dmar_domain *domain,
			       struct intel_iommu *iommu)
{
	int num;
	unsigned long ndomains;
	unsigned long flags;

1361 1362 1363
	ndomains = cap_ndoms(iommu->cap);

	spin_lock_irqsave(&iommu->lock, flags);
1364

1365 1366 1367 1368
	num = find_first_zero_bit(iommu->domain_ids, ndomains);
	if (num >= ndomains) {
		spin_unlock_irqrestore(&iommu->lock, flags);
		printk(KERN_ERR "IOMMU: no free domain ids\n");
1369
		return -ENOMEM;
1370 1371 1372
	}

	domain->id = num;
1373
	set_bit(num, iommu->domain_ids);
1374
	set_bit(iommu->seq_id, domain->iommu_bmp);
1375 1376 1377
	iommu->domains[num] = domain;
	spin_unlock_irqrestore(&iommu->lock, flags);

1378
	return 0;
1379 1380
}

1381 1382
static void iommu_detach_domain(struct dmar_domain *domain,
				struct intel_iommu *iommu)
1383 1384
{
	unsigned long flags;
1385 1386
	int num, ndomains;
	int found = 0;
1387

1388
	spin_lock_irqsave(&iommu->lock, flags);
1389
	ndomains = cap_ndoms(iommu->cap);
1390
	for_each_set_bit(num, iommu->domain_ids, ndomains) {
1391 1392 1393 1394 1395 1396 1397 1398
		if (iommu->domains[num] == domain) {
			found = 1;
			break;
		}
	}

	if (found) {
		clear_bit(num, iommu->domain_ids);
1399
		clear_bit(iommu->seq_id, domain->iommu_bmp);
1400 1401
		iommu->domains[num] = NULL;
	}
1402
	spin_unlock_irqrestore(&iommu->lock, flags);
1403 1404 1405
}

static struct iova_domain reserved_iova_list;
M
Mark Gross 已提交
1406
static struct lock_class_key reserved_rbtree_key;
1407

1408
static int dmar_init_reserved_ranges(void)
1409 1410 1411 1412 1413
{
	struct pci_dev *pdev = NULL;
	struct iova *iova;
	int i;

D
David Miller 已提交
1414
	init_iova_domain(&reserved_iova_list, DMA_32BIT_PFN);
1415

M
Mark Gross 已提交
1416 1417 1418
	lockdep_set_class(&reserved_iova_list.iova_rbtree_lock,
		&reserved_rbtree_key);

1419 1420 1421
	/* IOAPIC ranges shouldn't be accessed by DMA */
	iova = reserve_iova(&reserved_iova_list, IOVA_PFN(IOAPIC_RANGE_START),
		IOVA_PFN(IOAPIC_RANGE_END));
1422
	if (!iova) {
1423
		printk(KERN_ERR "Reserve IOAPIC range failed\n");
1424 1425
		return -ENODEV;
	}
1426 1427 1428 1429 1430 1431 1432 1433 1434

	/* Reserve all PCI MMIO to avoid peer-to-peer access */
	for_each_pci_dev(pdev) {
		struct resource *r;

		for (i = 0; i < PCI_NUM_RESOURCES; i++) {
			r = &pdev->resource[i];
			if (!r->flags || !(r->flags & IORESOURCE_MEM))
				continue;
1435 1436 1437
			iova = reserve_iova(&reserved_iova_list,
					    IOVA_PFN(r->start),
					    IOVA_PFN(r->end));
1438
			if (!iova) {
1439
				printk(KERN_ERR "Reserve iova failed\n");
1440 1441
				return -ENODEV;
			}
1442 1443
		}
	}
1444
	return 0;
1445 1446 1447 1448 1449 1450 1451 1452 1453 1454 1455 1456 1457 1458 1459 1460 1461 1462 1463 1464 1465 1466 1467 1468 1469 1470 1471
}

static void domain_reserve_special_ranges(struct dmar_domain *domain)
{
	copy_reserved_iova(&reserved_iova_list, &domain->iovad);
}

static inline int guestwidth_to_adjustwidth(int gaw)
{
	int agaw;
	int r = (gaw - 12) % 9;

	if (r == 0)
		agaw = gaw;
	else
		agaw = gaw + 9 - r;
	if (agaw > 64)
		agaw = 64;
	return agaw;
}

static int domain_init(struct dmar_domain *domain, int guest_width)
{
	struct intel_iommu *iommu;
	int adjust_width, agaw;
	unsigned long sagaw;

D
David Miller 已提交
1472
	init_iova_domain(&domain->iovad, DMA_32BIT_PFN);
1473
	spin_lock_init(&domain->iommu_lock);
1474 1475 1476 1477

	domain_reserve_special_ranges(domain);

	/* calculate AGAW */
1478
	iommu = domain_get_iommu(domain);
1479 1480 1481 1482 1483 1484 1485 1486 1487 1488 1489 1490 1491 1492 1493 1494
	if (guest_width > cap_mgaw(iommu->cap))
		guest_width = cap_mgaw(iommu->cap);
	domain->gaw = guest_width;
	adjust_width = guestwidth_to_adjustwidth(guest_width);
	agaw = width_to_agaw(adjust_width);
	sagaw = cap_sagaw(iommu->cap);
	if (!test_bit(agaw, &sagaw)) {
		/* hardware doesn't support it, choose a bigger one */
		pr_debug("IOMMU: hardware doesn't support agaw %d\n", agaw);
		agaw = find_next_bit(&sagaw, 5, agaw);
		if (agaw >= 5)
			return -ENODEV;
	}
	domain->agaw = agaw;
	INIT_LIST_HEAD(&domain->devices);

W
Weidong Han 已提交
1495 1496 1497 1498 1499
	if (ecap_coherent(iommu->ecap))
		domain->iommu_coherency = 1;
	else
		domain->iommu_coherency = 0;

1500 1501 1502 1503 1504
	if (ecap_sc_support(iommu->ecap))
		domain->iommu_snooping = 1;
	else
		domain->iommu_snooping = 0;

1505
	domain->iommu_superpage = fls(cap_super_page_val(iommu->cap));
1506
	domain->iommu_count = 1;
1507
	domain->nid = iommu->node;
1508

1509
	/* always allocate the top pgd */
1510
	domain->pgd = (struct dma_pte *)alloc_pgtable_page(domain->nid);
1511 1512
	if (!domain->pgd)
		return -ENOMEM;
F
Fenghua Yu 已提交
1513
	__iommu_flush_cache(iommu, domain->pgd, PAGE_SIZE);
1514 1515 1516 1517 1518
	return 0;
}

static void domain_exit(struct dmar_domain *domain)
{
1519 1520
	struct dmar_drhd_unit *drhd;
	struct intel_iommu *iommu;
1521 1522 1523 1524 1525

	/* Domain 0 is reserved, so dont process it */
	if (!domain)
		return;

1526 1527 1528 1529
	/* Flush any lazy unmaps that may reference this domain */
	if (!intel_iommu_strict)
		flush_unmaps_timeout(0);

1530 1531 1532 1533 1534
	domain_remove_dev_info(domain);
	/* destroy iovas */
	put_iova_domain(&domain->iovad);

	/* clear ptes */
1535
	dma_pte_clear_range(domain, 0, DOMAIN_MAX_PFN(domain->gaw));
1536 1537

	/* free page tables */
1538
	dma_pte_free_pagetable(domain, 0, DOMAIN_MAX_PFN(domain->gaw));
1539

1540
	for_each_active_iommu(iommu, drhd)
1541
		if (test_bit(iommu->seq_id, domain->iommu_bmp))
1542 1543
			iommu_detach_domain(domain, iommu);

1544 1545 1546
	free_domain_mem(domain);
}

F
Fenghua Yu 已提交
1547 1548
static int domain_context_mapping_one(struct dmar_domain *domain, int segment,
				 u8 bus, u8 devfn, int translation)
1549 1550 1551
{
	struct context_entry *context;
	unsigned long flags;
W
Weidong Han 已提交
1552
	struct intel_iommu *iommu;
1553 1554 1555 1556 1557
	struct dma_pte *pgd;
	unsigned long num;
	unsigned long ndomains;
	int id;
	int agaw;
Y
Yu Zhao 已提交
1558
	struct device_domain_info *info = NULL;
1559 1560 1561

	pr_debug("Set context mapping for %02x:%02x.%d\n",
		bus, PCI_SLOT(devfn), PCI_FUNC(devfn));
F
Fenghua Yu 已提交
1562

1563
	BUG_ON(!domain->pgd);
F
Fenghua Yu 已提交
1564 1565
	BUG_ON(translation != CONTEXT_TT_PASS_THROUGH &&
	       translation != CONTEXT_TT_MULTI_LEVEL);
W
Weidong Han 已提交
1566

1567
	iommu = device_to_iommu(segment, bus, devfn);
W
Weidong Han 已提交
1568 1569 1570
	if (!iommu)
		return -ENODEV;

1571 1572 1573 1574
	context = device_to_context_entry(iommu, bus, devfn);
	if (!context)
		return -ENOMEM;
	spin_lock_irqsave(&iommu->lock, flags);
1575
	if (context_present(context)) {
1576 1577 1578 1579
		spin_unlock_irqrestore(&iommu->lock, flags);
		return 0;
	}

1580 1581 1582
	id = domain->id;
	pgd = domain->pgd;

1583 1584
	if (domain->flags & DOMAIN_FLAG_VIRTUAL_MACHINE ||
	    domain->flags & DOMAIN_FLAG_STATIC_IDENTITY) {
1585 1586 1587 1588
		int found = 0;

		/* find an available domain id for this device in iommu */
		ndomains = cap_ndoms(iommu->cap);
1589
		for_each_set_bit(num, iommu->domain_ids, ndomains) {
1590 1591 1592 1593 1594 1595 1596 1597 1598 1599 1600 1601 1602 1603 1604 1605 1606 1607 1608 1609 1610 1611
			if (iommu->domains[num] == domain) {
				id = num;
				found = 1;
				break;
			}
		}

		if (found == 0) {
			num = find_first_zero_bit(iommu->domain_ids, ndomains);
			if (num >= ndomains) {
				spin_unlock_irqrestore(&iommu->lock, flags);
				printk(KERN_ERR "IOMMU: no free domain ids\n");
				return -EFAULT;
			}

			set_bit(num, iommu->domain_ids);
			iommu->domains[num] = domain;
			id = num;
		}

		/* Skip top levels of page tables for
		 * iommu which has less agaw than default.
1612
		 * Unnecessary for PT mode.
1613
		 */
1614 1615 1616 1617 1618 1619 1620
		if (translation != CONTEXT_TT_PASS_THROUGH) {
			for (agaw = domain->agaw; agaw != iommu->agaw; agaw--) {
				pgd = phys_to_virt(dma_pte_addr(pgd));
				if (!dma_pte_present(pgd)) {
					spin_unlock_irqrestore(&iommu->lock, flags);
					return -ENOMEM;
				}
1621 1622 1623 1624 1625
			}
		}
	}

	context_set_domain_id(context, id);
F
Fenghua Yu 已提交
1626

Y
Yu Zhao 已提交
1627 1628 1629 1630 1631
	if (translation != CONTEXT_TT_PASS_THROUGH) {
		info = iommu_support_dev_iotlb(domain, segment, bus, devfn);
		translation = info ? CONTEXT_TT_DEV_IOTLB :
				     CONTEXT_TT_MULTI_LEVEL;
	}
F
Fenghua Yu 已提交
1632 1633 1634 1635
	/*
	 * In pass through mode, AW must be programmed to indicate the largest
	 * AGAW value supported by hardware. And ASR is ignored by hardware.
	 */
Y
Yu Zhao 已提交
1636
	if (unlikely(translation == CONTEXT_TT_PASS_THROUGH))
F
Fenghua Yu 已提交
1637
		context_set_address_width(context, iommu->msagaw);
Y
Yu Zhao 已提交
1638 1639 1640 1641
	else {
		context_set_address_root(context, virt_to_phys(pgd));
		context_set_address_width(context, iommu->agaw);
	}
F
Fenghua Yu 已提交
1642 1643

	context_set_translation_type(context, translation);
1644 1645
	context_set_fault_enable(context);
	context_set_present(context);
W
Weidong Han 已提交
1646
	domain_flush_cache(domain, context, sizeof(*context));
1647

1648 1649 1650 1651 1652 1653 1654 1655 1656 1657 1658
	/*
	 * It's a non-present to present mapping. If hardware doesn't cache
	 * non-present entry we only need to flush the write-buffer. If the
	 * _does_ cache non-present entries, then it does so in the special
	 * domain #0, which we have to flush:
	 */
	if (cap_caching_mode(iommu->cap)) {
		iommu->flush.flush_context(iommu, 0,
					   (((u16)bus) << 8) | devfn,
					   DMA_CCMD_MASK_NOBIT,
					   DMA_CCMD_DEVICE_INVL);
1659
		iommu->flush.flush_iotlb(iommu, domain->id, 0, 0, DMA_TLB_DSI_FLUSH);
1660
	} else {
1661
		iommu_flush_write_buffer(iommu);
1662
	}
Y
Yu Zhao 已提交
1663
	iommu_enable_dev_iotlb(info);
1664
	spin_unlock_irqrestore(&iommu->lock, flags);
1665 1666

	spin_lock_irqsave(&domain->iommu_lock, flags);
1667
	if (!test_and_set_bit(iommu->seq_id, domain->iommu_bmp)) {
1668
		domain->iommu_count++;
1669 1670
		if (domain->iommu_count == 1)
			domain->nid = iommu->node;
1671
		domain_update_iommu_cap(domain);
1672 1673
	}
	spin_unlock_irqrestore(&domain->iommu_lock, flags);
1674 1675 1676 1677
	return 0;
}

static int
F
Fenghua Yu 已提交
1678 1679
domain_context_mapping(struct dmar_domain *domain, struct pci_dev *pdev,
			int translation)
1680 1681 1682 1683
{
	int ret;
	struct pci_dev *tmp, *parent;

1684
	ret = domain_context_mapping_one(domain, pci_domain_nr(pdev->bus),
F
Fenghua Yu 已提交
1685 1686
					 pdev->bus->number, pdev->devfn,
					 translation);
1687 1688 1689 1690 1691 1692 1693 1694 1695 1696
	if (ret)
		return ret;

	/* dependent device mapping */
	tmp = pci_find_upstream_pcie_bridge(pdev);
	if (!tmp)
		return 0;
	/* Secondary interface's bus number and devfn 0 */
	parent = pdev->bus->self;
	while (parent != tmp) {
1697 1698 1699
		ret = domain_context_mapping_one(domain,
						 pci_domain_nr(parent->bus),
						 parent->bus->number,
F
Fenghua Yu 已提交
1700
						 parent->devfn, translation);
1701 1702 1703 1704
		if (ret)
			return ret;
		parent = parent->bus->self;
	}
1705
	if (pci_is_pcie(tmp)) /* this is a PCIe-to-PCI bridge */
1706
		return domain_context_mapping_one(domain,
1707
					pci_domain_nr(tmp->subordinate),
F
Fenghua Yu 已提交
1708 1709
					tmp->subordinate->number, 0,
					translation);
1710 1711
	else /* this is a legacy PCI bridge */
		return domain_context_mapping_one(domain,
1712 1713
						  pci_domain_nr(tmp->bus),
						  tmp->bus->number,
F
Fenghua Yu 已提交
1714 1715
						  tmp->devfn,
						  translation);
1716 1717
}

W
Weidong Han 已提交
1718
static int domain_context_mapped(struct pci_dev *pdev)
1719 1720 1721
{
	int ret;
	struct pci_dev *tmp, *parent;
W
Weidong Han 已提交
1722 1723
	struct intel_iommu *iommu;

1724 1725
	iommu = device_to_iommu(pci_domain_nr(pdev->bus), pdev->bus->number,
				pdev->devfn);
W
Weidong Han 已提交
1726 1727
	if (!iommu)
		return -ENODEV;
1728

1729
	ret = device_context_mapped(iommu, pdev->bus->number, pdev->devfn);
1730 1731 1732 1733 1734 1735 1736 1737 1738
	if (!ret)
		return ret;
	/* dependent device mapping */
	tmp = pci_find_upstream_pcie_bridge(pdev);
	if (!tmp)
		return ret;
	/* Secondary interface's bus number and devfn 0 */
	parent = pdev->bus->self;
	while (parent != tmp) {
1739
		ret = device_context_mapped(iommu, parent->bus->number,
1740
					    parent->devfn);
1741 1742 1743 1744
		if (!ret)
			return ret;
		parent = parent->bus->self;
	}
1745
	if (pci_is_pcie(tmp))
1746 1747
		return device_context_mapped(iommu, tmp->subordinate->number,
					     0);
1748
	else
1749 1750
		return device_context_mapped(iommu, tmp->bus->number,
					     tmp->devfn);
1751 1752
}

1753 1754 1755 1756 1757 1758 1759 1760
/* Returns a number of VTD pages, but aligned to MM page size */
static inline unsigned long aligned_nrpages(unsigned long host_addr,
					    size_t size)
{
	host_addr &= ~PAGE_MASK;
	return PAGE_ALIGN(host_addr + size) >> VTD_PAGE_SHIFT;
}

1761 1762 1763 1764 1765 1766 1767 1768 1769 1770 1771 1772 1773 1774 1775 1776 1777 1778 1779 1780 1781 1782 1783 1784 1785 1786 1787 1788
/* Return largest possible superpage level for a given mapping */
static inline int hardware_largepage_caps(struct dmar_domain *domain,
					  unsigned long iov_pfn,
					  unsigned long phy_pfn,
					  unsigned long pages)
{
	int support, level = 1;
	unsigned long pfnmerge;

	support = domain->iommu_superpage;

	/* To use a large page, the virtual *and* physical addresses
	   must be aligned to 2MiB/1GiB/etc. Lower bits set in either
	   of them will mean we have to use smaller pages. So just
	   merge them and check both at once. */
	pfnmerge = iov_pfn | phy_pfn;

	while (support && !(pfnmerge & ~VTD_STRIDE_MASK)) {
		pages >>= VTD_STRIDE_SHIFT;
		if (!pages)
			break;
		pfnmerge >>= VTD_STRIDE_SHIFT;
		level++;
		support--;
	}
	return level;
}

1789 1790 1791
static int __domain_mapping(struct dmar_domain *domain, unsigned long iov_pfn,
			    struct scatterlist *sg, unsigned long phys_pfn,
			    unsigned long nr_pages, int prot)
1792 1793
{
	struct dma_pte *first_pte = NULL, *pte = NULL;
1794
	phys_addr_t uninitialized_var(pteval);
1795
	int addr_width = agaw_to_width(domain->agaw) - VTD_PAGE_SHIFT;
1796
	unsigned long sg_res;
1797 1798
	unsigned int largepage_lvl = 0;
	unsigned long lvl_pages = 0;
1799 1800 1801 1802 1803 1804 1805 1806

	BUG_ON(addr_width < BITS_PER_LONG && (iov_pfn + nr_pages - 1) >> addr_width);

	if ((prot & (DMA_PTE_READ|DMA_PTE_WRITE)) == 0)
		return -EINVAL;

	prot &= DMA_PTE_READ | DMA_PTE_WRITE | DMA_PTE_SNP;

1807 1808 1809 1810 1811 1812 1813
	if (sg)
		sg_res = 0;
	else {
		sg_res = nr_pages + 1;
		pteval = ((phys_addr_t)phys_pfn << VTD_PAGE_SHIFT) | prot;
	}

1814
	while (nr_pages > 0) {
1815 1816
		uint64_t tmp;

1817
		if (!sg_res) {
1818
			sg_res = aligned_nrpages(sg->offset, sg->length);
1819 1820 1821
			sg->dma_address = ((dma_addr_t)iov_pfn << VTD_PAGE_SHIFT) + sg->offset;
			sg->dma_length = sg->length;
			pteval = page_to_phys(sg_page(sg)) | prot;
1822
			phys_pfn = pteval >> VTD_PAGE_SHIFT;
1823
		}
1824

1825
		if (!pte) {
1826 1827 1828
			largepage_lvl = hardware_largepage_caps(domain, iov_pfn, phys_pfn, sg_res);

			first_pte = pte = pfn_to_dma_pte(domain, iov_pfn, largepage_lvl);
1829 1830
			if (!pte)
				return -ENOMEM;
1831
			/* It is large page*/
1832
			if (largepage_lvl > 1) {
1833
				pteval |= DMA_PTE_LARGE_PAGE;
1834 1835 1836 1837 1838 1839 1840
				/* Ensure that old small page tables are removed to make room
				   for superpage, if they exist. */
				dma_pte_clear_range(domain, iov_pfn,
						    iov_pfn + lvl_to_nr_pages(largepage_lvl) - 1);
				dma_pte_free_pagetable(domain, iov_pfn,
						       iov_pfn + lvl_to_nr_pages(largepage_lvl) - 1);
			} else {
1841
				pteval &= ~(uint64_t)DMA_PTE_LARGE_PAGE;
1842
			}
1843

1844 1845 1846 1847
		}
		/* We don't need lock here, nobody else
		 * touches the iova range
		 */
1848
		tmp = cmpxchg64_local(&pte->val, 0ULL, pteval);
1849
		if (tmp) {
1850
			static int dumps = 5;
1851 1852
			printk(KERN_CRIT "ERROR: DMA PTE for vPFN 0x%lx already set (to %llx not %llx)\n",
			       iov_pfn, tmp, (unsigned long long)pteval);
1853 1854 1855 1856 1857 1858
			if (dumps) {
				dumps--;
				debug_dma_dump_mappings(NULL);
			}
			WARN_ON(1);
		}
1859 1860 1861 1862 1863 1864 1865 1866 1867 1868 1869 1870 1871 1872 1873 1874 1875 1876 1877 1878 1879 1880 1881

		lvl_pages = lvl_to_nr_pages(largepage_lvl);

		BUG_ON(nr_pages < lvl_pages);
		BUG_ON(sg_res < lvl_pages);

		nr_pages -= lvl_pages;
		iov_pfn += lvl_pages;
		phys_pfn += lvl_pages;
		pteval += lvl_pages * VTD_PAGE_SIZE;
		sg_res -= lvl_pages;

		/* If the next PTE would be the first in a new page, then we
		   need to flush the cache on the entries we've just written.
		   And then we'll need to recalculate 'pte', so clear it and
		   let it get set again in the if (!pte) block above.

		   If we're done (!nr_pages) we need to flush the cache too.

		   Also if we've been setting superpages, we may need to
		   recalculate 'pte' and switch back to smaller pages for the
		   end of the mapping, if the trailing size is not enough to
		   use another superpage (i.e. sg_res < lvl_pages). */
1882
		pte++;
1883 1884
		if (!nr_pages || first_pte_in_page(pte) ||
		    (largepage_lvl > 1 && sg_res < lvl_pages)) {
1885 1886 1887 1888
			domain_flush_cache(domain, first_pte,
					   (void *)pte - (void *)first_pte);
			pte = NULL;
		}
1889 1890

		if (!sg_res && nr_pages)
1891 1892 1893 1894 1895
			sg = sg_next(sg);
	}
	return 0;
}

1896 1897 1898
static inline int domain_sg_mapping(struct dmar_domain *domain, unsigned long iov_pfn,
				    struct scatterlist *sg, unsigned long nr_pages,
				    int prot)
1899
{
1900 1901
	return __domain_mapping(domain, iov_pfn, sg, 0, nr_pages, prot);
}
1902

1903 1904 1905 1906 1907
static inline int domain_pfn_mapping(struct dmar_domain *domain, unsigned long iov_pfn,
				     unsigned long phys_pfn, unsigned long nr_pages,
				     int prot)
{
	return __domain_mapping(domain, iov_pfn, NULL, phys_pfn, nr_pages, prot);
1908 1909
}

1910
static void iommu_detach_dev(struct intel_iommu *iommu, u8 bus, u8 devfn)
1911
{
1912 1913
	if (!iommu)
		return;
1914 1915 1916

	clear_context_table(iommu, bus, devfn);
	iommu->flush.flush_context(iommu, 0, 0, 0,
1917
					   DMA_CCMD_GLOBAL_INVL);
1918
	iommu->flush.flush_iotlb(iommu, 0, 0, 0, DMA_TLB_GLOBAL_FLUSH);
1919 1920
}

1921 1922 1923 1924 1925 1926 1927 1928 1929
static inline void unlink_domain_info(struct device_domain_info *info)
{
	assert_spin_locked(&device_domain_lock);
	list_del(&info->link);
	list_del(&info->global);
	if (info->dev)
		info->dev->dev.archdata.iommu = NULL;
}

1930 1931 1932 1933
static void domain_remove_dev_info(struct dmar_domain *domain)
{
	struct device_domain_info *info;
	unsigned long flags;
1934
	struct intel_iommu *iommu;
1935 1936 1937 1938 1939

	spin_lock_irqsave(&device_domain_lock, flags);
	while (!list_empty(&domain->devices)) {
		info = list_entry(domain->devices.next,
			struct device_domain_info, link);
1940
		unlink_domain_info(info);
1941 1942
		spin_unlock_irqrestore(&device_domain_lock, flags);

Y
Yu Zhao 已提交
1943
		iommu_disable_dev_iotlb(info);
1944
		iommu = device_to_iommu(info->segment, info->bus, info->devfn);
1945
		iommu_detach_dev(iommu, info->bus, info->devfn);
1946 1947 1948 1949 1950 1951 1952 1953 1954
		free_devinfo_mem(info);

		spin_lock_irqsave(&device_domain_lock, flags);
	}
	spin_unlock_irqrestore(&device_domain_lock, flags);
}

/*
 * find_domain
1955
 * Note: we use struct pci_dev->dev.archdata.iommu stores the info
1956
 */
K
Kay, Allen M 已提交
1957
static struct dmar_domain *
1958 1959 1960 1961 1962
find_domain(struct pci_dev *pdev)
{
	struct device_domain_info *info;

	/* No lock here, assumes no domain exit in normal case */
1963
	info = pdev->dev.archdata.iommu;
1964 1965 1966 1967 1968 1969 1970 1971 1972 1973 1974 1975 1976 1977 1978
	if (info)
		return info->domain;
	return NULL;
}

/* domain is initialized */
static struct dmar_domain *get_domain_for_dev(struct pci_dev *pdev, int gaw)
{
	struct dmar_domain *domain, *found = NULL;
	struct intel_iommu *iommu;
	struct dmar_drhd_unit *drhd;
	struct device_domain_info *info, *tmp;
	struct pci_dev *dev_tmp;
	unsigned long flags;
	int bus = 0, devfn = 0;
1979
	int segment;
1980
	int ret;
1981 1982 1983 1984 1985

	domain = find_domain(pdev);
	if (domain)
		return domain;

1986 1987
	segment = pci_domain_nr(pdev->bus);

1988 1989
	dev_tmp = pci_find_upstream_pcie_bridge(pdev);
	if (dev_tmp) {
1990
		if (pci_is_pcie(dev_tmp)) {
1991 1992 1993 1994 1995 1996 1997 1998
			bus = dev_tmp->subordinate->number;
			devfn = 0;
		} else {
			bus = dev_tmp->bus->number;
			devfn = dev_tmp->devfn;
		}
		spin_lock_irqsave(&device_domain_lock, flags);
		list_for_each_entry(info, &device_domain_list, global) {
1999 2000
			if (info->segment == segment &&
			    info->bus == bus && info->devfn == devfn) {
2001 2002 2003 2004 2005 2006 2007 2008 2009 2010 2011 2012
				found = info->domain;
				break;
			}
		}
		spin_unlock_irqrestore(&device_domain_lock, flags);
		/* pcie-pci bridge already has a domain, uses it */
		if (found) {
			domain = found;
			goto found_domain;
		}
	}

2013 2014 2015 2016
	domain = alloc_domain();
	if (!domain)
		goto error;

2017 2018 2019 2020 2021
	/* Allocate new domain for the device */
	drhd = dmar_find_matched_drhd_unit(pdev);
	if (!drhd) {
		printk(KERN_ERR "IOMMU: can't find DMAR for device %s\n",
			pci_name(pdev));
2022
		free_domain_mem(domain);
2023 2024 2025 2026
		return NULL;
	}
	iommu = drhd->iommu;

2027 2028
	ret = iommu_attach_domain(domain, iommu);
	if (ret) {
2029
		free_domain_mem(domain);
2030
		goto error;
2031
	}
2032 2033 2034 2035 2036 2037 2038 2039 2040 2041 2042 2043 2044

	if (domain_init(domain, gaw)) {
		domain_exit(domain);
		goto error;
	}

	/* register pcie-to-pci device */
	if (dev_tmp) {
		info = alloc_devinfo_mem();
		if (!info) {
			domain_exit(domain);
			goto error;
		}
2045
		info->segment = segment;
2046 2047 2048 2049 2050
		info->bus = bus;
		info->devfn = devfn;
		info->dev = NULL;
		info->domain = domain;
		/* This domain is shared by devices under p2p bridge */
W
Weidong Han 已提交
2051
		domain->flags |= DOMAIN_FLAG_P2P_MULTIPLE_DEVICES;
2052 2053 2054 2055 2056

		/* pcie-to-pci bridge already has a domain, uses it */
		found = NULL;
		spin_lock_irqsave(&device_domain_lock, flags);
		list_for_each_entry(tmp, &device_domain_list, global) {
2057 2058
			if (tmp->segment == segment &&
			    tmp->bus == bus && tmp->devfn == devfn) {
2059 2060 2061 2062 2063
				found = tmp->domain;
				break;
			}
		}
		if (found) {
2064
			spin_unlock_irqrestore(&device_domain_lock, flags);
2065 2066 2067 2068 2069 2070
			free_devinfo_mem(info);
			domain_exit(domain);
			domain = found;
		} else {
			list_add(&info->link, &domain->devices);
			list_add(&info->global, &device_domain_list);
2071
			spin_unlock_irqrestore(&device_domain_lock, flags);
2072 2073 2074 2075 2076 2077 2078
		}
	}

found_domain:
	info = alloc_devinfo_mem();
	if (!info)
		goto error;
2079
	info->segment = segment;
2080 2081 2082 2083 2084 2085 2086 2087 2088 2089 2090 2091 2092 2093 2094 2095 2096 2097
	info->bus = pdev->bus->number;
	info->devfn = pdev->devfn;
	info->dev = pdev;
	info->domain = domain;
	spin_lock_irqsave(&device_domain_lock, flags);
	/* somebody is fast */
	found = find_domain(pdev);
	if (found != NULL) {
		spin_unlock_irqrestore(&device_domain_lock, flags);
		if (found != domain) {
			domain_exit(domain);
			domain = found;
		}
		free_devinfo_mem(info);
		return domain;
	}
	list_add(&info->link, &domain->devices);
	list_add(&info->global, &device_domain_list);
2098
	pdev->dev.archdata.iommu = info;
2099 2100 2101 2102 2103 2104 2105
	spin_unlock_irqrestore(&device_domain_lock, flags);
	return domain;
error:
	/* recheck it here, maybe others set it */
	return find_domain(pdev);
}

2106
static int iommu_identity_mapping;
2107 2108 2109
#define IDENTMAP_ALL		1
#define IDENTMAP_GFX		2
#define IDENTMAP_AZALIA		4
2110

2111 2112 2113
static int iommu_domain_identity_map(struct dmar_domain *domain,
				     unsigned long long start,
				     unsigned long long end)
2114
{
2115 2116 2117 2118 2119
	unsigned long first_vpfn = start >> VTD_PAGE_SHIFT;
	unsigned long last_vpfn = end >> VTD_PAGE_SHIFT;

	if (!reserve_iova(&domain->iovad, dma_to_mm_pfn(first_vpfn),
			  dma_to_mm_pfn(last_vpfn))) {
2120
		printk(KERN_ERR "IOMMU: reserve iova failed\n");
2121
		return -ENOMEM;
2122 2123
	}

2124 2125
	pr_debug("Mapping reserved region %llx-%llx for domain %d\n",
		 start, end, domain->id);
2126 2127 2128 2129
	/*
	 * RMRR range might have overlap with physical memory range,
	 * clear it first
	 */
2130
	dma_pte_clear_range(domain, first_vpfn, last_vpfn);
2131

2132 2133
	return domain_pfn_mapping(domain, first_vpfn, first_vpfn,
				  last_vpfn - first_vpfn + 1,
2134
				  DMA_PTE_READ|DMA_PTE_WRITE);
2135 2136 2137 2138 2139 2140 2141 2142 2143
}

static int iommu_prepare_identity_map(struct pci_dev *pdev,
				      unsigned long long start,
				      unsigned long long end)
{
	struct dmar_domain *domain;
	int ret;

2144
	domain = get_domain_for_dev(pdev, DEFAULT_DOMAIN_ADDRESS_WIDTH);
2145 2146 2147
	if (!domain)
		return -ENOMEM;

2148 2149 2150 2151 2152 2153 2154 2155 2156 2157 2158 2159 2160
	/* For _hardware_ passthrough, don't bother. But for software
	   passthrough, we do it anyway -- it may indicate a memory
	   range which is reserved in E820, so which didn't get set
	   up to start with in si_domain */
	if (domain == si_domain && hw_pass_through) {
		printk("Ignoring identity map for HW passthrough device %s [0x%Lx - 0x%Lx]\n",
		       pci_name(pdev), start, end);
		return 0;
	}

	printk(KERN_INFO
	       "IOMMU: Setting identity map for device %s [0x%Lx - 0x%Lx]\n",
	       pci_name(pdev), start, end);
2161
	
2162 2163 2164 2165 2166 2167 2168 2169 2170 2171
	if (end < start) {
		WARN(1, "Your BIOS is broken; RMRR ends before it starts!\n"
			"BIOS vendor: %s; Ver: %s; Product Version: %s\n",
			dmi_get_system_info(DMI_BIOS_VENDOR),
			dmi_get_system_info(DMI_BIOS_VERSION),
		     dmi_get_system_info(DMI_PRODUCT_VERSION));
		ret = -EIO;
		goto error;
	}

2172 2173 2174 2175 2176 2177 2178 2179 2180 2181
	if (end >> agaw_to_width(domain->agaw)) {
		WARN(1, "Your BIOS is broken; RMRR exceeds permitted address width (%d bits)\n"
		     "BIOS vendor: %s; Ver: %s; Product Version: %s\n",
		     agaw_to_width(domain->agaw),
		     dmi_get_system_info(DMI_BIOS_VENDOR),
		     dmi_get_system_info(DMI_BIOS_VERSION),
		     dmi_get_system_info(DMI_PRODUCT_VERSION));
		ret = -EIO;
		goto error;
	}
2182

2183
	ret = iommu_domain_identity_map(domain, start, end);
2184 2185 2186 2187
	if (ret)
		goto error;

	/* context entry init */
F
Fenghua Yu 已提交
2188
	ret = domain_context_mapping(domain, pdev, CONTEXT_TT_MULTI_LEVEL);
2189 2190 2191 2192 2193 2194
	if (ret)
		goto error;

	return 0;

 error:
2195 2196 2197 2198 2199 2200 2201
	domain_exit(domain);
	return ret;
}

static inline int iommu_prepare_rmrr_dev(struct dmar_rmrr_unit *rmrr,
	struct pci_dev *pdev)
{
2202
	if (pdev->dev.archdata.iommu == DUMMY_DEVICE_DOMAIN_INFO)
2203 2204
		return 0;
	return iommu_prepare_identity_map(pdev, rmrr->base_address,
2205
		rmrr->end_address);
2206 2207
}

2208
#ifdef CONFIG_INTEL_IOMMU_FLOPPY_WA
2209 2210 2211 2212 2213 2214 2215 2216 2217
static inline void iommu_prepare_isa(void)
{
	struct pci_dev *pdev;
	int ret;

	pdev = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, NULL);
	if (!pdev)
		return;

2218
	printk(KERN_INFO "IOMMU: Prepare 0-16MiB unity mapping for LPC\n");
2219
	ret = iommu_prepare_identity_map(pdev, 0, 16*1024*1024 - 1);
2220 2221

	if (ret)
2222 2223
		printk(KERN_ERR "IOMMU: Failed to create 0-16MiB identity map; "
		       "floppy might not work\n");
2224 2225 2226 2227 2228 2229 2230

}
#else
static inline void iommu_prepare_isa(void)
{
	return;
}
2231
#endif /* !CONFIG_INTEL_IOMMU_FLPY_WA */
2232

2233
static int md_domain_init(struct dmar_domain *domain, int guest_width);
2234

2235
static int __init si_domain_init(int hw)
2236 2237 2238
{
	struct dmar_drhd_unit *drhd;
	struct intel_iommu *iommu;
2239
	int nid, ret = 0;
2240 2241 2242 2243 2244

	si_domain = alloc_domain();
	if (!si_domain)
		return -EFAULT;

2245
	pr_debug("Identity mapping domain is domain %d\n", si_domain->id);
2246 2247 2248 2249 2250 2251 2252 2253 2254 2255 2256 2257 2258 2259 2260 2261

	for_each_active_iommu(iommu, drhd) {
		ret = iommu_attach_domain(si_domain, iommu);
		if (ret) {
			domain_exit(si_domain);
			return -EFAULT;
		}
	}

	if (md_domain_init(si_domain, DEFAULT_DOMAIN_ADDRESS_WIDTH)) {
		domain_exit(si_domain);
		return -EFAULT;
	}

	si_domain->flags = DOMAIN_FLAG_STATIC_IDENTITY;

2262 2263 2264
	if (hw)
		return 0;

2265
	for_each_online_node(nid) {
2266 2267 2268 2269 2270 2271 2272 2273 2274
		unsigned long start_pfn, end_pfn;
		int i;

		for_each_mem_pfn_range(i, nid, &start_pfn, &end_pfn, NULL) {
			ret = iommu_domain_identity_map(si_domain,
					PFN_PHYS(start_pfn), PFN_PHYS(end_pfn));
			if (ret)
				return ret;
		}
2275 2276
	}

2277 2278 2279 2280 2281 2282 2283 2284 2285 2286 2287 2288
	return 0;
}

static void domain_remove_one_dev_info(struct dmar_domain *domain,
					  struct pci_dev *pdev);
static int identity_mapping(struct pci_dev *pdev)
{
	struct device_domain_info *info;

	if (likely(!iommu_identity_mapping))
		return 0;

2289 2290 2291
	info = pdev->dev.archdata.iommu;
	if (info && info != DUMMY_DEVICE_DOMAIN_INFO)
		return (info->domain == si_domain);
2292 2293 2294 2295 2296

	return 0;
}

static int domain_add_dev_info(struct dmar_domain *domain,
2297 2298
			       struct pci_dev *pdev,
			       int translation)
2299 2300 2301
{
	struct device_domain_info *info;
	unsigned long flags;
2302
	int ret;
2303 2304 2305 2306 2307 2308 2309 2310 2311 2312 2313 2314 2315 2316 2317 2318 2319

	info = alloc_devinfo_mem();
	if (!info)
		return -ENOMEM;

	info->segment = pci_domain_nr(pdev->bus);
	info->bus = pdev->bus->number;
	info->devfn = pdev->devfn;
	info->dev = pdev;
	info->domain = domain;

	spin_lock_irqsave(&device_domain_lock, flags);
	list_add(&info->link, &domain->devices);
	list_add(&info->global, &device_domain_list);
	pdev->dev.archdata.iommu = info;
	spin_unlock_irqrestore(&device_domain_lock, flags);

2320 2321 2322
	ret = domain_context_mapping(domain, pdev, translation);
	if (ret) {
		spin_lock_irqsave(&device_domain_lock, flags);
2323
		unlink_domain_info(info);
2324 2325 2326 2327 2328
		spin_unlock_irqrestore(&device_domain_lock, flags);
		free_devinfo_mem(info);
		return ret;
	}

2329 2330 2331
	return 0;
}

2332 2333 2334 2335 2336 2337 2338 2339 2340 2341 2342 2343 2344 2345 2346 2347 2348 2349
static bool device_has_rmrr(struct pci_dev *dev)
{
	struct dmar_rmrr_unit *rmrr;
	int i;

	for_each_rmrr_units(rmrr) {
		for (i = 0; i < rmrr->devices_cnt; i++) {
			/*
			 * Return TRUE if this RMRR contains the device that
			 * is passed in.
			 */
			if (rmrr->devices[i] == dev)
				return true;
		}
	}
	return false;
}

2350 2351
static int iommu_should_identity_map(struct pci_dev *pdev, int startup)
{
2352 2353 2354 2355 2356 2357 2358 2359 2360 2361 2362 2363 2364

	/*
	 * We want to prevent any device associated with an RMRR from
	 * getting placed into the SI Domain. This is done because
	 * problems exist when devices are moved in and out of domains
	 * and their respective RMRR info is lost. We exempt USB devices
	 * from this process due to their usage of RMRRs that are known
	 * to not be needed after BIOS hand-off to OS.
	 */
	if (device_has_rmrr(pdev) &&
	    (pdev->class >> 8) != PCI_CLASS_SERIAL_USB)
		return 0;

2365 2366 2367 2368 2369 2370 2371 2372
	if ((iommu_identity_mapping & IDENTMAP_AZALIA) && IS_AZALIA(pdev))
		return 1;

	if ((iommu_identity_mapping & IDENTMAP_GFX) && IS_GFX_DEVICE(pdev))
		return 1;

	if (!(iommu_identity_mapping & IDENTMAP_ALL))
		return 0;
2373

2374 2375 2376 2377 2378 2379 2380 2381 2382 2383 2384 2385 2386 2387 2388 2389 2390
	/*
	 * We want to start off with all devices in the 1:1 domain, and
	 * take them out later if we find they can't access all of memory.
	 *
	 * However, we can't do this for PCI devices behind bridges,
	 * because all PCI devices behind the same bridge will end up
	 * with the same source-id on their transactions.
	 *
	 * Practically speaking, we can't change things around for these
	 * devices at run-time, because we can't be sure there'll be no
	 * DMA transactions in flight for any of their siblings.
	 * 
	 * So PCI devices (unless they're on the root bus) as well as
	 * their parent PCI-PCI or PCIe-PCI bridges must be left _out_ of
	 * the 1:1 domain, just in _case_ one of their siblings turns out
	 * not to be able to map all of memory.
	 */
2391
	if (!pci_is_pcie(pdev)) {
2392 2393 2394 2395
		if (!pci_is_root_bus(pdev->bus))
			return 0;
		if (pdev->class >> 8 == PCI_CLASS_BRIDGE_PCI)
			return 0;
2396
	} else if (pci_pcie_type(pdev) == PCI_EXP_TYPE_PCI_BRIDGE)
2397 2398 2399 2400 2401 2402 2403
		return 0;

	/* 
	 * At boot time, we don't yet know if devices will be 64-bit capable.
	 * Assume that they will -- if they turn out not to be, then we can 
	 * take them out of the 1:1 domain later.
	 */
2404 2405 2406 2407 2408 2409 2410 2411 2412 2413 2414 2415 2416
	if (!startup) {
		/*
		 * If the device's dma_mask is less than the system's memory
		 * size then this is not a candidate for identity mapping.
		 */
		u64 dma_mask = pdev->dma_mask;

		if (pdev->dev.coherent_dma_mask &&
		    pdev->dev.coherent_dma_mask < dma_mask)
			dma_mask = pdev->dev.coherent_dma_mask;

		return dma_mask >= dma_get_required_mask(&pdev->dev);
	}
2417 2418 2419 2420

	return 1;
}

2421
static int __init iommu_prepare_static_identity_mapping(int hw)
2422 2423 2424 2425
{
	struct pci_dev *pdev = NULL;
	int ret;

2426
	ret = si_domain_init(hw);
2427 2428 2429 2430
	if (ret)
		return -EFAULT;

	for_each_pci_dev(pdev) {
2431
		if (iommu_should_identity_map(pdev, 1)) {
2432
			ret = domain_add_dev_info(si_domain, pdev,
2433 2434 2435 2436 2437 2438
					     hw ? CONTEXT_TT_PASS_THROUGH :
						  CONTEXT_TT_MULTI_LEVEL);
			if (ret) {
				/* device not associated with an iommu */
				if (ret == -ENODEV)
					continue;
2439
				return ret;
2440 2441 2442
			}
			pr_info("IOMMU: %s identity mapping for device %s\n",
				hw ? "hardware" : "software", pci_name(pdev));
2443
		}
2444 2445 2446 2447 2448
	}

	return 0;
}

2449
static int __init init_dmars(void)
2450 2451 2452 2453 2454
{
	struct dmar_drhd_unit *drhd;
	struct dmar_rmrr_unit *rmrr;
	struct pci_dev *pdev;
	struct intel_iommu *iommu;
2455
	int i, ret;
2456

2457 2458 2459 2460 2461 2462 2463
	/*
	 * for each drhd
	 *    allocate root
	 *    initialize and program root entry to not present
	 * endfor
	 */
	for_each_drhd_unit(drhd) {
M
mark gross 已提交
2464 2465 2466 2467 2468
		/*
		 * lock not needed as this is only incremented in the single
		 * threaded kernel __init code path all other access are read
		 * only
		 */
2469 2470 2471 2472 2473 2474
		if (g_num_of_iommus < IOMMU_UNITS_SUPPORTED) {
			g_num_of_iommus++;
			continue;
		}
		printk_once(KERN_ERR "intel-iommu: exceeded %d IOMMUs\n",
			  IOMMU_UNITS_SUPPORTED);
M
mark gross 已提交
2475 2476
	}

W
Weidong Han 已提交
2477 2478 2479 2480 2481 2482 2483 2484
	g_iommus = kcalloc(g_num_of_iommus, sizeof(struct intel_iommu *),
			GFP_KERNEL);
	if (!g_iommus) {
		printk(KERN_ERR "Allocating global iommu array failed\n");
		ret = -ENOMEM;
		goto error;
	}

2485 2486 2487
	deferred_flush = kzalloc(g_num_of_iommus *
		sizeof(struct deferred_flush_tables), GFP_KERNEL);
	if (!deferred_flush) {
M
mark gross 已提交
2488 2489 2490 2491 2492 2493 2494
		ret = -ENOMEM;
		goto error;
	}

	for_each_drhd_unit(drhd) {
		if (drhd->ignored)
			continue;
2495 2496

		iommu = drhd->iommu;
W
Weidong Han 已提交
2497
		g_iommus[iommu->seq_id] = iommu;
2498

2499 2500 2501 2502
		ret = iommu_init_domains(iommu);
		if (ret)
			goto error;

2503 2504 2505
		/*
		 * TBD:
		 * we could share the same root & context tables
L
Lucas De Marchi 已提交
2506
		 * among all IOMMU's. Need to Split it later.
2507 2508 2509 2510 2511 2512
		 */
		ret = iommu_alloc_root_entry(iommu);
		if (ret) {
			printk(KERN_ERR "IOMMU: allocate root entry failed\n");
			goto error;
		}
F
Fenghua Yu 已提交
2513
		if (!ecap_pass_through(iommu->ecap))
2514
			hw_pass_through = 0;
2515 2516
	}

2517 2518 2519
	/*
	 * Start from the sane iommu hardware state.
	 */
2520 2521 2522 2523 2524
	for_each_drhd_unit(drhd) {
		if (drhd->ignored)
			continue;

		iommu = drhd->iommu;
2525 2526 2527 2528 2529 2530 2531 2532 2533 2534 2535 2536 2537 2538 2539 2540 2541 2542 2543 2544 2545 2546 2547 2548 2549 2550

		/*
		 * If the queued invalidation is already initialized by us
		 * (for example, while enabling interrupt-remapping) then
		 * we got the things already rolling from a sane state.
		 */
		if (iommu->qi)
			continue;

		/*
		 * Clear any previous faults.
		 */
		dmar_fault(-1, iommu);
		/*
		 * Disable queued invalidation if supported and already enabled
		 * before OS handover.
		 */
		dmar_disable_qi(iommu);
	}

	for_each_drhd_unit(drhd) {
		if (drhd->ignored)
			continue;

		iommu = drhd->iommu;

2551 2552 2553 2554 2555 2556 2557
		if (dmar_enable_qi(iommu)) {
			/*
			 * Queued Invalidate not enabled, use Register Based
			 * Invalidate
			 */
			iommu->flush.flush_context = __iommu_flush_context;
			iommu->flush.flush_iotlb = __iommu_flush_iotlb;
Y
Yinghai Lu 已提交
2558
			printk(KERN_INFO "IOMMU %d 0x%Lx: using Register based "
2559
			       "invalidation\n",
Y
Yinghai Lu 已提交
2560
				iommu->seq_id,
2561
			       (unsigned long long)drhd->reg_base_addr);
2562 2563 2564
		} else {
			iommu->flush.flush_context = qi_flush_context;
			iommu->flush.flush_iotlb = qi_flush_iotlb;
Y
Yinghai Lu 已提交
2565
			printk(KERN_INFO "IOMMU %d 0x%Lx: using Queued "
2566
			       "invalidation\n",
Y
Yinghai Lu 已提交
2567
				iommu->seq_id,
2568
			       (unsigned long long)drhd->reg_base_addr);
2569 2570 2571
		}
	}

2572
	if (iommu_pass_through)
2573 2574
		iommu_identity_mapping |= IDENTMAP_ALL;

2575
#ifdef CONFIG_INTEL_IOMMU_BROKEN_GFX_WA
2576
	iommu_identity_mapping |= IDENTMAP_GFX;
2577
#endif
2578 2579 2580

	check_tylersburg_isoch();

2581
	/*
2582 2583 2584
	 * If pass through is not set or not enabled, setup context entries for
	 * identity mappings for rmrr, gfx, and isa and may fall back to static
	 * identity mapping if iommu_identity_mapping is set.
2585
	 */
2586 2587
	if (iommu_identity_mapping) {
		ret = iommu_prepare_static_identity_mapping(hw_pass_through);
F
Fenghua Yu 已提交
2588
		if (ret) {
2589 2590
			printk(KERN_CRIT "Failed to setup IOMMU pass-through\n");
			goto error;
2591 2592 2593
		}
	}
	/*
2594 2595 2596 2597 2598 2599 2600 2601 2602 2603 2604 2605
	 * For each rmrr
	 *   for each dev attached to rmrr
	 *   do
	 *     locate drhd for dev, alloc domain for dev
	 *     allocate free domain
	 *     allocate page table entries for rmrr
	 *     if context not allocated for bus
	 *           allocate and init context
	 *           set present in root table for this bus
	 *     init context with domain, translation etc
	 *    endfor
	 * endfor
2606
	 */
2607 2608 2609 2610 2611 2612 2613 2614 2615 2616 2617 2618 2619 2620
	printk(KERN_INFO "IOMMU: Setting RMRR:\n");
	for_each_rmrr_units(rmrr) {
		for (i = 0; i < rmrr->devices_cnt; i++) {
			pdev = rmrr->devices[i];
			/*
			 * some BIOS lists non-exist devices in DMAR
			 * table.
			 */
			if (!pdev)
				continue;
			ret = iommu_prepare_rmrr_dev(rmrr, pdev);
			if (ret)
				printk(KERN_ERR
				       "IOMMU: mapping reserved region failed\n");
2621
		}
F
Fenghua Yu 已提交
2622
	}
2623

2624 2625
	iommu_prepare_isa();

2626 2627 2628 2629 2630 2631 2632 2633
	/*
	 * for each drhd
	 *   enable fault log
	 *   global invalidate context cache
	 *   global invalidate iotlb
	 *   enable translation
	 */
	for_each_drhd_unit(drhd) {
2634 2635 2636 2637 2638 2639 2640
		if (drhd->ignored) {
			/*
			 * we always have to disable PMRs or DMA may fail on
			 * this device
			 */
			if (force_on)
				iommu_disable_protect_mem_regions(drhd->iommu);
2641
			continue;
2642
		}
2643 2644 2645 2646
		iommu = drhd->iommu;

		iommu_flush_write_buffer(iommu);

2647 2648 2649 2650
		ret = dmar_set_interrupt(iommu);
		if (ret)
			goto error;

2651 2652
		iommu_set_root_entry(iommu);

2653
		iommu->flush.flush_context(iommu, 0, 0, 0, DMA_CCMD_GLOBAL_INVL);
2654
		iommu->flush.flush_iotlb(iommu, 0, 0, 0, DMA_TLB_GLOBAL_FLUSH);
M
mark gross 已提交
2655

2656 2657 2658
		ret = iommu_enable_translation(iommu);
		if (ret)
			goto error;
2659 2660

		iommu_disable_protect_mem_regions(iommu);
2661 2662 2663 2664 2665 2666 2667 2668 2669 2670
	}

	return 0;
error:
	for_each_drhd_unit(drhd) {
		if (drhd->ignored)
			continue;
		iommu = drhd->iommu;
		free_iommu(iommu);
	}
W
Weidong Han 已提交
2671
	kfree(g_iommus);
2672 2673 2674
	return ret;
}

2675
/* This takes a number of _MM_ pages, not VTD pages */
2676 2677 2678
static struct iova *intel_alloc_iova(struct device *dev,
				     struct dmar_domain *domain,
				     unsigned long nrpages, uint64_t dma_mask)
2679 2680 2681 2682
{
	struct pci_dev *pdev = to_pci_dev(dev);
	struct iova *iova = NULL;

2683 2684 2685 2686
	/* Restrict dma_mask to the width that the iommu can handle */
	dma_mask = min_t(uint64_t, DOMAIN_MAX_ADDR(domain->gaw), dma_mask);

	if (!dmar_forcedac && dma_mask > DMA_BIT_MASK(32)) {
2687 2688
		/*
		 * First try to allocate an io virtual address in
2689
		 * DMA_BIT_MASK(32) and if that fails then try allocating
J
Joe Perches 已提交
2690
		 * from higher range
2691
		 */
2692 2693 2694 2695 2696 2697 2698 2699 2700
		iova = alloc_iova(&domain->iovad, nrpages,
				  IOVA_PFN(DMA_BIT_MASK(32)), 1);
		if (iova)
			return iova;
	}
	iova = alloc_iova(&domain->iovad, nrpages, IOVA_PFN(dma_mask), 1);
	if (unlikely(!iova)) {
		printk(KERN_ERR "Allocating %ld-page iova for %s failed",
		       nrpages, pci_name(pdev));
2701 2702 2703 2704 2705 2706
		return NULL;
	}

	return iova;
}

2707
static struct dmar_domain *__get_valid_domain_for_dev(struct pci_dev *pdev)
2708 2709 2710 2711 2712 2713 2714 2715 2716
{
	struct dmar_domain *domain;
	int ret;

	domain = get_domain_for_dev(pdev,
			DEFAULT_DOMAIN_ADDRESS_WIDTH);
	if (!domain) {
		printk(KERN_ERR
			"Allocating domain for %s failed", pci_name(pdev));
A
Al Viro 已提交
2717
		return NULL;
2718 2719 2720
	}

	/* make sure context mapping is ok */
W
Weidong Han 已提交
2721
	if (unlikely(!domain_context_mapped(pdev))) {
F
Fenghua Yu 已提交
2722 2723
		ret = domain_context_mapping(domain, pdev,
					     CONTEXT_TT_MULTI_LEVEL);
2724 2725 2726 2727
		if (ret) {
			printk(KERN_ERR
				"Domain context map for %s failed",
				pci_name(pdev));
A
Al Viro 已提交
2728
			return NULL;
2729
		}
2730 2731
	}

2732 2733 2734
	return domain;
}

2735 2736 2737 2738 2739 2740 2741 2742 2743 2744 2745 2746
static inline struct dmar_domain *get_valid_domain_for_dev(struct pci_dev *dev)
{
	struct device_domain_info *info;

	/* No lock here, assumes no domain exit in normal case */
	info = dev->dev.archdata.iommu;
	if (likely(info))
		return info->domain;

	return __get_valid_domain_for_dev(dev);
}

2747 2748 2749 2750 2751 2752
static int iommu_dummy(struct pci_dev *pdev)
{
	return pdev->dev.archdata.iommu == DUMMY_DEVICE_DOMAIN_INFO;
}

/* Check if the pdev needs to go through non-identity map and unmap process.*/
2753
static int iommu_no_mapping(struct device *dev)
2754
{
2755
	struct pci_dev *pdev;
2756 2757
	int found;

2758 2759 2760 2761
	if (unlikely(dev->bus != &pci_bus_type))
		return 1;

	pdev = to_pci_dev(dev);
2762 2763 2764
	if (iommu_dummy(pdev))
		return 1;

2765
	if (!iommu_identity_mapping)
2766
		return 0;
2767 2768 2769

	found = identity_mapping(pdev);
	if (found) {
2770
		if (iommu_should_identity_map(pdev, 0))
2771 2772 2773 2774 2775 2776 2777 2778 2779 2780 2781 2782 2783 2784 2785 2786
			return 1;
		else {
			/*
			 * 32 bit DMA is removed from si_domain and fall back
			 * to non-identity mapping.
			 */
			domain_remove_one_dev_info(si_domain, pdev);
			printk(KERN_INFO "32bit %s uses non-identity mapping\n",
			       pci_name(pdev));
			return 0;
		}
	} else {
		/*
		 * In case of a detached 64 bit DMA device from vm, the device
		 * is put into si_domain for identity mapping.
		 */
2787
		if (iommu_should_identity_map(pdev, 0)) {
2788
			int ret;
2789 2790 2791 2792
			ret = domain_add_dev_info(si_domain, pdev,
						  hw_pass_through ?
						  CONTEXT_TT_PASS_THROUGH :
						  CONTEXT_TT_MULTI_LEVEL);
2793 2794 2795 2796 2797 2798 2799 2800
			if (!ret) {
				printk(KERN_INFO "64bit %s uses identity mapping\n",
				       pci_name(pdev));
				return 1;
			}
		}
	}

2801
	return 0;
2802 2803
}

2804 2805
static dma_addr_t __intel_map_single(struct device *hwdev, phys_addr_t paddr,
				     size_t size, int dir, u64 dma_mask)
2806 2807 2808
{
	struct pci_dev *pdev = to_pci_dev(hwdev);
	struct dmar_domain *domain;
F
Fenghua Yu 已提交
2809
	phys_addr_t start_paddr;
2810 2811
	struct iova *iova;
	int prot = 0;
I
Ingo Molnar 已提交
2812
	int ret;
2813
	struct intel_iommu *iommu;
2814
	unsigned long paddr_pfn = paddr >> PAGE_SHIFT;
2815 2816

	BUG_ON(dir == DMA_NONE);
2817

2818
	if (iommu_no_mapping(hwdev))
I
Ingo Molnar 已提交
2819
		return paddr;
2820 2821 2822 2823 2824

	domain = get_valid_domain_for_dev(pdev);
	if (!domain)
		return 0;

2825
	iommu = domain_get_iommu(domain);
2826
	size = aligned_nrpages(paddr, size);
2827

2828
	iova = intel_alloc_iova(hwdev, domain, dma_to_mm_pfn(size), dma_mask);
2829 2830 2831
	if (!iova)
		goto error;

2832 2833 2834 2835 2836
	/*
	 * Check if DMAR supports zero-length reads on write only
	 * mappings..
	 */
	if (dir == DMA_TO_DEVICE || dir == DMA_BIDIRECTIONAL || \
2837
			!cap_zlr(iommu->cap))
2838 2839 2840 2841
		prot |= DMA_PTE_READ;
	if (dir == DMA_FROM_DEVICE || dir == DMA_BIDIRECTIONAL)
		prot |= DMA_PTE_WRITE;
	/*
I
Ingo Molnar 已提交
2842
	 * paddr - (paddr + size) might be partial page, we should map the whole
2843
	 * page.  Note: if two part of one page are separately mapped, we
I
Ingo Molnar 已提交
2844
	 * might have two guest_addr mapping to the same host paddr, but this
2845 2846
	 * is not a big problem
	 */
2847
	ret = domain_pfn_mapping(domain, mm_to_dma_pfn(iova->pfn_lo),
2848
				 mm_to_dma_pfn(paddr_pfn), size, prot);
2849 2850 2851
	if (ret)
		goto error;

2852 2853
	/* it's a non-present to present mapping. Only flush if caching mode */
	if (cap_caching_mode(iommu->cap))
2854
		iommu_flush_iotlb_psi(iommu, domain->id, mm_to_dma_pfn(iova->pfn_lo), size, 1);
2855
	else
2856
		iommu_flush_write_buffer(iommu);
2857

2858 2859 2860
	start_paddr = (phys_addr_t)iova->pfn_lo << PAGE_SHIFT;
	start_paddr += paddr & ~PAGE_MASK;
	return start_paddr;
2861 2862

error:
2863 2864
	if (iova)
		__free_iova(&domain->iovad, iova);
2865
	printk(KERN_ERR"Device %s request: %zx@%llx dir %d --- failed\n",
F
Fenghua Yu 已提交
2866
		pci_name(pdev), size, (unsigned long long)paddr, dir);
2867 2868 2869
	return 0;
}

2870 2871 2872 2873
static dma_addr_t intel_map_page(struct device *dev, struct page *page,
				 unsigned long offset, size_t size,
				 enum dma_data_direction dir,
				 struct dma_attrs *attrs)
2874
{
2875 2876
	return __intel_map_single(dev, page_to_phys(page) + offset, size,
				  dir, to_pci_dev(dev)->dma_mask);
2877 2878
}

M
mark gross 已提交
2879 2880
static void flush_unmaps(void)
{
2881
	int i, j;
M
mark gross 已提交
2882 2883 2884 2885 2886

	timer_on = 0;

	/* just flush them all */
	for (i = 0; i < g_num_of_iommus; i++) {
2887 2888 2889
		struct intel_iommu *iommu = g_iommus[i];
		if (!iommu)
			continue;
2890

2891 2892 2893
		if (!deferred_flush[i].next)
			continue;

2894 2895 2896
		/* In caching mode, global flushes turn emulation expensive */
		if (!cap_caching_mode(iommu->cap))
			iommu->flush.flush_iotlb(iommu, 0, 0, 0,
Y
Yu Zhao 已提交
2897
					 DMA_TLB_GLOBAL_FLUSH);
2898
		for (j = 0; j < deferred_flush[i].next; j++) {
Y
Yu Zhao 已提交
2899 2900
			unsigned long mask;
			struct iova *iova = deferred_flush[i].iova[j];
2901 2902 2903 2904 2905 2906 2907 2908 2909 2910 2911
			struct dmar_domain *domain = deferred_flush[i].domain[j];

			/* On real hardware multiple invalidations are expensive */
			if (cap_caching_mode(iommu->cap))
				iommu_flush_iotlb_psi(iommu, domain->id,
				iova->pfn_lo, iova->pfn_hi - iova->pfn_lo + 1, 0);
			else {
				mask = ilog2(mm_to_dma_pfn(iova->pfn_hi - iova->pfn_lo + 1));
				iommu_flush_dev_iotlb(deferred_flush[i].domain[j],
						(uint64_t)iova->pfn_lo << PAGE_SHIFT, mask);
			}
Y
Yu Zhao 已提交
2912
			__free_iova(&deferred_flush[i].domain[j]->iovad, iova);
2913
		}
2914
		deferred_flush[i].next = 0;
M
mark gross 已提交
2915 2916 2917 2918 2919 2920 2921
	}

	list_size = 0;
}

static void flush_unmaps_timeout(unsigned long data)
{
2922 2923 2924
	unsigned long flags;

	spin_lock_irqsave(&async_umap_flush_lock, flags);
M
mark gross 已提交
2925
	flush_unmaps();
2926
	spin_unlock_irqrestore(&async_umap_flush_lock, flags);
M
mark gross 已提交
2927 2928 2929 2930 2931
}

static void add_unmap(struct dmar_domain *dom, struct iova *iova)
{
	unsigned long flags;
2932
	int next, iommu_id;
2933
	struct intel_iommu *iommu;
M
mark gross 已提交
2934 2935

	spin_lock_irqsave(&async_umap_flush_lock, flags);
2936 2937 2938
	if (list_size == HIGH_WATER_MARK)
		flush_unmaps();

2939 2940
	iommu = domain_get_iommu(dom);
	iommu_id = iommu->seq_id;
2941

2942 2943 2944 2945
	next = deferred_flush[iommu_id].next;
	deferred_flush[iommu_id].domain[next] = dom;
	deferred_flush[iommu_id].iova[next] = iova;
	deferred_flush[iommu_id].next++;
M
mark gross 已提交
2946 2947 2948 2949 2950 2951 2952 2953 2954

	if (!timer_on) {
		mod_timer(&unmap_timer, jiffies + msecs_to_jiffies(10));
		timer_on = 1;
	}
	list_size++;
	spin_unlock_irqrestore(&async_umap_flush_lock, flags);
}

2955 2956 2957
static void intel_unmap_page(struct device *dev, dma_addr_t dev_addr,
			     size_t size, enum dma_data_direction dir,
			     struct dma_attrs *attrs)
2958 2959
{
	struct pci_dev *pdev = to_pci_dev(dev);
2960
	struct dmar_domain *domain;
2961
	unsigned long start_pfn, last_pfn;
2962
	struct iova *iova;
2963
	struct intel_iommu *iommu;
2964

2965
	if (iommu_no_mapping(dev))
2966
		return;
2967

2968 2969 2970
	domain = find_domain(pdev);
	BUG_ON(!domain);

2971 2972
	iommu = domain_get_iommu(domain);

2973
	iova = find_iova(&domain->iovad, IOVA_PFN(dev_addr));
2974 2975
	if (WARN_ONCE(!iova, "Driver unmaps unmatched page at PFN %llx\n",
		      (unsigned long long)dev_addr))
2976 2977
		return;

2978 2979
	start_pfn = mm_to_dma_pfn(iova->pfn_lo);
	last_pfn = mm_to_dma_pfn(iova->pfn_hi + 1) - 1;
2980

2981 2982
	pr_debug("Device %s unmapping: pfn %lx-%lx\n",
		 pci_name(pdev), start_pfn, last_pfn);
2983

2984
	/*  clear the whole page */
2985 2986
	dma_pte_clear_range(domain, start_pfn, last_pfn);

2987
	/* free page tables */
2988 2989
	dma_pte_free_pagetable(domain, start_pfn, last_pfn);

M
mark gross 已提交
2990
	if (intel_iommu_strict) {
2991
		iommu_flush_iotlb_psi(iommu, domain->id, start_pfn,
2992
				      last_pfn - start_pfn + 1, 0);
M
mark gross 已提交
2993 2994 2995 2996 2997 2998 2999 3000 3001
		/* free iova */
		__free_iova(&domain->iovad, iova);
	} else {
		add_unmap(domain, iova);
		/*
		 * queue up the release of the unmap to save the 1/6th of the
		 * cpu used up by the iotlb flush operation...
		 */
	}
3002 3003
}

3004
static void *intel_alloc_coherent(struct device *hwdev, size_t size,
3005 3006
				  dma_addr_t *dma_handle, gfp_t flags,
				  struct dma_attrs *attrs)
3007 3008 3009 3010
{
	void *vaddr;
	int order;

F
Fenghua Yu 已提交
3011
	size = PAGE_ALIGN(size);
3012
	order = get_order(size);
3013 3014 3015 3016 3017 3018 3019 3020 3021

	if (!iommu_no_mapping(hwdev))
		flags &= ~(GFP_DMA | GFP_DMA32);
	else if (hwdev->coherent_dma_mask < dma_get_required_mask(hwdev)) {
		if (hwdev->coherent_dma_mask < DMA_BIT_MASK(32))
			flags |= GFP_DMA;
		else
			flags |= GFP_DMA32;
	}
3022 3023 3024 3025 3026 3027

	vaddr = (void *)__get_free_pages(flags, order);
	if (!vaddr)
		return NULL;
	memset(vaddr, 0, size);

3028 3029 3030
	*dma_handle = __intel_map_single(hwdev, virt_to_bus(vaddr), size,
					 DMA_BIDIRECTIONAL,
					 hwdev->coherent_dma_mask);
3031 3032 3033 3034 3035 3036
	if (*dma_handle)
		return vaddr;
	free_pages((unsigned long)vaddr, order);
	return NULL;
}

3037
static void intel_free_coherent(struct device *hwdev, size_t size, void *vaddr,
3038
				dma_addr_t dma_handle, struct dma_attrs *attrs)
3039 3040 3041
{
	int order;

F
Fenghua Yu 已提交
3042
	size = PAGE_ALIGN(size);
3043 3044
	order = get_order(size);

3045
	intel_unmap_page(hwdev, dma_handle, size, DMA_BIDIRECTIONAL, NULL);
3046 3047 3048
	free_pages((unsigned long)vaddr, order);
}

3049 3050 3051
static void intel_unmap_sg(struct device *hwdev, struct scatterlist *sglist,
			   int nelems, enum dma_data_direction dir,
			   struct dma_attrs *attrs)
3052 3053 3054
{
	struct pci_dev *pdev = to_pci_dev(hwdev);
	struct dmar_domain *domain;
3055
	unsigned long start_pfn, last_pfn;
3056
	struct iova *iova;
3057
	struct intel_iommu *iommu;
3058

3059
	if (iommu_no_mapping(hwdev))
3060 3061 3062
		return;

	domain = find_domain(pdev);
3063 3064 3065
	BUG_ON(!domain);

	iommu = domain_get_iommu(domain);
3066

F
FUJITA Tomonori 已提交
3067
	iova = find_iova(&domain->iovad, IOVA_PFN(sglist[0].dma_address));
3068 3069
	if (WARN_ONCE(!iova, "Driver unmaps unmatched sglist at PFN %llx\n",
		      (unsigned long long)sglist[0].dma_address))
3070 3071
		return;

3072 3073
	start_pfn = mm_to_dma_pfn(iova->pfn_lo);
	last_pfn = mm_to_dma_pfn(iova->pfn_hi + 1) - 1;
3074 3075

	/*  clear the whole page */
3076 3077
	dma_pte_clear_range(domain, start_pfn, last_pfn);

3078
	/* free page tables */
3079
	dma_pte_free_pagetable(domain, start_pfn, last_pfn);
3080

3081 3082
	if (intel_iommu_strict) {
		iommu_flush_iotlb_psi(iommu, domain->id, start_pfn,
3083
				      last_pfn - start_pfn + 1, 0);
3084 3085 3086 3087 3088 3089 3090 3091 3092
		/* free iova */
		__free_iova(&domain->iovad, iova);
	} else {
		add_unmap(domain, iova);
		/*
		 * queue up the release of the unmap to save the 1/6th of the
		 * cpu used up by the iotlb flush operation...
		 */
	}
3093 3094 3095
}

static int intel_nontranslate_map_sg(struct device *hddev,
F
FUJITA Tomonori 已提交
3096
	struct scatterlist *sglist, int nelems, int dir)
3097 3098
{
	int i;
F
FUJITA Tomonori 已提交
3099
	struct scatterlist *sg;
3100

F
FUJITA Tomonori 已提交
3101
	for_each_sg(sglist, sg, nelems, i) {
F
FUJITA Tomonori 已提交
3102
		BUG_ON(!sg_page(sg));
3103
		sg->dma_address = page_to_phys(sg_page(sg)) + sg->offset;
F
FUJITA Tomonori 已提交
3104
		sg->dma_length = sg->length;
3105 3106 3107 3108
	}
	return nelems;
}

3109 3110
static int intel_map_sg(struct device *hwdev, struct scatterlist *sglist, int nelems,
			enum dma_data_direction dir, struct dma_attrs *attrs)
3111 3112 3113 3114
{
	int i;
	struct pci_dev *pdev = to_pci_dev(hwdev);
	struct dmar_domain *domain;
3115 3116 3117 3118
	size_t size = 0;
	int prot = 0;
	struct iova *iova = NULL;
	int ret;
F
FUJITA Tomonori 已提交
3119
	struct scatterlist *sg;
3120
	unsigned long start_vpfn;
3121
	struct intel_iommu *iommu;
3122 3123

	BUG_ON(dir == DMA_NONE);
3124
	if (iommu_no_mapping(hwdev))
F
FUJITA Tomonori 已提交
3125
		return intel_nontranslate_map_sg(hwdev, sglist, nelems, dir);
3126

3127 3128 3129 3130
	domain = get_valid_domain_for_dev(pdev);
	if (!domain)
		return 0;

3131 3132
	iommu = domain_get_iommu(domain);

3133
	for_each_sg(sglist, sg, nelems, i)
3134
		size += aligned_nrpages(sg->offset, sg->length);
3135

3136 3137
	iova = intel_alloc_iova(hwdev, domain, dma_to_mm_pfn(size),
				pdev->dma_mask);
3138
	if (!iova) {
F
FUJITA Tomonori 已提交
3139
		sglist->dma_length = 0;
3140 3141 3142 3143 3144 3145 3146 3147
		return 0;
	}

	/*
	 * Check if DMAR supports zero-length reads on write only
	 * mappings..
	 */
	if (dir == DMA_TO_DEVICE || dir == DMA_BIDIRECTIONAL || \
3148
			!cap_zlr(iommu->cap))
3149 3150 3151 3152
		prot |= DMA_PTE_READ;
	if (dir == DMA_FROM_DEVICE || dir == DMA_BIDIRECTIONAL)
		prot |= DMA_PTE_WRITE;

3153
	start_vpfn = mm_to_dma_pfn(iova->pfn_lo);
3154

3155
	ret = domain_sg_mapping(domain, start_vpfn, sglist, size, prot);
3156 3157 3158 3159 3160 3161 3162 3163 3164 3165
	if (unlikely(ret)) {
		/*  clear the page */
		dma_pte_clear_range(domain, start_vpfn,
				    start_vpfn + size - 1);
		/* free page tables */
		dma_pte_free_pagetable(domain, start_vpfn,
				       start_vpfn + size - 1);
		/* free iova */
		__free_iova(&domain->iovad, iova);
		return 0;
3166 3167
	}

3168 3169
	/* it's a non-present to present mapping. Only flush if caching mode */
	if (cap_caching_mode(iommu->cap))
3170
		iommu_flush_iotlb_psi(iommu, domain->id, start_vpfn, size, 1);
3171
	else
3172
		iommu_flush_write_buffer(iommu);
3173

3174 3175 3176
	return nelems;
}

3177 3178 3179 3180 3181
static int intel_mapping_error(struct device *dev, dma_addr_t dma_addr)
{
	return !dma_addr;
}

3182
struct dma_map_ops intel_dma_ops = {
3183 3184
	.alloc = intel_alloc_coherent,
	.free = intel_free_coherent,
3185 3186
	.map_sg = intel_map_sg,
	.unmap_sg = intel_unmap_sg,
3187 3188
	.map_page = intel_map_page,
	.unmap_page = intel_unmap_page,
3189
	.mapping_error = intel_mapping_error,
3190 3191 3192 3193 3194 3195 3196 3197 3198 3199 3200 3201 3202 3203 3204 3205 3206 3207 3208 3209 3210 3211 3212 3213 3214 3215 3216 3217 3218 3219 3220 3221 3222 3223 3224 3225 3226 3227 3228 3229 3230 3231 3232 3233 3234 3235 3236 3237 3238 3239 3240 3241 3242 3243 3244 3245 3246 3247 3248 3249 3250 3251 3252 3253 3254 3255 3256 3257 3258 3259 3260 3261 3262 3263 3264 3265 3266 3267 3268 3269 3270 3271 3272 3273
};

static inline int iommu_domain_cache_init(void)
{
	int ret = 0;

	iommu_domain_cache = kmem_cache_create("iommu_domain",
					 sizeof(struct dmar_domain),
					 0,
					 SLAB_HWCACHE_ALIGN,

					 NULL);
	if (!iommu_domain_cache) {
		printk(KERN_ERR "Couldn't create iommu_domain cache\n");
		ret = -ENOMEM;
	}

	return ret;
}

static inline int iommu_devinfo_cache_init(void)
{
	int ret = 0;

	iommu_devinfo_cache = kmem_cache_create("iommu_devinfo",
					 sizeof(struct device_domain_info),
					 0,
					 SLAB_HWCACHE_ALIGN,
					 NULL);
	if (!iommu_devinfo_cache) {
		printk(KERN_ERR "Couldn't create devinfo cache\n");
		ret = -ENOMEM;
	}

	return ret;
}

static inline int iommu_iova_cache_init(void)
{
	int ret = 0;

	iommu_iova_cache = kmem_cache_create("iommu_iova",
					 sizeof(struct iova),
					 0,
					 SLAB_HWCACHE_ALIGN,
					 NULL);
	if (!iommu_iova_cache) {
		printk(KERN_ERR "Couldn't create iova cache\n");
		ret = -ENOMEM;
	}

	return ret;
}

static int __init iommu_init_mempool(void)
{
	int ret;
	ret = iommu_iova_cache_init();
	if (ret)
		return ret;

	ret = iommu_domain_cache_init();
	if (ret)
		goto domain_error;

	ret = iommu_devinfo_cache_init();
	if (!ret)
		return ret;

	kmem_cache_destroy(iommu_domain_cache);
domain_error:
	kmem_cache_destroy(iommu_iova_cache);

	return -ENOMEM;
}

static void __init iommu_exit_mempool(void)
{
	kmem_cache_destroy(iommu_devinfo_cache);
	kmem_cache_destroy(iommu_domain_cache);
	kmem_cache_destroy(iommu_iova_cache);

}

3274 3275 3276 3277 3278 3279 3280 3281 3282 3283 3284 3285 3286 3287 3288 3289 3290 3291 3292 3293 3294 3295 3296 3297 3298 3299 3300 3301
static void quirk_ioat_snb_local_iommu(struct pci_dev *pdev)
{
	struct dmar_drhd_unit *drhd;
	u32 vtbar;
	int rc;

	/* We know that this device on this chipset has its own IOMMU.
	 * If we find it under a different IOMMU, then the BIOS is lying
	 * to us. Hope that the IOMMU for this device is actually
	 * disabled, and it needs no translation...
	 */
	rc = pci_bus_read_config_dword(pdev->bus, PCI_DEVFN(0, 0), 0xb0, &vtbar);
	if (rc) {
		/* "can't" happen */
		dev_info(&pdev->dev, "failed to run vt-d quirk\n");
		return;
	}
	vtbar &= 0xffff0000;

	/* we know that the this iommu should be at offset 0xa000 from vtbar */
	drhd = dmar_find_matched_drhd_unit(pdev);
	if (WARN_TAINT_ONCE(!drhd || drhd->reg_base_addr - vtbar != 0xa000,
			    TAINT_FIRMWARE_WORKAROUND,
			    "BIOS assigned incorrect VT-d unit for Intel(R) QuickData Technology device\n"))
		pdev->dev.archdata.iommu = DUMMY_DEVICE_DOMAIN_INFO;
}
DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IOAT_SNB, quirk_ioat_snb_local_iommu);

3302 3303 3304 3305 3306 3307 3308 3309 3310 3311 3312 3313 3314 3315 3316 3317 3318 3319 3320 3321 3322 3323 3324
static void __init init_no_remapping_devices(void)
{
	struct dmar_drhd_unit *drhd;

	for_each_drhd_unit(drhd) {
		if (!drhd->include_all) {
			int i;
			for (i = 0; i < drhd->devices_cnt; i++)
				if (drhd->devices[i] != NULL)
					break;
			/* ignore DMAR unit if no pci devices exist */
			if (i == drhd->devices_cnt)
				drhd->ignored = 1;
		}
	}

	for_each_drhd_unit(drhd) {
		int i;
		if (drhd->ignored || drhd->include_all)
			continue;

		for (i = 0; i < drhd->devices_cnt; i++)
			if (drhd->devices[i] &&
3325
			    !IS_GFX_DEVICE(drhd->devices[i]))
3326 3327 3328 3329 3330
				break;

		if (i < drhd->devices_cnt)
			continue;

3331 3332 3333 3334 3335 3336 3337 3338 3339 3340 3341
		/* This IOMMU has *only* gfx devices. Either bypass it or
		   set the gfx_mapped flag, as appropriate */
		if (dmar_map_gfx) {
			intel_iommu_gfx_mapped = 1;
		} else {
			drhd->ignored = 1;
			for (i = 0; i < drhd->devices_cnt; i++) {
				if (!drhd->devices[i])
					continue;
				drhd->devices[i]->dev.archdata.iommu = DUMMY_DEVICE_DOMAIN_INFO;
			}
3342 3343 3344 3345
		}
	}
}

3346 3347 3348 3349 3350 3351 3352 3353 3354 3355
#ifdef CONFIG_SUSPEND
static int init_iommu_hw(void)
{
	struct dmar_drhd_unit *drhd;
	struct intel_iommu *iommu = NULL;

	for_each_active_iommu(iommu, drhd)
		if (iommu->qi)
			dmar_reenable_qi(iommu);

3356 3357 3358 3359 3360 3361 3362 3363 3364 3365 3366
	for_each_iommu(iommu, drhd) {
		if (drhd->ignored) {
			/*
			 * we always have to disable PMRs or DMA may fail on
			 * this device
			 */
			if (force_on)
				iommu_disable_protect_mem_regions(iommu);
			continue;
		}
	
3367 3368 3369 3370 3371
		iommu_flush_write_buffer(iommu);

		iommu_set_root_entry(iommu);

		iommu->flush.flush_context(iommu, 0, 0, 0,
3372
					   DMA_CCMD_GLOBAL_INVL);
3373
		iommu->flush.flush_iotlb(iommu, 0, 0, 0,
3374
					 DMA_TLB_GLOBAL_FLUSH);
3375 3376
		if (iommu_enable_translation(iommu))
			return 1;
3377
		iommu_disable_protect_mem_regions(iommu);
3378 3379 3380 3381 3382 3383 3384 3385 3386 3387 3388 3389
	}

	return 0;
}

static void iommu_flush_all(void)
{
	struct dmar_drhd_unit *drhd;
	struct intel_iommu *iommu;

	for_each_active_iommu(iommu, drhd) {
		iommu->flush.flush_context(iommu, 0, 0, 0,
3390
					   DMA_CCMD_GLOBAL_INVL);
3391
		iommu->flush.flush_iotlb(iommu, 0, 0, 0,
3392
					 DMA_TLB_GLOBAL_FLUSH);
3393 3394 3395
	}
}

3396
static int iommu_suspend(void)
3397 3398 3399 3400 3401 3402 3403 3404 3405 3406 3407 3408 3409 3410 3411 3412 3413
{
	struct dmar_drhd_unit *drhd;
	struct intel_iommu *iommu = NULL;
	unsigned long flag;

	for_each_active_iommu(iommu, drhd) {
		iommu->iommu_state = kzalloc(sizeof(u32) * MAX_SR_DMAR_REGS,
						 GFP_ATOMIC);
		if (!iommu->iommu_state)
			goto nomem;
	}

	iommu_flush_all();

	for_each_active_iommu(iommu, drhd) {
		iommu_disable_translation(iommu);

3414
		raw_spin_lock_irqsave(&iommu->register_lock, flag);
3415 3416 3417 3418 3419 3420 3421 3422 3423 3424

		iommu->iommu_state[SR_DMAR_FECTL_REG] =
			readl(iommu->reg + DMAR_FECTL_REG);
		iommu->iommu_state[SR_DMAR_FEDATA_REG] =
			readl(iommu->reg + DMAR_FEDATA_REG);
		iommu->iommu_state[SR_DMAR_FEADDR_REG] =
			readl(iommu->reg + DMAR_FEADDR_REG);
		iommu->iommu_state[SR_DMAR_FEUADDR_REG] =
			readl(iommu->reg + DMAR_FEUADDR_REG);

3425
		raw_spin_unlock_irqrestore(&iommu->register_lock, flag);
3426 3427 3428 3429 3430 3431 3432 3433 3434 3435
	}
	return 0;

nomem:
	for_each_active_iommu(iommu, drhd)
		kfree(iommu->iommu_state);

	return -ENOMEM;
}

3436
static void iommu_resume(void)
3437 3438 3439 3440 3441 3442
{
	struct dmar_drhd_unit *drhd;
	struct intel_iommu *iommu = NULL;
	unsigned long flag;

	if (init_iommu_hw()) {
3443 3444 3445 3446
		if (force_on)
			panic("tboot: IOMMU setup failed, DMAR can not resume!\n");
		else
			WARN(1, "IOMMU setup failed, DMAR can not resume!\n");
3447
		return;
3448 3449 3450 3451
	}

	for_each_active_iommu(iommu, drhd) {

3452
		raw_spin_lock_irqsave(&iommu->register_lock, flag);
3453 3454 3455 3456 3457 3458 3459 3460 3461 3462

		writel(iommu->iommu_state[SR_DMAR_FECTL_REG],
			iommu->reg + DMAR_FECTL_REG);
		writel(iommu->iommu_state[SR_DMAR_FEDATA_REG],
			iommu->reg + DMAR_FEDATA_REG);
		writel(iommu->iommu_state[SR_DMAR_FEADDR_REG],
			iommu->reg + DMAR_FEADDR_REG);
		writel(iommu->iommu_state[SR_DMAR_FEUADDR_REG],
			iommu->reg + DMAR_FEUADDR_REG);

3463
		raw_spin_unlock_irqrestore(&iommu->register_lock, flag);
3464 3465 3466 3467 3468 3469
	}

	for_each_active_iommu(iommu, drhd)
		kfree(iommu->iommu_state);
}

3470
static struct syscore_ops iommu_syscore_ops = {
3471 3472 3473 3474
	.resume		= iommu_resume,
	.suspend	= iommu_suspend,
};

3475
static void __init init_iommu_pm_ops(void)
3476
{
3477
	register_syscore_ops(&iommu_syscore_ops);
3478 3479 3480
}

#else
3481
static inline void init_iommu_pm_ops(void) {}
3482 3483
#endif	/* CONFIG_PM */

3484 3485 3486 3487 3488 3489 3490 3491 3492 3493 3494 3495 3496 3497 3498 3499 3500 3501 3502 3503 3504 3505 3506 3507 3508 3509 3510 3511 3512 3513 3514 3515 3516 3517 3518 3519 3520 3521 3522 3523 3524 3525 3526 3527 3528 3529 3530 3531 3532 3533 3534 3535 3536 3537 3538 3539 3540 3541 3542 3543 3544 3545 3546 3547 3548 3549 3550 3551 3552 3553 3554 3555 3556 3557 3558 3559 3560 3561 3562 3563 3564 3565 3566 3567 3568 3569 3570 3571 3572 3573 3574 3575 3576 3577 3578 3579 3580 3581 3582 3583 3584 3585 3586 3587 3588 3589 3590
LIST_HEAD(dmar_rmrr_units);

static void __init dmar_register_rmrr_unit(struct dmar_rmrr_unit *rmrr)
{
	list_add(&rmrr->list, &dmar_rmrr_units);
}


int __init dmar_parse_one_rmrr(struct acpi_dmar_header *header)
{
	struct acpi_dmar_reserved_memory *rmrr;
	struct dmar_rmrr_unit *rmrru;

	rmrru = kzalloc(sizeof(*rmrru), GFP_KERNEL);
	if (!rmrru)
		return -ENOMEM;

	rmrru->hdr = header;
	rmrr = (struct acpi_dmar_reserved_memory *)header;
	rmrru->base_address = rmrr->base_address;
	rmrru->end_address = rmrr->end_address;

	dmar_register_rmrr_unit(rmrru);
	return 0;
}

static int __init
rmrr_parse_dev(struct dmar_rmrr_unit *rmrru)
{
	struct acpi_dmar_reserved_memory *rmrr;
	int ret;

	rmrr = (struct acpi_dmar_reserved_memory *) rmrru->hdr;
	ret = dmar_parse_dev_scope((void *)(rmrr + 1),
		((void *)rmrr) + rmrr->header.length,
		&rmrru->devices_cnt, &rmrru->devices, rmrr->segment);

	if (ret || (rmrru->devices_cnt == 0)) {
		list_del(&rmrru->list);
		kfree(rmrru);
	}
	return ret;
}

static LIST_HEAD(dmar_atsr_units);

int __init dmar_parse_one_atsr(struct acpi_dmar_header *hdr)
{
	struct acpi_dmar_atsr *atsr;
	struct dmar_atsr_unit *atsru;

	atsr = container_of(hdr, struct acpi_dmar_atsr, header);
	atsru = kzalloc(sizeof(*atsru), GFP_KERNEL);
	if (!atsru)
		return -ENOMEM;

	atsru->hdr = hdr;
	atsru->include_all = atsr->flags & 0x1;

	list_add(&atsru->list, &dmar_atsr_units);

	return 0;
}

static int __init atsr_parse_dev(struct dmar_atsr_unit *atsru)
{
	int rc;
	struct acpi_dmar_atsr *atsr;

	if (atsru->include_all)
		return 0;

	atsr = container_of(atsru->hdr, struct acpi_dmar_atsr, header);
	rc = dmar_parse_dev_scope((void *)(atsr + 1),
				(void *)atsr + atsr->header.length,
				&atsru->devices_cnt, &atsru->devices,
				atsr->segment);
	if (rc || !atsru->devices_cnt) {
		list_del(&atsru->list);
		kfree(atsru);
	}

	return rc;
}

int dmar_find_matched_atsr_unit(struct pci_dev *dev)
{
	int i;
	struct pci_bus *bus;
	struct acpi_dmar_atsr *atsr;
	struct dmar_atsr_unit *atsru;

	dev = pci_physfn(dev);

	list_for_each_entry(atsru, &dmar_atsr_units, list) {
		atsr = container_of(atsru->hdr, struct acpi_dmar_atsr, header);
		if (atsr->segment == pci_domain_nr(dev->bus))
			goto found;
	}

	return 0;

found:
	for (bus = dev->bus; bus; bus = bus->parent) {
		struct pci_dev *bridge = bus->self;

		if (!bridge || !pci_is_pcie(bridge) ||
3591
		    pci_pcie_type(bridge) == PCI_EXP_TYPE_PCI_BRIDGE)
3592 3593
			return 0;

3594
		if (pci_pcie_type(bridge) == PCI_EXP_TYPE_ROOT_PORT) {
3595 3596 3597 3598 3599 3600 3601 3602 3603 3604 3605 3606 3607
			for (i = 0; i < atsru->devices_cnt; i++)
				if (atsru->devices[i] == bridge)
					return 1;
			break;
		}
	}

	if (atsru->include_all)
		return 1;

	return 0;
}

3608
int __init dmar_parse_rmrr_atsr_dev(void)
3609 3610 3611 3612 3613 3614 3615 3616 3617 3618 3619 3620 3621 3622 3623 3624 3625 3626 3627 3628
{
	struct dmar_rmrr_unit *rmrr, *rmrr_n;
	struct dmar_atsr_unit *atsr, *atsr_n;
	int ret = 0;

	list_for_each_entry_safe(rmrr, rmrr_n, &dmar_rmrr_units, list) {
		ret = rmrr_parse_dev(rmrr);
		if (ret)
			return ret;
	}

	list_for_each_entry_safe(atsr, atsr_n, &dmar_atsr_units, list) {
		ret = atsr_parse_dev(atsr);
		if (ret)
			return ret;
	}

	return ret;
}

F
Fenghua Yu 已提交
3629 3630 3631 3632 3633 3634 3635 3636 3637 3638 3639 3640 3641
/*
 * Here we only respond to action of unbound device from driver.
 *
 * Added device is not attached to its DMAR domain here yet. That will happen
 * when mapping the device to iova.
 */
static int device_notifier(struct notifier_block *nb,
				  unsigned long action, void *data)
{
	struct device *dev = data;
	struct pci_dev *pdev = to_pci_dev(dev);
	struct dmar_domain *domain;

3642 3643 3644
	if (iommu_no_mapping(dev))
		return 0;

F
Fenghua Yu 已提交
3645 3646 3647 3648
	domain = find_domain(pdev);
	if (!domain)
		return 0;

3649
	if (action == BUS_NOTIFY_UNBOUND_DRIVER && !iommu_pass_through) {
F
Fenghua Yu 已提交
3650 3651
		domain_remove_one_dev_info(domain, pdev);

3652 3653 3654 3655 3656 3657
		if (!(domain->flags & DOMAIN_FLAG_VIRTUAL_MACHINE) &&
		    !(domain->flags & DOMAIN_FLAG_STATIC_IDENTITY) &&
		    list_empty(&domain->devices))
			domain_exit(domain);
	}

F
Fenghua Yu 已提交
3658 3659 3660 3661 3662 3663 3664
	return 0;
}

static struct notifier_block device_nb = {
	.notifier_call = device_notifier,
};

3665 3666 3667 3668
int __init intel_iommu_init(void)
{
	int ret = 0;

3669 3670 3671 3672 3673 3674
	/* VT-d is required for a TXT/tboot launch, so enforce that */
	force_on = tboot_force_iommu();

	if (dmar_table_init()) {
		if (force_on)
			panic("tboot: Failed to initialize DMAR table\n");
3675
		return 	-ENODEV;
3676
	}
3677

3678
	if (dmar_dev_scope_init() < 0) {
3679 3680
		if (force_on)
			panic("tboot: Failed to initialize DMAR device scope\n");
3681
		return 	-ENODEV;
3682
	}
3683

3684
	if (no_iommu || dmar_disabled)
3685 3686
		return -ENODEV;

3687 3688 3689 3690 3691 3692
	if (iommu_init_mempool()) {
		if (force_on)
			panic("tboot: Failed to initialize iommu memory\n");
		return 	-ENODEV;
	}

3693 3694 3695 3696 3697 3698
	if (list_empty(&dmar_rmrr_units))
		printk(KERN_INFO "DMAR: No RMRR found\n");

	if (list_empty(&dmar_atsr_units))
		printk(KERN_INFO "DMAR: No ATSR found\n");

3699 3700 3701 3702 3703
	if (dmar_init_reserved_ranges()) {
		if (force_on)
			panic("tboot: Failed to reserve iommu ranges\n");
		return 	-ENODEV;
	}
3704 3705 3706

	init_no_remapping_devices();

3707
	ret = init_dmars();
3708
	if (ret) {
3709 3710
		if (force_on)
			panic("tboot: Failed to initialize DMARs\n");
3711 3712 3713 3714 3715 3716 3717 3718
		printk(KERN_ERR "IOMMU: dmar init failed\n");
		put_iova_domain(&reserved_iova_list);
		iommu_exit_mempool();
		return ret;
	}
	printk(KERN_INFO
	"PCI-DMA: Intel(R) Virtualization Technology for Directed I/O\n");

M
mark gross 已提交
3719
	init_timer(&unmap_timer);
3720 3721 3722
#ifdef CONFIG_SWIOTLB
	swiotlb = 0;
#endif
3723
	dma_ops = &intel_dma_ops;
F
Fenghua Yu 已提交
3724

3725
	init_iommu_pm_ops();
3726

3727
	bus_set_iommu(&pci_bus_type, &intel_iommu_ops);
3728

F
Fenghua Yu 已提交
3729 3730
	bus_register_notifier(&pci_bus_type, &device_nb);

3731 3732
	intel_iommu_enabled = 1;

3733 3734
	return 0;
}
3735

3736 3737 3738 3739 3740 3741 3742 3743 3744 3745 3746 3747 3748 3749 3750
static void iommu_detach_dependent_devices(struct intel_iommu *iommu,
					   struct pci_dev *pdev)
{
	struct pci_dev *tmp, *parent;

	if (!iommu || !pdev)
		return;

	/* dependent device detach */
	tmp = pci_find_upstream_pcie_bridge(pdev);
	/* Secondary interface's bus number and devfn 0 */
	if (tmp) {
		parent = pdev->bus->self;
		while (parent != tmp) {
			iommu_detach_dev(iommu, parent->bus->number,
3751
					 parent->devfn);
3752 3753
			parent = parent->bus->self;
		}
3754
		if (pci_is_pcie(tmp)) /* this is a PCIe-to-PCI bridge */
3755 3756 3757
			iommu_detach_dev(iommu,
				tmp->subordinate->number, 0);
		else /* this is a legacy PCI bridge */
3758 3759
			iommu_detach_dev(iommu, tmp->bus->number,
					 tmp->devfn);
3760 3761 3762
	}
}

3763
static void domain_remove_one_dev_info(struct dmar_domain *domain,
3764 3765 3766 3767 3768 3769 3770 3771
					  struct pci_dev *pdev)
{
	struct device_domain_info *info;
	struct intel_iommu *iommu;
	unsigned long flags;
	int found = 0;
	struct list_head *entry, *tmp;

3772 3773
	iommu = device_to_iommu(pci_domain_nr(pdev->bus), pdev->bus->number,
				pdev->devfn);
3774 3775 3776 3777 3778 3779
	if (!iommu)
		return;

	spin_lock_irqsave(&device_domain_lock, flags);
	list_for_each_safe(entry, tmp, &domain->devices) {
		info = list_entry(entry, struct device_domain_info, link);
3780 3781
		if (info->segment == pci_domain_nr(pdev->bus) &&
		    info->bus == pdev->bus->number &&
3782
		    info->devfn == pdev->devfn) {
3783
			unlink_domain_info(info);
3784 3785
			spin_unlock_irqrestore(&device_domain_lock, flags);

Y
Yu Zhao 已提交
3786
			iommu_disable_dev_iotlb(info);
3787
			iommu_detach_dev(iommu, info->bus, info->devfn);
3788
			iommu_detach_dependent_devices(iommu, pdev);
3789 3790 3791 3792 3793 3794 3795 3796 3797 3798 3799 3800 3801 3802
			free_devinfo_mem(info);

			spin_lock_irqsave(&device_domain_lock, flags);

			if (found)
				break;
			else
				continue;
		}

		/* if there is no other devices under the same iommu
		 * owned by this domain, clear this iommu in iommu_bmp
		 * update iommu count and coherency
		 */
3803 3804
		if (iommu == device_to_iommu(info->segment, info->bus,
					    info->devfn))
3805 3806 3807
			found = 1;
	}

3808 3809
	spin_unlock_irqrestore(&device_domain_lock, flags);

3810 3811 3812
	if (found == 0) {
		unsigned long tmp_flags;
		spin_lock_irqsave(&domain->iommu_lock, tmp_flags);
3813
		clear_bit(iommu->seq_id, domain->iommu_bmp);
3814
		domain->iommu_count--;
3815
		domain_update_iommu_cap(domain);
3816
		spin_unlock_irqrestore(&domain->iommu_lock, tmp_flags);
3817

3818 3819 3820 3821 3822 3823 3824
		if (!(domain->flags & DOMAIN_FLAG_VIRTUAL_MACHINE) &&
		    !(domain->flags & DOMAIN_FLAG_STATIC_IDENTITY)) {
			spin_lock_irqsave(&iommu->lock, tmp_flags);
			clear_bit(domain->id, iommu->domain_ids);
			iommu->domains[domain->id] = NULL;
			spin_unlock_irqrestore(&iommu->lock, tmp_flags);
		}
3825 3826 3827 3828 3829 3830 3831 3832 3833 3834 3835 3836 3837
	}
}

static void vm_domain_remove_all_dev_info(struct dmar_domain *domain)
{
	struct device_domain_info *info;
	struct intel_iommu *iommu;
	unsigned long flags1, flags2;

	spin_lock_irqsave(&device_domain_lock, flags1);
	while (!list_empty(&domain->devices)) {
		info = list_entry(domain->devices.next,
			struct device_domain_info, link);
3838
		unlink_domain_info(info);
3839 3840
		spin_unlock_irqrestore(&device_domain_lock, flags1);

Y
Yu Zhao 已提交
3841
		iommu_disable_dev_iotlb(info);
3842
		iommu = device_to_iommu(info->segment, info->bus, info->devfn);
3843
		iommu_detach_dev(iommu, info->bus, info->devfn);
3844
		iommu_detach_dependent_devices(iommu, info->dev);
3845 3846

		/* clear this iommu in iommu_bmp, update iommu count
3847
		 * and capabilities
3848 3849 3850
		 */
		spin_lock_irqsave(&domain->iommu_lock, flags2);
		if (test_and_clear_bit(iommu->seq_id,
3851
				       domain->iommu_bmp)) {
3852
			domain->iommu_count--;
3853
			domain_update_iommu_cap(domain);
3854 3855 3856 3857 3858 3859 3860 3861 3862
		}
		spin_unlock_irqrestore(&domain->iommu_lock, flags2);

		free_devinfo_mem(info);
		spin_lock_irqsave(&device_domain_lock, flags1);
	}
	spin_unlock_irqrestore(&device_domain_lock, flags1);
}

3863 3864 3865 3866 3867 3868 3869 3870 3871 3872 3873 3874
/* domain id for virtual machine, it won't be set in context */
static unsigned long vm_domid;

static struct dmar_domain *iommu_alloc_vm_domain(void)
{
	struct dmar_domain *domain;

	domain = alloc_domain_mem();
	if (!domain)
		return NULL;

	domain->id = vm_domid++;
3875
	domain->nid = -1;
3876
	memset(domain->iommu_bmp, 0, sizeof(domain->iommu_bmp));
3877 3878 3879 3880 3881
	domain->flags = DOMAIN_FLAG_VIRTUAL_MACHINE;

	return domain;
}

3882
static int md_domain_init(struct dmar_domain *domain, int guest_width)
3883 3884 3885 3886 3887 3888 3889 3890 3891 3892 3893 3894 3895 3896 3897 3898 3899
{
	int adjust_width;

	init_iova_domain(&domain->iovad, DMA_32BIT_PFN);
	spin_lock_init(&domain->iommu_lock);

	domain_reserve_special_ranges(domain);

	/* calculate AGAW */
	domain->gaw = guest_width;
	adjust_width = guestwidth_to_adjustwidth(guest_width);
	domain->agaw = width_to_agaw(adjust_width);

	INIT_LIST_HEAD(&domain->devices);

	domain->iommu_count = 0;
	domain->iommu_coherency = 0;
3900
	domain->iommu_snooping = 0;
3901
	domain->iommu_superpage = 0;
3902
	domain->max_addr = 0;
3903
	domain->nid = -1;
3904 3905

	/* always allocate the top pgd */
3906
	domain->pgd = (struct dma_pte *)alloc_pgtable_page(domain->nid);
3907 3908 3909 3910 3911 3912 3913 3914 3915 3916 3917 3918 3919 3920 3921 3922 3923 3924 3925 3926
	if (!domain->pgd)
		return -ENOMEM;
	domain_flush_cache(domain, domain->pgd, PAGE_SIZE);
	return 0;
}

static void iommu_free_vm_domain(struct dmar_domain *domain)
{
	unsigned long flags;
	struct dmar_drhd_unit *drhd;
	struct intel_iommu *iommu;
	unsigned long i;
	unsigned long ndomains;

	for_each_drhd_unit(drhd) {
		if (drhd->ignored)
			continue;
		iommu = drhd->iommu;

		ndomains = cap_ndoms(iommu->cap);
3927
		for_each_set_bit(i, iommu->domain_ids, ndomains) {
3928 3929 3930 3931 3932 3933 3934 3935 3936 3937 3938 3939 3940 3941 3942 3943 3944 3945 3946 3947 3948 3949
			if (iommu->domains[i] == domain) {
				spin_lock_irqsave(&iommu->lock, flags);
				clear_bit(i, iommu->domain_ids);
				iommu->domains[i] = NULL;
				spin_unlock_irqrestore(&iommu->lock, flags);
				break;
			}
		}
	}
}

static void vm_domain_exit(struct dmar_domain *domain)
{
	/* Domain 0 is reserved, so dont process it */
	if (!domain)
		return;

	vm_domain_remove_all_dev_info(domain);
	/* destroy iovas */
	put_iova_domain(&domain->iovad);

	/* clear ptes */
3950
	dma_pte_clear_range(domain, 0, DOMAIN_MAX_PFN(domain->gaw));
3951 3952

	/* free page tables */
3953
	dma_pte_free_pagetable(domain, 0, DOMAIN_MAX_PFN(domain->gaw));
3954 3955 3956 3957 3958

	iommu_free_vm_domain(domain);
	free_domain_mem(domain);
}

3959
static int intel_iommu_domain_init(struct iommu_domain *domain)
K
Kay, Allen M 已提交
3960
{
3961
	struct dmar_domain *dmar_domain;
K
Kay, Allen M 已提交
3962

3963 3964
	dmar_domain = iommu_alloc_vm_domain();
	if (!dmar_domain) {
K
Kay, Allen M 已提交
3965
		printk(KERN_ERR
3966 3967
			"intel_iommu_domain_init: dmar_domain == NULL\n");
		return -ENOMEM;
K
Kay, Allen M 已提交
3968
	}
3969
	if (md_domain_init(dmar_domain, DEFAULT_DOMAIN_ADDRESS_WIDTH)) {
K
Kay, Allen M 已提交
3970
		printk(KERN_ERR
3971 3972 3973
			"intel_iommu_domain_init() failed\n");
		vm_domain_exit(dmar_domain);
		return -ENOMEM;
K
Kay, Allen M 已提交
3974
	}
3975
	domain_update_iommu_cap(dmar_domain);
3976
	domain->priv = dmar_domain;
3977

3978 3979 3980 3981
	domain->geometry.aperture_start = 0;
	domain->geometry.aperture_end   = __DOMAIN_MAX_ADDR(dmar_domain->gaw);
	domain->geometry.force_aperture = true;

3982
	return 0;
K
Kay, Allen M 已提交
3983 3984
}

3985
static void intel_iommu_domain_destroy(struct iommu_domain *domain)
K
Kay, Allen M 已提交
3986
{
3987 3988 3989 3990
	struct dmar_domain *dmar_domain = domain->priv;

	domain->priv = NULL;
	vm_domain_exit(dmar_domain);
K
Kay, Allen M 已提交
3991 3992
}

3993 3994
static int intel_iommu_attach_device(struct iommu_domain *domain,
				     struct device *dev)
K
Kay, Allen M 已提交
3995
{
3996 3997
	struct dmar_domain *dmar_domain = domain->priv;
	struct pci_dev *pdev = to_pci_dev(dev);
3998 3999
	struct intel_iommu *iommu;
	int addr_width;
4000 4001 4002 4003 4004 4005 4006

	/* normally pdev is not mapped */
	if (unlikely(domain_context_mapped(pdev))) {
		struct dmar_domain *old_domain;

		old_domain = find_domain(pdev);
		if (old_domain) {
4007 4008 4009
			if (dmar_domain->flags & DOMAIN_FLAG_VIRTUAL_MACHINE ||
			    dmar_domain->flags & DOMAIN_FLAG_STATIC_IDENTITY)
				domain_remove_one_dev_info(old_domain, pdev);
4010 4011 4012 4013 4014
			else
				domain_remove_dev_info(old_domain);
		}
	}

4015 4016
	iommu = device_to_iommu(pci_domain_nr(pdev->bus), pdev->bus->number,
				pdev->devfn);
4017 4018 4019 4020 4021
	if (!iommu)
		return -ENODEV;

	/* check if this iommu agaw is sufficient for max mapped address */
	addr_width = agaw_to_width(iommu->agaw);
4022 4023 4024 4025 4026
	if (addr_width > cap_mgaw(iommu->cap))
		addr_width = cap_mgaw(iommu->cap);

	if (dmar_domain->max_addr > (1LL << addr_width)) {
		printk(KERN_ERR "%s: iommu width (%d) is not "
4027
		       "sufficient for the mapped address (%llx)\n",
4028
		       __func__, addr_width, dmar_domain->max_addr);
4029 4030
		return -EFAULT;
	}
4031 4032 4033 4034 4035 4036 4037 4038 4039 4040
	dmar_domain->gaw = addr_width;

	/*
	 * Knock out extra levels of page tables if necessary
	 */
	while (iommu->agaw < dmar_domain->agaw) {
		struct dma_pte *pte;

		pte = dmar_domain->pgd;
		if (dma_pte_present(pte)) {
4041 4042
			dmar_domain->pgd = (struct dma_pte *)
				phys_to_virt(dma_pte_addr(pte));
4043
			free_pgtable_page(pte);
4044 4045 4046
		}
		dmar_domain->agaw--;
	}
4047

4048
	return domain_add_dev_info(dmar_domain, pdev, CONTEXT_TT_MULTI_LEVEL);
K
Kay, Allen M 已提交
4049 4050
}

4051 4052
static void intel_iommu_detach_device(struct iommu_domain *domain,
				      struct device *dev)
K
Kay, Allen M 已提交
4053
{
4054 4055 4056
	struct dmar_domain *dmar_domain = domain->priv;
	struct pci_dev *pdev = to_pci_dev(dev);

4057
	domain_remove_one_dev_info(dmar_domain, pdev);
4058
}
4059

4060 4061
static int intel_iommu_map(struct iommu_domain *domain,
			   unsigned long iova, phys_addr_t hpa,
4062
			   size_t size, int iommu_prot)
4063
{
4064
	struct dmar_domain *dmar_domain = domain->priv;
4065
	u64 max_addr;
4066
	int prot = 0;
4067
	int ret;
4068

4069 4070 4071 4072
	if (iommu_prot & IOMMU_READ)
		prot |= DMA_PTE_READ;
	if (iommu_prot & IOMMU_WRITE)
		prot |= DMA_PTE_WRITE;
4073 4074
	if ((iommu_prot & IOMMU_CACHE) && dmar_domain->iommu_snooping)
		prot |= DMA_PTE_SNP;
4075

4076
	max_addr = iova + size;
4077
	if (dmar_domain->max_addr < max_addr) {
4078 4079 4080
		u64 end;

		/* check if minimum agaw is sufficient for mapped address */
4081
		end = __DOMAIN_MAX_ADDR(dmar_domain->gaw) + 1;
4082
		if (end < max_addr) {
4083
			printk(KERN_ERR "%s: iommu width (%d) is not "
4084
			       "sufficient for the mapped address (%llx)\n",
4085
			       __func__, dmar_domain->gaw, max_addr);
4086 4087
			return -EFAULT;
		}
4088
		dmar_domain->max_addr = max_addr;
4089
	}
4090 4091
	/* Round up size to next multiple of PAGE_SIZE, if it and
	   the low bits of hpa would take us onto the next page */
4092
	size = aligned_nrpages(hpa, size);
4093 4094
	ret = domain_pfn_mapping(dmar_domain, iova >> VTD_PAGE_SHIFT,
				 hpa >> VTD_PAGE_SHIFT, size, prot);
4095
	return ret;
K
Kay, Allen M 已提交
4096 4097
}

4098 4099
static size_t intel_iommu_unmap(struct iommu_domain *domain,
			     unsigned long iova, size_t size)
K
Kay, Allen M 已提交
4100
{
4101
	struct dmar_domain *dmar_domain = domain->priv;
4102
	int order;
4103

4104
	order = dma_pte_clear_range(dmar_domain, iova >> VTD_PAGE_SHIFT,
4105
			    (iova + size - 1) >> VTD_PAGE_SHIFT);
4106

4107 4108
	if (dmar_domain->max_addr == iova + size)
		dmar_domain->max_addr = iova;
4109

4110
	return PAGE_SIZE << order;
K
Kay, Allen M 已提交
4111 4112
}

4113
static phys_addr_t intel_iommu_iova_to_phys(struct iommu_domain *domain,
4114
					    dma_addr_t iova)
K
Kay, Allen M 已提交
4115
{
4116
	struct dmar_domain *dmar_domain = domain->priv;
K
Kay, Allen M 已提交
4117
	struct dma_pte *pte;
4118
	u64 phys = 0;
K
Kay, Allen M 已提交
4119

4120
	pte = pfn_to_dma_pte(dmar_domain, iova >> VTD_PAGE_SHIFT, 0);
K
Kay, Allen M 已提交
4121
	if (pte)
4122
		phys = dma_pte_addr(pte);
K
Kay, Allen M 已提交
4123

4124
	return phys;
K
Kay, Allen M 已提交
4125
}
4126

S
Sheng Yang 已提交
4127 4128 4129 4130 4131 4132 4133
static int intel_iommu_domain_has_cap(struct iommu_domain *domain,
				      unsigned long cap)
{
	struct dmar_domain *dmar_domain = domain->priv;

	if (cap == IOMMU_CAP_CACHE_COHERENCY)
		return dmar_domain->iommu_snooping;
4134
	if (cap == IOMMU_CAP_INTR_REMAP)
4135
		return irq_remapping_enabled;
S
Sheng Yang 已提交
4136 4137 4138 4139

	return 0;
}

4140
static void swap_pci_ref(struct pci_dev **from, struct pci_dev *to)
4141
{
4142 4143 4144
	pci_dev_put(*from);
	*from = to;
}
4145

4146
#define REQ_ACS_FLAGS	(PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF)
4147

4148 4149 4150
static int intel_iommu_add_device(struct device *dev)
{
	struct pci_dev *pdev = to_pci_dev(dev);
4151
	struct pci_dev *bridge, *dma_pdev = NULL;
4152 4153
	struct iommu_group *group;
	int ret;
4154

4155 4156
	if (!device_to_iommu(pci_domain_nr(pdev->bus),
			     pdev->bus->number, pdev->devfn))
4157 4158 4159 4160
		return -ENODEV;

	bridge = pci_find_upstream_pcie_bridge(pdev);
	if (bridge) {
4161 4162 4163 4164
		if (pci_is_pcie(bridge))
			dma_pdev = pci_get_domain_bus_and_slot(
						pci_domain_nr(pdev->bus),
						bridge->subordinate->number, 0);
4165
		if (!dma_pdev)
4166 4167 4168 4169
			dma_pdev = pci_dev_get(bridge);
	} else
		dma_pdev = pci_dev_get(pdev);

4170
	/* Account for quirked devices */
4171 4172
	swap_pci_ref(&dma_pdev, pci_get_dma_source(dma_pdev));

4173 4174 4175 4176
	/*
	 * If it's a multifunction device that does not support our
	 * required ACS flags, add to the same group as function 0.
	 */
4177 4178 4179 4180 4181 4182 4183
	if (dma_pdev->multifunction &&
	    !pci_acs_enabled(dma_pdev, REQ_ACS_FLAGS))
		swap_pci_ref(&dma_pdev,
			     pci_get_slot(dma_pdev->bus,
					  PCI_DEVFN(PCI_SLOT(dma_pdev->devfn),
					  0)));

4184 4185 4186 4187 4188
	/*
	 * Devices on the root bus go through the iommu.  If that's not us,
	 * find the next upstream device and test ACS up to the root bus.
	 * Finding the next device may require skipping virtual buses.
	 */
4189
	while (!pci_is_root_bus(dma_pdev->bus)) {
4190 4191 4192 4193 4194 4195 4196 4197 4198 4199
		struct pci_bus *bus = dma_pdev->bus;

		while (!bus->self) {
			if (!pci_is_root_bus(bus))
				bus = bus->parent;
			else
				goto root_bus;
		}

		if (pci_acs_path_enabled(bus->self, NULL, REQ_ACS_FLAGS))
4200 4201
			break;

4202
		swap_pci_ref(&dma_pdev, pci_dev_get(bus->self));
4203 4204
	}

4205
root_bus:
4206 4207 4208 4209 4210 4211
	group = iommu_group_get(&dma_pdev->dev);
	pci_dev_put(dma_pdev);
	if (!group) {
		group = iommu_group_alloc();
		if (IS_ERR(group))
			return PTR_ERR(group);
4212 4213
	}

4214
	ret = iommu_group_add_device(group, dev);
4215

4216 4217 4218
	iommu_group_put(group);
	return ret;
}
4219

4220 4221 4222
static void intel_iommu_remove_device(struct device *dev)
{
	iommu_group_remove_device(dev);
4223 4224
}

4225 4226 4227 4228 4229
static struct iommu_ops intel_iommu_ops = {
	.domain_init	= intel_iommu_domain_init,
	.domain_destroy = intel_iommu_domain_destroy,
	.attach_dev	= intel_iommu_attach_device,
	.detach_dev	= intel_iommu_detach_device,
4230 4231
	.map		= intel_iommu_map,
	.unmap		= intel_iommu_unmap,
4232
	.iova_to_phys	= intel_iommu_iova_to_phys,
S
Sheng Yang 已提交
4233
	.domain_has_cap = intel_iommu_domain_has_cap,
4234 4235
	.add_device	= intel_iommu_add_device,
	.remove_device	= intel_iommu_remove_device,
4236
	.pgsize_bitmap	= INTEL_IOMMU_PGSIZES,
4237
};
4238

4239 4240 4241 4242 4243 4244 4245 4246 4247 4248 4249 4250 4251 4252 4253
static void quirk_iommu_g4x_gfx(struct pci_dev *dev)
{
	/* G4x/GM45 integrated gfx dmar support is totally busted. */
	printk(KERN_INFO "DMAR: Disabling IOMMU for graphics on this chipset\n");
	dmar_map_gfx = 0;
}

DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2a40, quirk_iommu_g4x_gfx);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e00, quirk_iommu_g4x_gfx);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e10, quirk_iommu_g4x_gfx);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e20, quirk_iommu_g4x_gfx);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e30, quirk_iommu_g4x_gfx);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e40, quirk_iommu_g4x_gfx);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e90, quirk_iommu_g4x_gfx);

4254
static void quirk_iommu_rwbf(struct pci_dev *dev)
4255 4256 4257
{
	/*
	 * Mobile 4 Series Chipset neglects to set RWBF capability,
4258
	 * but needs it. Same seems to hold for the desktop versions.
4259 4260 4261 4262 4263 4264
	 */
	printk(KERN_INFO "DMAR: Forcing write-buffer flush capability\n");
	rwbf_quirk = 1;
}

DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2a40, quirk_iommu_rwbf);
4265 4266 4267 4268 4269 4270
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e00, quirk_iommu_rwbf);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e10, quirk_iommu_rwbf);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e20, quirk_iommu_rwbf);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e30, quirk_iommu_rwbf);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e40, quirk_iommu_rwbf);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e90, quirk_iommu_rwbf);
4271

4272 4273 4274 4275 4276 4277 4278 4279 4280 4281
#define GGC 0x52
#define GGC_MEMORY_SIZE_MASK	(0xf << 8)
#define GGC_MEMORY_SIZE_NONE	(0x0 << 8)
#define GGC_MEMORY_SIZE_1M	(0x1 << 8)
#define GGC_MEMORY_SIZE_2M	(0x3 << 8)
#define GGC_MEMORY_VT_ENABLED	(0x8 << 8)
#define GGC_MEMORY_SIZE_2M_VT	(0x9 << 8)
#define GGC_MEMORY_SIZE_3M_VT	(0xa << 8)
#define GGC_MEMORY_SIZE_4M_VT	(0xb << 8)

4282
static void quirk_calpella_no_shadow_gtt(struct pci_dev *dev)
4283 4284 4285
{
	unsigned short ggc;

4286
	if (pci_read_config_word(dev, GGC, &ggc))
4287 4288
		return;

4289
	if (!(ggc & GGC_MEMORY_VT_ENABLED)) {
4290 4291
		printk(KERN_INFO "DMAR: BIOS has allocated no shadow GTT; disabling IOMMU for graphics\n");
		dmar_map_gfx = 0;
4292 4293 4294 4295 4296
	} else if (dmar_map_gfx) {
		/* we have to ensure the gfx device is idle before we flush */
		printk(KERN_INFO "DMAR: Disabling batched IOTLB flush on Ironlake\n");
		intel_iommu_strict = 1;
       }
4297 4298 4299 4300 4301 4302
}
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0040, quirk_calpella_no_shadow_gtt);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0044, quirk_calpella_no_shadow_gtt);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0062, quirk_calpella_no_shadow_gtt);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x006a, quirk_calpella_no_shadow_gtt);

4303 4304 4305 4306 4307 4308 4309 4310 4311 4312 4313 4314 4315 4316 4317 4318 4319 4320 4321 4322 4323 4324 4325 4326 4327 4328 4329 4330 4331 4332 4333 4334 4335 4336 4337 4338 4339 4340 4341 4342 4343 4344 4345 4346 4347 4348 4349 4350 4351 4352 4353 4354 4355 4356 4357 4358 4359
/* On Tylersburg chipsets, some BIOSes have been known to enable the
   ISOCH DMAR unit for the Azalia sound device, but not give it any
   TLB entries, which causes it to deadlock. Check for that.  We do
   this in a function called from init_dmars(), instead of in a PCI
   quirk, because we don't want to print the obnoxious "BIOS broken"
   message if VT-d is actually disabled.
*/
static void __init check_tylersburg_isoch(void)
{
	struct pci_dev *pdev;
	uint32_t vtisochctrl;

	/* If there's no Azalia in the system anyway, forget it. */
	pdev = pci_get_device(PCI_VENDOR_ID_INTEL, 0x3a3e, NULL);
	if (!pdev)
		return;
	pci_dev_put(pdev);

	/* System Management Registers. Might be hidden, in which case
	   we can't do the sanity check. But that's OK, because the
	   known-broken BIOSes _don't_ actually hide it, so far. */
	pdev = pci_get_device(PCI_VENDOR_ID_INTEL, 0x342e, NULL);
	if (!pdev)
		return;

	if (pci_read_config_dword(pdev, 0x188, &vtisochctrl)) {
		pci_dev_put(pdev);
		return;
	}

	pci_dev_put(pdev);

	/* If Azalia DMA is routed to the non-isoch DMAR unit, fine. */
	if (vtisochctrl & 1)
		return;

	/* Drop all bits other than the number of TLB entries */
	vtisochctrl &= 0x1c;

	/* If we have the recommended number of TLB entries (16), fine. */
	if (vtisochctrl == 0x10)
		return;

	/* Zero TLB entries? You get to ride the short bus to school. */
	if (!vtisochctrl) {
		WARN(1, "Your BIOS is broken; DMA routed to ISOCH DMAR unit but no TLB space.\n"
		     "BIOS vendor: %s; Ver: %s; Product Version: %s\n",
		     dmi_get_system_info(DMI_BIOS_VENDOR),
		     dmi_get_system_info(DMI_BIOS_VERSION),
		     dmi_get_system_info(DMI_PRODUCT_VERSION));
		iommu_identity_mapping |= IDENTMAP_AZALIA;
		return;
	}
	
	printk(KERN_WARNING "DMAR: Recommended TLB entries for ISOCH unit is 16; your BIOS set %d\n",
	       vtisochctrl);
}