intel-iommu.c 105.8 KB
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/*
 * Copyright (c) 2006, Intel Corporation.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
 * version 2, as published by the Free Software Foundation.
 *
 * This program is distributed in the hope it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 *
 * You should have received a copy of the GNU General Public License along with
 * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
 * Place - Suite 330, Boston, MA 02111-1307 USA.
 *
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 * Copyright (C) 2006-2008 Intel Corporation
 * Author: Ashok Raj <ashok.raj@intel.com>
 * Author: Shaohua Li <shaohua.li@intel.com>
 * Author: Anil S Keshavamurthy <anil.s.keshavamurthy@intel.com>
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 * Author: Fenghua Yu <fenghua.yu@intel.com>
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 */

#include <linux/init.h>
#include <linux/bitmap.h>
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#include <linux/debugfs.h>
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#include <linux/export.h>
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#include <linux/slab.h>
#include <linux/irq.h>
#include <linux/interrupt.h>
#include <linux/spinlock.h>
#include <linux/pci.h>
#include <linux/dmar.h>
#include <linux/dma-mapping.h>
#include <linux/mempool.h>
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#include <linux/timer.h>
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#include <linux/iova.h>
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#include <linux/iommu.h>
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#include <linux/intel-iommu.h>
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#include <linux/syscore_ops.h>
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#include <linux/tboot.h>
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#include <linux/dmi.h>
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#include <linux/pci-ats.h>
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#include <linux/memblock.h>
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#include <asm/irq_remapping.h>
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#include <asm/cacheflush.h>
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#include <asm/iommu.h>
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#define ROOT_SIZE		VTD_PAGE_SIZE
#define CONTEXT_SIZE		VTD_PAGE_SIZE

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#define IS_GFX_DEVICE(pdev) ((pdev->class >> 16) == PCI_BASE_CLASS_DISPLAY)
#define IS_ISA_DEVICE(pdev) ((pdev->class >> 8) == PCI_CLASS_BRIDGE_ISA)
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#define IS_AZALIA(pdev) ((pdev)->vendor == 0x8086 && (pdev)->device == 0x3a3e)
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#define IOAPIC_RANGE_START	(0xfee00000)
#define IOAPIC_RANGE_END	(0xfeefffff)
#define IOVA_START_ADDR		(0x1000)

#define DEFAULT_DOMAIN_ADDRESS_WIDTH 48

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#define MAX_AGAW_WIDTH 64

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#define __DOMAIN_MAX_PFN(gaw)  ((((uint64_t)1) << (gaw-VTD_PAGE_SHIFT)) - 1)
#define __DOMAIN_MAX_ADDR(gaw) ((((uint64_t)1) << gaw) - 1)

/* We limit DOMAIN_MAX_PFN to fit in an unsigned long, and DOMAIN_MAX_ADDR
   to match. That way, we can use 'unsigned long' for PFNs with impunity. */
#define DOMAIN_MAX_PFN(gaw)	((unsigned long) min_t(uint64_t, \
				__DOMAIN_MAX_PFN(gaw), (unsigned long)-1))
#define DOMAIN_MAX_ADDR(gaw)	(((uint64_t)__DOMAIN_MAX_PFN(gaw)) << VTD_PAGE_SHIFT)
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#define IOVA_PFN(addr)		((addr) >> PAGE_SHIFT)
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#define DMA_32BIT_PFN		IOVA_PFN(DMA_BIT_MASK(32))
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#define DMA_64BIT_PFN		IOVA_PFN(DMA_BIT_MASK(64))
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/* page table handling */
#define LEVEL_STRIDE		(9)
#define LEVEL_MASK		(((u64)1 << LEVEL_STRIDE) - 1)

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/*
 * This bitmap is used to advertise the page sizes our hardware support
 * to the IOMMU core, which will then use this information to split
 * physically contiguous memory regions it is mapping into page sizes
 * that we support.
 *
 * Traditionally the IOMMU core just handed us the mappings directly,
 * after making sure the size is an order of a 4KiB page and that the
 * mapping has natural alignment.
 *
 * To retain this behavior, we currently advertise that we support
 * all page sizes that are an order of 4KiB.
 *
 * If at some point we'd like to utilize the IOMMU core's new behavior,
 * we could change this to advertise the real page sizes we support.
 */
#define INTEL_IOMMU_PGSIZES	(~0xFFFUL)

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static inline int agaw_to_level(int agaw)
{
	return agaw + 2;
}

static inline int agaw_to_width(int agaw)
{
	return 30 + agaw * LEVEL_STRIDE;
}

static inline int width_to_agaw(int width)
{
	return (width - 30) / LEVEL_STRIDE;
}

static inline unsigned int level_to_offset_bits(int level)
{
	return (level - 1) * LEVEL_STRIDE;
}

static inline int pfn_level_offset(unsigned long pfn, int level)
{
	return (pfn >> level_to_offset_bits(level)) & LEVEL_MASK;
}

static inline unsigned long level_mask(int level)
{
	return -1UL << level_to_offset_bits(level);
}

static inline unsigned long level_size(int level)
{
	return 1UL << level_to_offset_bits(level);
}

static inline unsigned long align_to_level(unsigned long pfn, int level)
{
	return (pfn + level_size(level) - 1) & level_mask(level);
}
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static inline unsigned long lvl_to_nr_pages(unsigned int lvl)
{
	return  1 << ((lvl - 1) * LEVEL_STRIDE);
}

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/* VT-d pages must always be _smaller_ than MM pages. Otherwise things
   are never going to work. */
static inline unsigned long dma_to_mm_pfn(unsigned long dma_pfn)
{
	return dma_pfn >> (PAGE_SHIFT - VTD_PAGE_SHIFT);
}

static inline unsigned long mm_to_dma_pfn(unsigned long mm_pfn)
{
	return mm_pfn << (PAGE_SHIFT - VTD_PAGE_SHIFT);
}
static inline unsigned long page_to_dma_pfn(struct page *pg)
{
	return mm_to_dma_pfn(page_to_pfn(pg));
}
static inline unsigned long virt_to_dma_pfn(void *p)
{
	return page_to_dma_pfn(virt_to_page(p));
}

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/* global iommu list, set NULL for ignored DMAR units */
static struct intel_iommu **g_iommus;

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static void __init check_tylersburg_isoch(void);
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static int rwbf_quirk;

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/*
 * set to 1 to panic kernel if can't successfully enable VT-d
 * (used when kernel is launched w/ TXT)
 */
static int force_on = 0;

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/*
 * 0: Present
 * 1-11: Reserved
 * 12-63: Context Ptr (12 - (haw-1))
 * 64-127: Reserved
 */
struct root_entry {
	u64	val;
	u64	rsvd1;
};
#define ROOT_ENTRY_NR (VTD_PAGE_SIZE/sizeof(struct root_entry))
static inline bool root_present(struct root_entry *root)
{
	return (root->val & 1);
}
static inline void set_root_present(struct root_entry *root)
{
	root->val |= 1;
}
static inline void set_root_value(struct root_entry *root, unsigned long value)
{
	root->val |= value & VTD_PAGE_MASK;
}

static inline struct context_entry *
get_context_addr_from_root(struct root_entry *root)
{
	return (struct context_entry *)
		(root_present(root)?phys_to_virt(
		root->val & VTD_PAGE_MASK) :
		NULL);
}

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/*
 * low 64 bits:
 * 0: present
 * 1: fault processing disable
 * 2-3: translation type
 * 12-63: address space root
 * high 64 bits:
 * 0-2: address width
 * 3-6: aval
 * 8-23: domain id
 */
struct context_entry {
	u64 lo;
	u64 hi;
};
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static inline bool context_present(struct context_entry *context)
{
	return (context->lo & 1);
}
static inline void context_set_present(struct context_entry *context)
{
	context->lo |= 1;
}

static inline void context_set_fault_enable(struct context_entry *context)
{
	context->lo &= (((u64)-1) << 2) | 1;
}

static inline void context_set_translation_type(struct context_entry *context,
						unsigned long value)
{
	context->lo &= (((u64)-1) << 4) | 3;
	context->lo |= (value & 3) << 2;
}

static inline void context_set_address_root(struct context_entry *context,
					    unsigned long value)
{
	context->lo |= value & VTD_PAGE_MASK;
}

static inline void context_set_address_width(struct context_entry *context,
					     unsigned long value)
{
	context->hi |= value & 7;
}

static inline void context_set_domain_id(struct context_entry *context,
					 unsigned long value)
{
	context->hi |= (value & ((1 << 16) - 1)) << 8;
}

static inline void context_clear_entry(struct context_entry *context)
{
	context->lo = 0;
	context->hi = 0;
}
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/*
 * 0: readable
 * 1: writable
 * 2-6: reserved
 * 7: super page
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 * 8-10: available
 * 11: snoop behavior
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 * 12-63: Host physcial address
 */
struct dma_pte {
	u64 val;
};

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static inline void dma_clear_pte(struct dma_pte *pte)
{
	pte->val = 0;
}

static inline void dma_set_pte_readable(struct dma_pte *pte)
{
	pte->val |= DMA_PTE_READ;
}

static inline void dma_set_pte_writable(struct dma_pte *pte)
{
	pte->val |= DMA_PTE_WRITE;
}

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static inline void dma_set_pte_snp(struct dma_pte *pte)
{
	pte->val |= DMA_PTE_SNP;
}

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static inline void dma_set_pte_prot(struct dma_pte *pte, unsigned long prot)
{
	pte->val = (pte->val & ~3) | (prot & 3);
}

static inline u64 dma_pte_addr(struct dma_pte *pte)
{
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#ifdef CONFIG_64BIT
	return pte->val & VTD_PAGE_MASK;
#else
	/* Must have a full atomic 64-bit read */
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	return  __cmpxchg64(&pte->val, 0ULL, 0ULL) & VTD_PAGE_MASK;
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#endif
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}

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static inline void dma_set_pte_pfn(struct dma_pte *pte, unsigned long pfn)
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{
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	pte->val |= (uint64_t)pfn << VTD_PAGE_SHIFT;
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}

static inline bool dma_pte_present(struct dma_pte *pte)
{
	return (pte->val & 3) != 0;
}
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static inline bool dma_pte_superpage(struct dma_pte *pte)
{
	return (pte->val & (1 << 7));
}

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static inline int first_pte_in_page(struct dma_pte *pte)
{
	return !((unsigned long)pte & ~VTD_PAGE_MASK);
}

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/*
 * This domain is a statically identity mapping domain.
 *	1. This domain creats a static 1:1 mapping to all usable memory.
 * 	2. It maps to each iommu if successful.
 *	3. Each iommu mapps to this domain if successful.
 */
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static struct dmar_domain *si_domain;
static int hw_pass_through = 1;
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/* devices under the same p2p bridge are owned in one domain */
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#define DOMAIN_FLAG_P2P_MULTIPLE_DEVICES (1 << 0)
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/* domain represents a virtual machine, more than one devices
 * across iommus may be owned in one domain, e.g. kvm guest.
 */
#define DOMAIN_FLAG_VIRTUAL_MACHINE	(1 << 1)

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/* si_domain contains mulitple devices */
#define DOMAIN_FLAG_STATIC_IDENTITY	(1 << 2)

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/* define the limit of IOMMUs supported in each domain */
#ifdef	CONFIG_X86
# define	IOMMU_UNITS_SUPPORTED	MAX_IO_APICS
#else
# define	IOMMU_UNITS_SUPPORTED	64
#endif

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struct dmar_domain {
	int	id;			/* domain id */
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	int	nid;			/* node id */
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	DECLARE_BITMAP(iommu_bmp, IOMMU_UNITS_SUPPORTED);
					/* bitmap of iommus this domain uses*/
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	struct list_head devices; 	/* all devices' list */
	struct iova_domain iovad;	/* iova's that belong to this domain */

	struct dma_pte	*pgd;		/* virtual address */
	int		gaw;		/* max guest address width */

	/* adjusted guest address width, 0 is level 2 30-bit */
	int		agaw;

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	int		flags;		/* flags to find out type of domain */
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	int		iommu_coherency;/* indicate coherency of iommu access */
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	int		iommu_snooping; /* indicate snooping control feature*/
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	int		iommu_count;	/* reference count of iommu */
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	int		iommu_superpage;/* Level of superpages supported:
					   0 == 4KiB (no superpages), 1 == 2MiB,
					   2 == 1GiB, 3 == 512GiB, 4 == 1TiB */
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	spinlock_t	iommu_lock;	/* protect iommu set in domain */
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	u64		max_addr;	/* maximum mapped address */
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};

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/* PCI domain-device relationship */
struct device_domain_info {
	struct list_head link;	/* link to domain siblings */
	struct list_head global; /* link to global list */
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	int segment;		/* PCI domain */
	u8 bus;			/* PCI bus number */
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	u8 devfn;		/* PCI devfn number */
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	struct pci_dev *dev; /* it's NULL for PCIe-to-PCI bridge */
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	struct intel_iommu *iommu; /* IOMMU used by this device */
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	struct dmar_domain *domain; /* pointer to domain */
};

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static void flush_unmaps_timeout(unsigned long data);

DEFINE_TIMER(unmap_timer,  flush_unmaps_timeout, 0, 0);

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#define HIGH_WATER_MARK 250
struct deferred_flush_tables {
	int next;
	struct iova *iova[HIGH_WATER_MARK];
	struct dmar_domain *domain[HIGH_WATER_MARK];
};

static struct deferred_flush_tables *deferred_flush;

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/* bitmap for indexing intel_iommus */
static int g_num_of_iommus;

static DEFINE_SPINLOCK(async_umap_flush_lock);
static LIST_HEAD(unmaps_to_do);

static int timer_on;
static long list_size;

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static void domain_remove_dev_info(struct dmar_domain *domain);

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#ifdef CONFIG_INTEL_IOMMU_DEFAULT_ON
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int dmar_disabled = 0;
#else
int dmar_disabled = 1;
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#endif /*CONFIG_INTEL_IOMMU_DEFAULT_ON*/
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int intel_iommu_enabled = 0;
EXPORT_SYMBOL_GPL(intel_iommu_enabled);

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static int dmar_map_gfx = 1;
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static int dmar_forcedac;
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static int intel_iommu_strict;
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static int intel_iommu_superpage = 1;
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int intel_iommu_gfx_mapped;
EXPORT_SYMBOL_GPL(intel_iommu_gfx_mapped);

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#define DUMMY_DEVICE_DOMAIN_INFO ((struct device_domain_info *)(-1))
static DEFINE_SPINLOCK(device_domain_lock);
static LIST_HEAD(device_domain_list);

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static struct iommu_ops intel_iommu_ops;

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static int __init intel_iommu_setup(char *str)
{
	if (!str)
		return -EINVAL;
	while (*str) {
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		if (!strncmp(str, "on", 2)) {
			dmar_disabled = 0;
			printk(KERN_INFO "Intel-IOMMU: enabled\n");
		} else if (!strncmp(str, "off", 3)) {
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			dmar_disabled = 1;
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			printk(KERN_INFO "Intel-IOMMU: disabled\n");
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		} else if (!strncmp(str, "igfx_off", 8)) {
			dmar_map_gfx = 0;
			printk(KERN_INFO
				"Intel-IOMMU: disable GFX device mapping\n");
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		} else if (!strncmp(str, "forcedac", 8)) {
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			printk(KERN_INFO
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				"Intel-IOMMU: Forcing DAC for PCI devices\n");
			dmar_forcedac = 1;
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		} else if (!strncmp(str, "strict", 6)) {
			printk(KERN_INFO
				"Intel-IOMMU: disable batched IOTLB flush\n");
			intel_iommu_strict = 1;
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		} else if (!strncmp(str, "sp_off", 6)) {
			printk(KERN_INFO
				"Intel-IOMMU: disable supported super page\n");
			intel_iommu_superpage = 0;
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		}

		str += strcspn(str, ",");
		while (*str == ',')
			str++;
	}
	return 0;
}
__setup("intel_iommu=", intel_iommu_setup);

static struct kmem_cache *iommu_domain_cache;
static struct kmem_cache *iommu_devinfo_cache;
static struct kmem_cache *iommu_iova_cache;

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static inline void *alloc_pgtable_page(int node)
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{
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	struct page *page;
	void *vaddr = NULL;
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	page = alloc_pages_node(node, GFP_ATOMIC | __GFP_ZERO, 0);
	if (page)
		vaddr = page_address(page);
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	return vaddr;
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}

static inline void free_pgtable_page(void *vaddr)
{
	free_page((unsigned long)vaddr);
}

static inline void *alloc_domain_mem(void)
{
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	return kmem_cache_alloc(iommu_domain_cache, GFP_ATOMIC);
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}

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static void free_domain_mem(void *vaddr)
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{
	kmem_cache_free(iommu_domain_cache, vaddr);
}

static inline void * alloc_devinfo_mem(void)
{
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	return kmem_cache_alloc(iommu_devinfo_cache, GFP_ATOMIC);
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}

static inline void free_devinfo_mem(void *vaddr)
{
	kmem_cache_free(iommu_devinfo_cache, vaddr);
}

struct iova *alloc_iova_mem(void)
{
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	return kmem_cache_alloc(iommu_iova_cache, GFP_ATOMIC);
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}

void free_iova_mem(struct iova *iova)
{
	kmem_cache_free(iommu_iova_cache, iova);
}

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static int __iommu_calculate_agaw(struct intel_iommu *iommu, int max_gaw)
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{
	unsigned long sagaw;
	int agaw = -1;

	sagaw = cap_sagaw(iommu->cap);
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	for (agaw = width_to_agaw(max_gaw);
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	     agaw >= 0; agaw--) {
		if (test_bit(agaw, &sagaw))
			break;
	}

	return agaw;
}

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/*
 * Calculate max SAGAW for each iommu.
 */
int iommu_calculate_max_sagaw(struct intel_iommu *iommu)
{
	return __iommu_calculate_agaw(iommu, MAX_AGAW_WIDTH);
}

/*
 * calculate agaw for each iommu.
 * "SAGAW" may be different across iommus, use a default agaw, and
 * get a supported less agaw for iommus that don't support the default agaw.
 */
int iommu_calculate_agaw(struct intel_iommu *iommu)
{
	return __iommu_calculate_agaw(iommu, DEFAULT_DOMAIN_ADDRESS_WIDTH);
}

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/* This functionin only returns single iommu in a domain */
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static struct intel_iommu *domain_get_iommu(struct dmar_domain *domain)
{
	int iommu_id;

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	/* si_domain and vm domain should not get here. */
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	BUG_ON(domain->flags & DOMAIN_FLAG_VIRTUAL_MACHINE);
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	BUG_ON(domain->flags & DOMAIN_FLAG_STATIC_IDENTITY);
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	iommu_id = find_first_bit(domain->iommu_bmp, g_num_of_iommus);
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	if (iommu_id < 0 || iommu_id >= g_num_of_iommus)
		return NULL;

	return g_iommus[iommu_id];
}

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static void domain_update_iommu_coherency(struct dmar_domain *domain)
{
	int i;

	domain->iommu_coherency = 1;

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	for_each_set_bit(i, domain->iommu_bmp, g_num_of_iommus) {
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		if (!ecap_coherent(g_iommus[i]->ecap)) {
			domain->iommu_coherency = 0;
			break;
		}
	}
}

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static void domain_update_iommu_snooping(struct dmar_domain *domain)
{
	int i;

	domain->iommu_snooping = 1;

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	for_each_set_bit(i, domain->iommu_bmp, g_num_of_iommus) {
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		if (!ecap_sc_support(g_iommus[i]->ecap)) {
			domain->iommu_snooping = 0;
			break;
		}
	}
}

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static void domain_update_iommu_superpage(struct dmar_domain *domain)
{
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	struct dmar_drhd_unit *drhd;
	struct intel_iommu *iommu = NULL;
	int mask = 0xf;
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	if (!intel_iommu_superpage) {
		domain->iommu_superpage = 0;
		return;
	}

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	/* set iommu_superpage to the smallest common denominator */
	for_each_active_iommu(iommu, drhd) {
		mask &= cap_super_page_val(iommu->cap);
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		if (!mask) {
			break;
		}
	}
	domain->iommu_superpage = fls(mask);
}

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/* Some capabilities may be different across iommus */
static void domain_update_iommu_cap(struct dmar_domain *domain)
{
	domain_update_iommu_coherency(domain);
	domain_update_iommu_snooping(domain);
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	domain_update_iommu_superpage(domain);
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}

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static struct intel_iommu *device_to_iommu(int segment, u8 bus, u8 devfn)
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{
	struct dmar_drhd_unit *drhd = NULL;
	int i;

	for_each_drhd_unit(drhd) {
		if (drhd->ignored)
			continue;
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		if (segment != drhd->segment)
			continue;
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		for (i = 0; i < drhd->devices_cnt; i++) {
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			if (drhd->devices[i] &&
			    drhd->devices[i]->bus->number == bus &&
659 660
			    drhd->devices[i]->devfn == devfn)
				return drhd->iommu;
661 662
			if (drhd->devices[i] &&
			    drhd->devices[i]->subordinate &&
663
			    drhd->devices[i]->subordinate->number <= bus &&
664
			    drhd->devices[i]->subordinate->busn_res.end >= bus)
665 666
				return drhd->iommu;
		}
667 668 669 670 671 672 673 674

		if (drhd->include_all)
			return drhd->iommu;
	}

	return NULL;
}

W
Weidong Han 已提交
675 676 677 678 679 680 681
static void domain_flush_cache(struct dmar_domain *domain,
			       void *addr, int size)
{
	if (!domain->iommu_coherency)
		clflush_cache_range(addr, size);
}

682 683 684 685 686 687 688 689 690 691 692 693 694
/* Gets context entry for a given bus and devfn */
static struct context_entry * device_to_context_entry(struct intel_iommu *iommu,
		u8 bus, u8 devfn)
{
	struct root_entry *root;
	struct context_entry *context;
	unsigned long phy_addr;
	unsigned long flags;

	spin_lock_irqsave(&iommu->lock, flags);
	root = &iommu->root_entry[bus];
	context = get_context_addr_from_root(root);
	if (!context) {
695 696
		context = (struct context_entry *)
				alloc_pgtable_page(iommu->node);
697 698 699 700
		if (!context) {
			spin_unlock_irqrestore(&iommu->lock, flags);
			return NULL;
		}
F
Fenghua Yu 已提交
701
		__iommu_flush_cache(iommu, (void *)context, CONTEXT_SIZE);
702 703 704 705 706 707 708 709 710 711 712 713 714 715 716 717 718 719 720 721 722 723 724
		phy_addr = virt_to_phys((void *)context);
		set_root_value(root, phy_addr);
		set_root_present(root);
		__iommu_flush_cache(iommu, root, sizeof(*root));
	}
	spin_unlock_irqrestore(&iommu->lock, flags);
	return &context[devfn];
}

static int device_context_mapped(struct intel_iommu *iommu, u8 bus, u8 devfn)
{
	struct root_entry *root;
	struct context_entry *context;
	int ret;
	unsigned long flags;

	spin_lock_irqsave(&iommu->lock, flags);
	root = &iommu->root_entry[bus];
	context = get_context_addr_from_root(root);
	if (!context) {
		ret = 0;
		goto out;
	}
725
	ret = context_present(&context[devfn]);
726 727 728 729 730 731 732 733 734 735 736 737 738 739 740
out:
	spin_unlock_irqrestore(&iommu->lock, flags);
	return ret;
}

static void clear_context_table(struct intel_iommu *iommu, u8 bus, u8 devfn)
{
	struct root_entry *root;
	struct context_entry *context;
	unsigned long flags;

	spin_lock_irqsave(&iommu->lock, flags);
	root = &iommu->root_entry[bus];
	context = get_context_addr_from_root(root);
	if (context) {
741
		context_clear_entry(&context[devfn]);
742 743 744 745 746 747 748 749 750 751 752 753 754 755 756 757 758 759 760 761 762 763 764 765 766 767 768 769 770
		__iommu_flush_cache(iommu, &context[devfn], \
			sizeof(*context));
	}
	spin_unlock_irqrestore(&iommu->lock, flags);
}

static void free_context_table(struct intel_iommu *iommu)
{
	struct root_entry *root;
	int i;
	unsigned long flags;
	struct context_entry *context;

	spin_lock_irqsave(&iommu->lock, flags);
	if (!iommu->root_entry) {
		goto out;
	}
	for (i = 0; i < ROOT_ENTRY_NR; i++) {
		root = &iommu->root_entry[i];
		context = get_context_addr_from_root(root);
		if (context)
			free_pgtable_page(context);
	}
	free_pgtable_page(iommu->root_entry);
	iommu->root_entry = NULL;
out:
	spin_unlock_irqrestore(&iommu->lock, flags);
}

771
static struct dma_pte *pfn_to_dma_pte(struct dmar_domain *domain,
772
				      unsigned long pfn, int target_level)
773
{
774
	int addr_width = agaw_to_width(domain->agaw) - VTD_PAGE_SHIFT;
775 776
	struct dma_pte *parent, *pte = NULL;
	int level = agaw_to_level(domain->agaw);
777
	int offset;
778 779

	BUG_ON(!domain->pgd);
780
	BUG_ON(addr_width < BITS_PER_LONG && pfn >> addr_width);
781 782 783 784 785
	parent = domain->pgd;

	while (level > 0) {
		void *tmp_page;

786
		offset = pfn_level_offset(pfn, level);
787
		pte = &parent[offset];
788
		if (!target_level && (dma_pte_superpage(pte) || !dma_pte_present(pte)))
789 790
			break;
		if (level == target_level)
791 792
			break;

793
		if (!dma_pte_present(pte)) {
794 795
			uint64_t pteval;

796
			tmp_page = alloc_pgtable_page(domain->nid);
797

798
			if (!tmp_page)
799
				return NULL;
800

801
			domain_flush_cache(domain, tmp_page, VTD_PAGE_SIZE);
802
			pteval = ((uint64_t)virt_to_dma_pfn(tmp_page) << VTD_PAGE_SHIFT) | DMA_PTE_READ | DMA_PTE_WRITE;
803 804 805 806 807 808 809
			if (cmpxchg64(&pte->val, 0ULL, pteval)) {
				/* Someone else set it while we were thinking; use theirs. */
				free_pgtable_page(tmp_page);
			} else {
				dma_pte_addr(pte);
				domain_flush_cache(domain, pte, sizeof(*pte));
			}
810
		}
811
		parent = phys_to_virt(dma_pte_addr(pte));
812 813 814 815 816 817
		level--;
	}

	return pte;
}

818

819
/* return address's pte at specific level */
820 821
static struct dma_pte *dma_pfn_level_pte(struct dmar_domain *domain,
					 unsigned long pfn,
822
					 int level, int *large_page)
823 824 825 826 827 828 829
{
	struct dma_pte *parent, *pte = NULL;
	int total = agaw_to_level(domain->agaw);
	int offset;

	parent = domain->pgd;
	while (level <= total) {
830
		offset = pfn_level_offset(pfn, total);
831 832 833 834
		pte = &parent[offset];
		if (level == total)
			return pte;

835 836
		if (!dma_pte_present(pte)) {
			*large_page = total;
837
			break;
838 839 840 841 842 843 844
		}

		if (pte->val & DMA_PTE_LARGE_PAGE) {
			*large_page = total;
			return pte;
		}

845
		parent = phys_to_virt(dma_pte_addr(pte));
846 847 848 849 850 851
		total--;
	}
	return NULL;
}

/* clear last level pte, a tlb flush should be followed */
852
static int dma_pte_clear_range(struct dmar_domain *domain,
853 854
				unsigned long start_pfn,
				unsigned long last_pfn)
855
{
856
	int addr_width = agaw_to_width(domain->agaw) - VTD_PAGE_SHIFT;
857
	unsigned int large_page = 1;
858
	struct dma_pte *first_pte, *pte;
859
	int order;
860

861
	BUG_ON(addr_width < BITS_PER_LONG && start_pfn >> addr_width);
862
	BUG_ON(addr_width < BITS_PER_LONG && last_pfn >> addr_width);
863
	BUG_ON(start_pfn > last_pfn);
864

865
	/* we don't need lock here; nobody else touches the iova range */
866
	do {
867 868
		large_page = 1;
		first_pte = pte = dma_pfn_level_pte(domain, start_pfn, 1, &large_page);
869
		if (!pte) {
870
			start_pfn = align_to_level(start_pfn + 1, large_page + 1);
871 872
			continue;
		}
873
		do {
874
			dma_clear_pte(pte);
875
			start_pfn += lvl_to_nr_pages(large_page);
876
			pte++;
877 878
		} while (start_pfn <= last_pfn && !first_pte_in_page(pte));

879 880
		domain_flush_cache(domain, first_pte,
				   (void *)pte - (void *)first_pte);
881 882

	} while (start_pfn && start_pfn <= last_pfn);
883 884 885

	order = (large_page - 1) * 9;
	return order;
886 887 888 889
}

/* free page table pages. last level pte should already be cleared */
static void dma_pte_free_pagetable(struct dmar_domain *domain,
890 891
				   unsigned long start_pfn,
				   unsigned long last_pfn)
892
{
893
	int addr_width = agaw_to_width(domain->agaw) - VTD_PAGE_SHIFT;
894
	struct dma_pte *first_pte, *pte;
895 896
	int total = agaw_to_level(domain->agaw);
	int level;
897
	unsigned long tmp;
898
	int large_page = 2;
899

900 901
	BUG_ON(addr_width < BITS_PER_LONG && start_pfn >> addr_width);
	BUG_ON(addr_width < BITS_PER_LONG && last_pfn >> addr_width);
902
	BUG_ON(start_pfn > last_pfn);
903

904
	/* We don't need lock here; nobody else touches the iova range */
905 906
	level = 2;
	while (level <= total) {
907 908
		tmp = align_to_level(start_pfn, level);

909
		/* If we can't even clear one PTE at this level, we're done */
910
		if (tmp + level_size(level) - 1 > last_pfn)
911 912
			return;

913
		do {
914 915 916 917
			large_page = level;
			first_pte = pte = dma_pfn_level_pte(domain, tmp, level, &large_page);
			if (large_page > level)
				level = large_page + 1;
918 919 920 921
			if (!pte) {
				tmp = align_to_level(tmp + 1, level + 1);
				continue;
			}
922
			do {
923 924 925 926
				if (dma_pte_present(pte)) {
					free_pgtable_page(phys_to_virt(dma_pte_addr(pte)));
					dma_clear_pte(pte);
				}
927 928
				pte++;
				tmp += level_size(level);
929 930 931
			} while (!first_pte_in_page(pte) &&
				 tmp + level_size(level) - 1 <= last_pfn);

932 933 934
			domain_flush_cache(domain, first_pte,
					   (void *)pte - (void *)first_pte);
			
935
		} while (tmp && tmp + level_size(level) - 1 <= last_pfn);
936 937 938
		level++;
	}
	/* free pgd */
939
	if (start_pfn == 0 && last_pfn == DOMAIN_MAX_PFN(domain->gaw)) {
940 941 942 943 944 945 946 947 948 949 950
		free_pgtable_page(domain->pgd);
		domain->pgd = NULL;
	}
}

/* iommu handling */
static int iommu_alloc_root_entry(struct intel_iommu *iommu)
{
	struct root_entry *root;
	unsigned long flags;

951
	root = (struct root_entry *)alloc_pgtable_page(iommu->node);
952 953 954
	if (!root)
		return -ENOMEM;

F
Fenghua Yu 已提交
955
	__iommu_flush_cache(iommu, root, ROOT_SIZE);
956 957 958 959 960 961 962 963 964 965 966

	spin_lock_irqsave(&iommu->lock, flags);
	iommu->root_entry = root;
	spin_unlock_irqrestore(&iommu->lock, flags);

	return 0;
}

static void iommu_set_root_entry(struct intel_iommu *iommu)
{
	void *addr;
967
	u32 sts;
968 969 970 971
	unsigned long flag;

	addr = iommu->root_entry;

972
	raw_spin_lock_irqsave(&iommu->register_lock, flag);
973 974
	dmar_writeq(iommu->reg + DMAR_RTADDR_REG, virt_to_phys(addr));

975
	writel(iommu->gcmd | DMA_GCMD_SRTP, iommu->reg + DMAR_GCMD_REG);
976 977 978

	/* Make sure hardware complete it */
	IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
979
		      readl, (sts & DMA_GSTS_RTPS), sts);
980

981
	raw_spin_unlock_irqrestore(&iommu->register_lock, flag);
982 983 984 985 986 987 988
}

static void iommu_flush_write_buffer(struct intel_iommu *iommu)
{
	u32 val;
	unsigned long flag;

989
	if (!rwbf_quirk && !cap_rwbf(iommu->cap))
990 991
		return;

992
	raw_spin_lock_irqsave(&iommu->register_lock, flag);
993
	writel(iommu->gcmd | DMA_GCMD_WBF, iommu->reg + DMAR_GCMD_REG);
994 995 996

	/* Make sure hardware complete it */
	IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
997
		      readl, (!(val & DMA_GSTS_WBFS)), val);
998

999
	raw_spin_unlock_irqrestore(&iommu->register_lock, flag);
1000 1001 1002
}

/* return value determine if we need a write buffer flush */
1003 1004 1005
static void __iommu_flush_context(struct intel_iommu *iommu,
				  u16 did, u16 source_id, u8 function_mask,
				  u64 type)
1006 1007 1008 1009 1010 1011 1012 1013 1014 1015 1016 1017 1018 1019 1020 1021 1022 1023 1024 1025
{
	u64 val = 0;
	unsigned long flag;

	switch (type) {
	case DMA_CCMD_GLOBAL_INVL:
		val = DMA_CCMD_GLOBAL_INVL;
		break;
	case DMA_CCMD_DOMAIN_INVL:
		val = DMA_CCMD_DOMAIN_INVL|DMA_CCMD_DID(did);
		break;
	case DMA_CCMD_DEVICE_INVL:
		val = DMA_CCMD_DEVICE_INVL|DMA_CCMD_DID(did)
			| DMA_CCMD_SID(source_id) | DMA_CCMD_FM(function_mask);
		break;
	default:
		BUG();
	}
	val |= DMA_CCMD_ICC;

1026
	raw_spin_lock_irqsave(&iommu->register_lock, flag);
1027 1028 1029 1030 1031 1032
	dmar_writeq(iommu->reg + DMAR_CCMD_REG, val);

	/* Make sure hardware complete it */
	IOMMU_WAIT_OP(iommu, DMAR_CCMD_REG,
		dmar_readq, (!(val & DMA_CCMD_ICC)), val);

1033
	raw_spin_unlock_irqrestore(&iommu->register_lock, flag);
1034 1035 1036
}

/* return value determine if we need a write buffer flush */
1037 1038
static void __iommu_flush_iotlb(struct intel_iommu *iommu, u16 did,
				u64 addr, unsigned int size_order, u64 type)
1039 1040 1041 1042 1043 1044 1045 1046 1047 1048 1049 1050 1051 1052 1053 1054 1055 1056 1057 1058 1059 1060 1061 1062 1063 1064 1065 1066 1067 1068 1069 1070 1071
{
	int tlb_offset = ecap_iotlb_offset(iommu->ecap);
	u64 val = 0, val_iva = 0;
	unsigned long flag;

	switch (type) {
	case DMA_TLB_GLOBAL_FLUSH:
		/* global flush doesn't need set IVA_REG */
		val = DMA_TLB_GLOBAL_FLUSH|DMA_TLB_IVT;
		break;
	case DMA_TLB_DSI_FLUSH:
		val = DMA_TLB_DSI_FLUSH|DMA_TLB_IVT|DMA_TLB_DID(did);
		break;
	case DMA_TLB_PSI_FLUSH:
		val = DMA_TLB_PSI_FLUSH|DMA_TLB_IVT|DMA_TLB_DID(did);
		/* Note: always flush non-leaf currently */
		val_iva = size_order | addr;
		break;
	default:
		BUG();
	}
	/* Note: set drain read/write */
#if 0
	/*
	 * This is probably to be super secure.. Looks like we can
	 * ignore it without any impact.
	 */
	if (cap_read_drain(iommu->cap))
		val |= DMA_TLB_READ_DRAIN;
#endif
	if (cap_write_drain(iommu->cap))
		val |= DMA_TLB_WRITE_DRAIN;

1072
	raw_spin_lock_irqsave(&iommu->register_lock, flag);
1073 1074 1075 1076 1077 1078 1079 1080 1081
	/* Note: Only uses first TLB reg currently */
	if (val_iva)
		dmar_writeq(iommu->reg + tlb_offset, val_iva);
	dmar_writeq(iommu->reg + tlb_offset + 8, val);

	/* Make sure hardware complete it */
	IOMMU_WAIT_OP(iommu, tlb_offset + 8,
		dmar_readq, (!(val & DMA_TLB_IVT)), val);

1082
	raw_spin_unlock_irqrestore(&iommu->register_lock, flag);
1083 1084 1085 1086 1087 1088

	/* check IOTLB invalidation granularity */
	if (DMA_TLB_IAIG(val) == 0)
		printk(KERN_ERR"IOMMU: flush IOTLB failed\n");
	if (DMA_TLB_IAIG(val) != DMA_TLB_IIRG(type))
		pr_debug("IOMMU: tlb flush request %Lx, actual %Lx\n",
F
Fenghua Yu 已提交
1089 1090
			(unsigned long long)DMA_TLB_IIRG(type),
			(unsigned long long)DMA_TLB_IAIG(val));
1091 1092
}

Y
Yu Zhao 已提交
1093 1094 1095 1096 1097 1098 1099 1100 1101 1102 1103 1104 1105 1106 1107 1108 1109 1110 1111 1112 1113 1114 1115 1116 1117 1118 1119 1120 1121 1122 1123 1124 1125 1126 1127 1128 1129
static struct device_domain_info *iommu_support_dev_iotlb(
	struct dmar_domain *domain, int segment, u8 bus, u8 devfn)
{
	int found = 0;
	unsigned long flags;
	struct device_domain_info *info;
	struct intel_iommu *iommu = device_to_iommu(segment, bus, devfn);

	if (!ecap_dev_iotlb_support(iommu->ecap))
		return NULL;

	if (!iommu->qi)
		return NULL;

	spin_lock_irqsave(&device_domain_lock, flags);
	list_for_each_entry(info, &domain->devices, link)
		if (info->bus == bus && info->devfn == devfn) {
			found = 1;
			break;
		}
	spin_unlock_irqrestore(&device_domain_lock, flags);

	if (!found || !info->dev)
		return NULL;

	if (!pci_find_ext_capability(info->dev, PCI_EXT_CAP_ID_ATS))
		return NULL;

	if (!dmar_find_matched_atsr_unit(info->dev))
		return NULL;

	info->iommu = iommu;

	return info;
}

static void iommu_enable_dev_iotlb(struct device_domain_info *info)
1130
{
Y
Yu Zhao 已提交
1131 1132 1133 1134 1135 1136 1137 1138 1139 1140 1141 1142 1143 1144 1145 1146 1147 1148 1149 1150 1151 1152 1153 1154 1155 1156 1157 1158 1159 1160 1161 1162 1163
	if (!info)
		return;

	pci_enable_ats(info->dev, VTD_PAGE_SHIFT);
}

static void iommu_disable_dev_iotlb(struct device_domain_info *info)
{
	if (!info->dev || !pci_ats_enabled(info->dev))
		return;

	pci_disable_ats(info->dev);
}

static void iommu_flush_dev_iotlb(struct dmar_domain *domain,
				  u64 addr, unsigned mask)
{
	u16 sid, qdep;
	unsigned long flags;
	struct device_domain_info *info;

	spin_lock_irqsave(&device_domain_lock, flags);
	list_for_each_entry(info, &domain->devices, link) {
		if (!info->dev || !pci_ats_enabled(info->dev))
			continue;

		sid = info->bus << 8 | info->devfn;
		qdep = pci_ats_queue_depth(info->dev);
		qi_flush_dev_iotlb(info->iommu, sid, qdep, addr, mask);
	}
	spin_unlock_irqrestore(&device_domain_lock, flags);
}

1164
static void iommu_flush_iotlb_psi(struct intel_iommu *iommu, u16 did,
1165
				  unsigned long pfn, unsigned int pages, int map)
1166
{
1167
	unsigned int mask = ilog2(__roundup_pow_of_two(pages));
1168
	uint64_t addr = (uint64_t)pfn << VTD_PAGE_SHIFT;
1169 1170 1171 1172

	BUG_ON(pages == 0);

	/*
1173 1174
	 * Fallback to domain selective flush if no PSI support or the size is
	 * too big.
1175 1176 1177
	 * PSI requires page size to be 2 ^ x, and the base address is naturally
	 * aligned to the size
	 */
1178 1179
	if (!cap_pgsel_inv(iommu->cap) || mask > cap_max_amask_val(iommu->cap))
		iommu->flush.flush_iotlb(iommu, did, 0, 0,
1180
						DMA_TLB_DSI_FLUSH);
1181 1182 1183
	else
		iommu->flush.flush_iotlb(iommu, did, addr, mask,
						DMA_TLB_PSI_FLUSH);
1184 1185

	/*
1186 1187
	 * In caching mode, changes of pages from non-present to present require
	 * flush. However, device IOTLB doesn't need to be flushed in this case.
1188
	 */
1189
	if (!cap_caching_mode(iommu->cap) || !map)
Y
Yu Zhao 已提交
1190
		iommu_flush_dev_iotlb(iommu->domains[did], addr, mask);
1191 1192
}

M
mark gross 已提交
1193 1194 1195 1196 1197
static void iommu_disable_protect_mem_regions(struct intel_iommu *iommu)
{
	u32 pmen;
	unsigned long flags;

1198
	raw_spin_lock_irqsave(&iommu->register_lock, flags);
M
mark gross 已提交
1199 1200 1201 1202 1203 1204 1205 1206
	pmen = readl(iommu->reg + DMAR_PMEN_REG);
	pmen &= ~DMA_PMEN_EPM;
	writel(pmen, iommu->reg + DMAR_PMEN_REG);

	/* wait for the protected region status bit to clear */
	IOMMU_WAIT_OP(iommu, DMAR_PMEN_REG,
		readl, !(pmen & DMA_PMEN_PRS), pmen);

1207
	raw_spin_unlock_irqrestore(&iommu->register_lock, flags);
M
mark gross 已提交
1208 1209
}

1210 1211 1212 1213 1214
static int iommu_enable_translation(struct intel_iommu *iommu)
{
	u32 sts;
	unsigned long flags;

1215
	raw_spin_lock_irqsave(&iommu->register_lock, flags);
1216 1217
	iommu->gcmd |= DMA_GCMD_TE;
	writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG);
1218 1219 1220

	/* Make sure hardware complete it */
	IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
1221
		      readl, (sts & DMA_GSTS_TES), sts);
1222

1223
	raw_spin_unlock_irqrestore(&iommu->register_lock, flags);
1224 1225 1226 1227 1228 1229 1230 1231
	return 0;
}

static int iommu_disable_translation(struct intel_iommu *iommu)
{
	u32 sts;
	unsigned long flag;

1232
	raw_spin_lock_irqsave(&iommu->register_lock, flag);
1233 1234 1235 1236 1237
	iommu->gcmd &= ~DMA_GCMD_TE;
	writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG);

	/* Make sure hardware complete it */
	IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
1238
		      readl, (!(sts & DMA_GSTS_TES)), sts);
1239

1240
	raw_spin_unlock_irqrestore(&iommu->register_lock, flag);
1241 1242 1243
	return 0;
}

1244

1245 1246 1247 1248 1249 1250
static int iommu_init_domains(struct intel_iommu *iommu)
{
	unsigned long ndomains;
	unsigned long nlongs;

	ndomains = cap_ndoms(iommu->cap);
M
Masanari Iida 已提交
1251
	pr_debug("IOMMU %d: Number of Domains supported <%ld>\n", iommu->seq_id,
Y
Yinghai Lu 已提交
1252
			ndomains);
1253 1254
	nlongs = BITS_TO_LONGS(ndomains);

1255 1256
	spin_lock_init(&iommu->lock);

1257 1258 1259 1260 1261 1262 1263 1264 1265 1266 1267 1268 1269 1270 1271 1272 1273 1274 1275 1276 1277 1278 1279 1280 1281 1282
	/* TBD: there might be 64K domains,
	 * consider other allocation for future chip
	 */
	iommu->domain_ids = kcalloc(nlongs, sizeof(unsigned long), GFP_KERNEL);
	if (!iommu->domain_ids) {
		printk(KERN_ERR "Allocating domain id array failed\n");
		return -ENOMEM;
	}
	iommu->domains = kcalloc(ndomains, sizeof(struct dmar_domain *),
			GFP_KERNEL);
	if (!iommu->domains) {
		printk(KERN_ERR "Allocating domain array failed\n");
		return -ENOMEM;
	}

	/*
	 * if Caching mode is set, then invalid translations are tagged
	 * with domainid 0. Hence we need to pre-allocate it.
	 */
	if (cap_caching_mode(iommu->cap))
		set_bit(0, iommu->domain_ids);
	return 0;
}


static void domain_exit(struct dmar_domain *domain);
1283
static void vm_domain_exit(struct dmar_domain *domain);
1284 1285

void free_dmar_iommu(struct intel_iommu *iommu)
1286 1287 1288
{
	struct dmar_domain *domain;
	int i;
1289
	unsigned long flags;
1290

1291
	if ((iommu->domains) && (iommu->domain_ids)) {
1292
		for_each_set_bit(i, iommu->domain_ids, cap_ndoms(iommu->cap)) {
1293 1294 1295 1296 1297 1298 1299 1300 1301 1302 1303
			domain = iommu->domains[i];
			clear_bit(i, iommu->domain_ids);

			spin_lock_irqsave(&domain->iommu_lock, flags);
			if (--domain->iommu_count == 0) {
				if (domain->flags & DOMAIN_FLAG_VIRTUAL_MACHINE)
					vm_domain_exit(domain);
				else
					domain_exit(domain);
			}
			spin_unlock_irqrestore(&domain->iommu_lock, flags);
1304
		}
1305 1306 1307 1308 1309 1310
	}

	if (iommu->gcmd & DMA_GCMD_TE)
		iommu_disable_translation(iommu);

	if (iommu->irq) {
1311
		irq_set_handler_data(iommu->irq, NULL);
1312 1313 1314 1315 1316 1317 1318 1319
		/* This will mask the irq */
		free_irq(iommu->irq, iommu);
		destroy_irq(iommu->irq);
	}

	kfree(iommu->domains);
	kfree(iommu->domain_ids);

W
Weidong Han 已提交
1320 1321 1322 1323 1324 1325 1326 1327 1328 1329 1330
	g_iommus[iommu->seq_id] = NULL;

	/* if all iommus are freed, free g_iommus */
	for (i = 0; i < g_num_of_iommus; i++) {
		if (g_iommus[i])
			break;
	}

	if (i == g_num_of_iommus)
		kfree(g_iommus);

1331 1332 1333 1334
	/* free context mapping */
	free_context_table(iommu);
}

1335
static struct dmar_domain *alloc_domain(void)
1336 1337 1338 1339 1340 1341 1342
{
	struct dmar_domain *domain;

	domain = alloc_domain_mem();
	if (!domain)
		return NULL;

1343
	domain->nid = -1;
1344
	memset(domain->iommu_bmp, 0, sizeof(domain->iommu_bmp));
1345 1346 1347 1348 1349 1350 1351 1352 1353 1354 1355 1356
	domain->flags = 0;

	return domain;
}

static int iommu_attach_domain(struct dmar_domain *domain,
			       struct intel_iommu *iommu)
{
	int num;
	unsigned long ndomains;
	unsigned long flags;

1357 1358 1359
	ndomains = cap_ndoms(iommu->cap);

	spin_lock_irqsave(&iommu->lock, flags);
1360

1361 1362 1363 1364
	num = find_first_zero_bit(iommu->domain_ids, ndomains);
	if (num >= ndomains) {
		spin_unlock_irqrestore(&iommu->lock, flags);
		printk(KERN_ERR "IOMMU: no free domain ids\n");
1365
		return -ENOMEM;
1366 1367 1368
	}

	domain->id = num;
1369
	set_bit(num, iommu->domain_ids);
1370
	set_bit(iommu->seq_id, domain->iommu_bmp);
1371 1372 1373
	iommu->domains[num] = domain;
	spin_unlock_irqrestore(&iommu->lock, flags);

1374
	return 0;
1375 1376
}

1377 1378
static void iommu_detach_domain(struct dmar_domain *domain,
				struct intel_iommu *iommu)
1379 1380
{
	unsigned long flags;
1381 1382
	int num, ndomains;
	int found = 0;
1383

1384
	spin_lock_irqsave(&iommu->lock, flags);
1385
	ndomains = cap_ndoms(iommu->cap);
1386
	for_each_set_bit(num, iommu->domain_ids, ndomains) {
1387 1388 1389 1390 1391 1392 1393 1394
		if (iommu->domains[num] == domain) {
			found = 1;
			break;
		}
	}

	if (found) {
		clear_bit(num, iommu->domain_ids);
1395
		clear_bit(iommu->seq_id, domain->iommu_bmp);
1396 1397
		iommu->domains[num] = NULL;
	}
1398
	spin_unlock_irqrestore(&iommu->lock, flags);
1399 1400 1401
}

static struct iova_domain reserved_iova_list;
M
Mark Gross 已提交
1402
static struct lock_class_key reserved_rbtree_key;
1403

1404
static int dmar_init_reserved_ranges(void)
1405 1406 1407 1408 1409
{
	struct pci_dev *pdev = NULL;
	struct iova *iova;
	int i;

D
David Miller 已提交
1410
	init_iova_domain(&reserved_iova_list, DMA_32BIT_PFN);
1411

M
Mark Gross 已提交
1412 1413 1414
	lockdep_set_class(&reserved_iova_list.iova_rbtree_lock,
		&reserved_rbtree_key);

1415 1416 1417
	/* IOAPIC ranges shouldn't be accessed by DMA */
	iova = reserve_iova(&reserved_iova_list, IOVA_PFN(IOAPIC_RANGE_START),
		IOVA_PFN(IOAPIC_RANGE_END));
1418
	if (!iova) {
1419
		printk(KERN_ERR "Reserve IOAPIC range failed\n");
1420 1421
		return -ENODEV;
	}
1422 1423 1424 1425 1426 1427 1428 1429 1430

	/* Reserve all PCI MMIO to avoid peer-to-peer access */
	for_each_pci_dev(pdev) {
		struct resource *r;

		for (i = 0; i < PCI_NUM_RESOURCES; i++) {
			r = &pdev->resource[i];
			if (!r->flags || !(r->flags & IORESOURCE_MEM))
				continue;
1431 1432 1433
			iova = reserve_iova(&reserved_iova_list,
					    IOVA_PFN(r->start),
					    IOVA_PFN(r->end));
1434
			if (!iova) {
1435
				printk(KERN_ERR "Reserve iova failed\n");
1436 1437
				return -ENODEV;
			}
1438 1439
		}
	}
1440
	return 0;
1441 1442 1443 1444 1445 1446 1447 1448 1449 1450 1451 1452 1453 1454 1455 1456 1457 1458 1459 1460 1461 1462 1463 1464 1465 1466 1467
}

static void domain_reserve_special_ranges(struct dmar_domain *domain)
{
	copy_reserved_iova(&reserved_iova_list, &domain->iovad);
}

static inline int guestwidth_to_adjustwidth(int gaw)
{
	int agaw;
	int r = (gaw - 12) % 9;

	if (r == 0)
		agaw = gaw;
	else
		agaw = gaw + 9 - r;
	if (agaw > 64)
		agaw = 64;
	return agaw;
}

static int domain_init(struct dmar_domain *domain, int guest_width)
{
	struct intel_iommu *iommu;
	int adjust_width, agaw;
	unsigned long sagaw;

D
David Miller 已提交
1468
	init_iova_domain(&domain->iovad, DMA_32BIT_PFN);
1469
	spin_lock_init(&domain->iommu_lock);
1470 1471 1472 1473

	domain_reserve_special_ranges(domain);

	/* calculate AGAW */
1474
	iommu = domain_get_iommu(domain);
1475 1476 1477 1478 1479 1480 1481 1482 1483 1484 1485 1486 1487 1488 1489 1490
	if (guest_width > cap_mgaw(iommu->cap))
		guest_width = cap_mgaw(iommu->cap);
	domain->gaw = guest_width;
	adjust_width = guestwidth_to_adjustwidth(guest_width);
	agaw = width_to_agaw(adjust_width);
	sagaw = cap_sagaw(iommu->cap);
	if (!test_bit(agaw, &sagaw)) {
		/* hardware doesn't support it, choose a bigger one */
		pr_debug("IOMMU: hardware doesn't support agaw %d\n", agaw);
		agaw = find_next_bit(&sagaw, 5, agaw);
		if (agaw >= 5)
			return -ENODEV;
	}
	domain->agaw = agaw;
	INIT_LIST_HEAD(&domain->devices);

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Weidong Han 已提交
1491 1492 1493 1494 1495
	if (ecap_coherent(iommu->ecap))
		domain->iommu_coherency = 1;
	else
		domain->iommu_coherency = 0;

1496 1497 1498 1499 1500
	if (ecap_sc_support(iommu->ecap))
		domain->iommu_snooping = 1;
	else
		domain->iommu_snooping = 0;

1501
	domain->iommu_superpage = fls(cap_super_page_val(iommu->cap));
1502
	domain->iommu_count = 1;
1503
	domain->nid = iommu->node;
1504

1505
	/* always allocate the top pgd */
1506
	domain->pgd = (struct dma_pte *)alloc_pgtable_page(domain->nid);
1507 1508
	if (!domain->pgd)
		return -ENOMEM;
F
Fenghua Yu 已提交
1509
	__iommu_flush_cache(iommu, domain->pgd, PAGE_SIZE);
1510 1511 1512 1513 1514
	return 0;
}

static void domain_exit(struct dmar_domain *domain)
{
1515 1516
	struct dmar_drhd_unit *drhd;
	struct intel_iommu *iommu;
1517 1518 1519 1520 1521

	/* Domain 0 is reserved, so dont process it */
	if (!domain)
		return;

1522 1523 1524 1525
	/* Flush any lazy unmaps that may reference this domain */
	if (!intel_iommu_strict)
		flush_unmaps_timeout(0);

1526 1527 1528 1529 1530
	domain_remove_dev_info(domain);
	/* destroy iovas */
	put_iova_domain(&domain->iovad);

	/* clear ptes */
1531
	dma_pte_clear_range(domain, 0, DOMAIN_MAX_PFN(domain->gaw));
1532 1533

	/* free page tables */
1534
	dma_pte_free_pagetable(domain, 0, DOMAIN_MAX_PFN(domain->gaw));
1535

1536
	for_each_active_iommu(iommu, drhd)
1537
		if (test_bit(iommu->seq_id, domain->iommu_bmp))
1538 1539
			iommu_detach_domain(domain, iommu);

1540 1541 1542
	free_domain_mem(domain);
}

F
Fenghua Yu 已提交
1543 1544
static int domain_context_mapping_one(struct dmar_domain *domain, int segment,
				 u8 bus, u8 devfn, int translation)
1545 1546 1547
{
	struct context_entry *context;
	unsigned long flags;
W
Weidong Han 已提交
1548
	struct intel_iommu *iommu;
1549 1550 1551 1552 1553
	struct dma_pte *pgd;
	unsigned long num;
	unsigned long ndomains;
	int id;
	int agaw;
Y
Yu Zhao 已提交
1554
	struct device_domain_info *info = NULL;
1555 1556 1557

	pr_debug("Set context mapping for %02x:%02x.%d\n",
		bus, PCI_SLOT(devfn), PCI_FUNC(devfn));
F
Fenghua Yu 已提交
1558

1559
	BUG_ON(!domain->pgd);
F
Fenghua Yu 已提交
1560 1561
	BUG_ON(translation != CONTEXT_TT_PASS_THROUGH &&
	       translation != CONTEXT_TT_MULTI_LEVEL);
W
Weidong Han 已提交
1562

1563
	iommu = device_to_iommu(segment, bus, devfn);
W
Weidong Han 已提交
1564 1565 1566
	if (!iommu)
		return -ENODEV;

1567 1568 1569 1570
	context = device_to_context_entry(iommu, bus, devfn);
	if (!context)
		return -ENOMEM;
	spin_lock_irqsave(&iommu->lock, flags);
1571
	if (context_present(context)) {
1572 1573 1574 1575
		spin_unlock_irqrestore(&iommu->lock, flags);
		return 0;
	}

1576 1577 1578
	id = domain->id;
	pgd = domain->pgd;

1579 1580
	if (domain->flags & DOMAIN_FLAG_VIRTUAL_MACHINE ||
	    domain->flags & DOMAIN_FLAG_STATIC_IDENTITY) {
1581 1582 1583 1584
		int found = 0;

		/* find an available domain id for this device in iommu */
		ndomains = cap_ndoms(iommu->cap);
1585
		for_each_set_bit(num, iommu->domain_ids, ndomains) {
1586 1587 1588 1589 1590 1591 1592 1593 1594 1595 1596 1597 1598 1599 1600 1601 1602 1603 1604 1605 1606 1607
			if (iommu->domains[num] == domain) {
				id = num;
				found = 1;
				break;
			}
		}

		if (found == 0) {
			num = find_first_zero_bit(iommu->domain_ids, ndomains);
			if (num >= ndomains) {
				spin_unlock_irqrestore(&iommu->lock, flags);
				printk(KERN_ERR "IOMMU: no free domain ids\n");
				return -EFAULT;
			}

			set_bit(num, iommu->domain_ids);
			iommu->domains[num] = domain;
			id = num;
		}

		/* Skip top levels of page tables for
		 * iommu which has less agaw than default.
1608
		 * Unnecessary for PT mode.
1609
		 */
1610 1611 1612 1613 1614 1615 1616
		if (translation != CONTEXT_TT_PASS_THROUGH) {
			for (agaw = domain->agaw; agaw != iommu->agaw; agaw--) {
				pgd = phys_to_virt(dma_pte_addr(pgd));
				if (!dma_pte_present(pgd)) {
					spin_unlock_irqrestore(&iommu->lock, flags);
					return -ENOMEM;
				}
1617 1618 1619 1620 1621
			}
		}
	}

	context_set_domain_id(context, id);
F
Fenghua Yu 已提交
1622

Y
Yu Zhao 已提交
1623 1624 1625 1626 1627
	if (translation != CONTEXT_TT_PASS_THROUGH) {
		info = iommu_support_dev_iotlb(domain, segment, bus, devfn);
		translation = info ? CONTEXT_TT_DEV_IOTLB :
				     CONTEXT_TT_MULTI_LEVEL;
	}
F
Fenghua Yu 已提交
1628 1629 1630 1631
	/*
	 * In pass through mode, AW must be programmed to indicate the largest
	 * AGAW value supported by hardware. And ASR is ignored by hardware.
	 */
Y
Yu Zhao 已提交
1632
	if (unlikely(translation == CONTEXT_TT_PASS_THROUGH))
F
Fenghua Yu 已提交
1633
		context_set_address_width(context, iommu->msagaw);
Y
Yu Zhao 已提交
1634 1635 1636 1637
	else {
		context_set_address_root(context, virt_to_phys(pgd));
		context_set_address_width(context, iommu->agaw);
	}
F
Fenghua Yu 已提交
1638 1639

	context_set_translation_type(context, translation);
1640 1641
	context_set_fault_enable(context);
	context_set_present(context);
W
Weidong Han 已提交
1642
	domain_flush_cache(domain, context, sizeof(*context));
1643

1644 1645 1646 1647 1648 1649 1650 1651 1652 1653 1654
	/*
	 * It's a non-present to present mapping. If hardware doesn't cache
	 * non-present entry we only need to flush the write-buffer. If the
	 * _does_ cache non-present entries, then it does so in the special
	 * domain #0, which we have to flush:
	 */
	if (cap_caching_mode(iommu->cap)) {
		iommu->flush.flush_context(iommu, 0,
					   (((u16)bus) << 8) | devfn,
					   DMA_CCMD_MASK_NOBIT,
					   DMA_CCMD_DEVICE_INVL);
1655
		iommu->flush.flush_iotlb(iommu, domain->id, 0, 0, DMA_TLB_DSI_FLUSH);
1656
	} else {
1657
		iommu_flush_write_buffer(iommu);
1658
	}
Y
Yu Zhao 已提交
1659
	iommu_enable_dev_iotlb(info);
1660
	spin_unlock_irqrestore(&iommu->lock, flags);
1661 1662

	spin_lock_irqsave(&domain->iommu_lock, flags);
1663
	if (!test_and_set_bit(iommu->seq_id, domain->iommu_bmp)) {
1664
		domain->iommu_count++;
1665 1666
		if (domain->iommu_count == 1)
			domain->nid = iommu->node;
1667
		domain_update_iommu_cap(domain);
1668 1669
	}
	spin_unlock_irqrestore(&domain->iommu_lock, flags);
1670 1671 1672 1673
	return 0;
}

static int
F
Fenghua Yu 已提交
1674 1675
domain_context_mapping(struct dmar_domain *domain, struct pci_dev *pdev,
			int translation)
1676 1677 1678 1679
{
	int ret;
	struct pci_dev *tmp, *parent;

1680
	ret = domain_context_mapping_one(domain, pci_domain_nr(pdev->bus),
F
Fenghua Yu 已提交
1681 1682
					 pdev->bus->number, pdev->devfn,
					 translation);
1683 1684 1685 1686 1687 1688 1689 1690 1691 1692
	if (ret)
		return ret;

	/* dependent device mapping */
	tmp = pci_find_upstream_pcie_bridge(pdev);
	if (!tmp)
		return 0;
	/* Secondary interface's bus number and devfn 0 */
	parent = pdev->bus->self;
	while (parent != tmp) {
1693 1694 1695
		ret = domain_context_mapping_one(domain,
						 pci_domain_nr(parent->bus),
						 parent->bus->number,
F
Fenghua Yu 已提交
1696
						 parent->devfn, translation);
1697 1698 1699 1700
		if (ret)
			return ret;
		parent = parent->bus->self;
	}
1701
	if (pci_is_pcie(tmp)) /* this is a PCIe-to-PCI bridge */
1702
		return domain_context_mapping_one(domain,
1703
					pci_domain_nr(tmp->subordinate),
F
Fenghua Yu 已提交
1704 1705
					tmp->subordinate->number, 0,
					translation);
1706 1707
	else /* this is a legacy PCI bridge */
		return domain_context_mapping_one(domain,
1708 1709
						  pci_domain_nr(tmp->bus),
						  tmp->bus->number,
F
Fenghua Yu 已提交
1710 1711
						  tmp->devfn,
						  translation);
1712 1713
}

W
Weidong Han 已提交
1714
static int domain_context_mapped(struct pci_dev *pdev)
1715 1716 1717
{
	int ret;
	struct pci_dev *tmp, *parent;
W
Weidong Han 已提交
1718 1719
	struct intel_iommu *iommu;

1720 1721
	iommu = device_to_iommu(pci_domain_nr(pdev->bus), pdev->bus->number,
				pdev->devfn);
W
Weidong Han 已提交
1722 1723
	if (!iommu)
		return -ENODEV;
1724

1725
	ret = device_context_mapped(iommu, pdev->bus->number, pdev->devfn);
1726 1727 1728 1729 1730 1731 1732 1733 1734
	if (!ret)
		return ret;
	/* dependent device mapping */
	tmp = pci_find_upstream_pcie_bridge(pdev);
	if (!tmp)
		return ret;
	/* Secondary interface's bus number and devfn 0 */
	parent = pdev->bus->self;
	while (parent != tmp) {
1735
		ret = device_context_mapped(iommu, parent->bus->number,
1736
					    parent->devfn);
1737 1738 1739 1740
		if (!ret)
			return ret;
		parent = parent->bus->self;
	}
1741
	if (pci_is_pcie(tmp))
1742 1743
		return device_context_mapped(iommu, tmp->subordinate->number,
					     0);
1744
	else
1745 1746
		return device_context_mapped(iommu, tmp->bus->number,
					     tmp->devfn);
1747 1748
}

1749 1750 1751 1752 1753 1754 1755 1756
/* Returns a number of VTD pages, but aligned to MM page size */
static inline unsigned long aligned_nrpages(unsigned long host_addr,
					    size_t size)
{
	host_addr &= ~PAGE_MASK;
	return PAGE_ALIGN(host_addr + size) >> VTD_PAGE_SHIFT;
}

1757 1758 1759 1760 1761 1762 1763 1764 1765 1766 1767 1768 1769 1770 1771 1772 1773 1774 1775 1776 1777 1778 1779 1780 1781 1782 1783 1784
/* Return largest possible superpage level for a given mapping */
static inline int hardware_largepage_caps(struct dmar_domain *domain,
					  unsigned long iov_pfn,
					  unsigned long phy_pfn,
					  unsigned long pages)
{
	int support, level = 1;
	unsigned long pfnmerge;

	support = domain->iommu_superpage;

	/* To use a large page, the virtual *and* physical addresses
	   must be aligned to 2MiB/1GiB/etc. Lower bits set in either
	   of them will mean we have to use smaller pages. So just
	   merge them and check both at once. */
	pfnmerge = iov_pfn | phy_pfn;

	while (support && !(pfnmerge & ~VTD_STRIDE_MASK)) {
		pages >>= VTD_STRIDE_SHIFT;
		if (!pages)
			break;
		pfnmerge >>= VTD_STRIDE_SHIFT;
		level++;
		support--;
	}
	return level;
}

1785 1786 1787
static int __domain_mapping(struct dmar_domain *domain, unsigned long iov_pfn,
			    struct scatterlist *sg, unsigned long phys_pfn,
			    unsigned long nr_pages, int prot)
1788 1789
{
	struct dma_pte *first_pte = NULL, *pte = NULL;
1790
	phys_addr_t uninitialized_var(pteval);
1791
	int addr_width = agaw_to_width(domain->agaw) - VTD_PAGE_SHIFT;
1792
	unsigned long sg_res;
1793 1794
	unsigned int largepage_lvl = 0;
	unsigned long lvl_pages = 0;
1795 1796 1797 1798 1799 1800 1801 1802

	BUG_ON(addr_width < BITS_PER_LONG && (iov_pfn + nr_pages - 1) >> addr_width);

	if ((prot & (DMA_PTE_READ|DMA_PTE_WRITE)) == 0)
		return -EINVAL;

	prot &= DMA_PTE_READ | DMA_PTE_WRITE | DMA_PTE_SNP;

1803 1804 1805 1806 1807 1808 1809
	if (sg)
		sg_res = 0;
	else {
		sg_res = nr_pages + 1;
		pteval = ((phys_addr_t)phys_pfn << VTD_PAGE_SHIFT) | prot;
	}

1810
	while (nr_pages > 0) {
1811 1812
		uint64_t tmp;

1813
		if (!sg_res) {
1814
			sg_res = aligned_nrpages(sg->offset, sg->length);
1815 1816 1817
			sg->dma_address = ((dma_addr_t)iov_pfn << VTD_PAGE_SHIFT) + sg->offset;
			sg->dma_length = sg->length;
			pteval = page_to_phys(sg_page(sg)) | prot;
1818
			phys_pfn = pteval >> VTD_PAGE_SHIFT;
1819
		}
1820

1821
		if (!pte) {
1822 1823 1824
			largepage_lvl = hardware_largepage_caps(domain, iov_pfn, phys_pfn, sg_res);

			first_pte = pte = pfn_to_dma_pte(domain, iov_pfn, largepage_lvl);
1825 1826
			if (!pte)
				return -ENOMEM;
1827 1828 1829 1830 1831 1832
			/* It is large page*/
			if (largepage_lvl > 1)
				pteval |= DMA_PTE_LARGE_PAGE;
			else
				pteval &= ~(uint64_t)DMA_PTE_LARGE_PAGE;

1833 1834 1835 1836
		}
		/* We don't need lock here, nobody else
		 * touches the iova range
		 */
1837
		tmp = cmpxchg64_local(&pte->val, 0ULL, pteval);
1838
		if (tmp) {
1839
			static int dumps = 5;
1840 1841
			printk(KERN_CRIT "ERROR: DMA PTE for vPFN 0x%lx already set (to %llx not %llx)\n",
			       iov_pfn, tmp, (unsigned long long)pteval);
1842 1843 1844 1845 1846 1847
			if (dumps) {
				dumps--;
				debug_dma_dump_mappings(NULL);
			}
			WARN_ON(1);
		}
1848 1849 1850 1851 1852 1853 1854 1855 1856 1857 1858 1859 1860 1861 1862 1863 1864 1865 1866 1867 1868 1869 1870

		lvl_pages = lvl_to_nr_pages(largepage_lvl);

		BUG_ON(nr_pages < lvl_pages);
		BUG_ON(sg_res < lvl_pages);

		nr_pages -= lvl_pages;
		iov_pfn += lvl_pages;
		phys_pfn += lvl_pages;
		pteval += lvl_pages * VTD_PAGE_SIZE;
		sg_res -= lvl_pages;

		/* If the next PTE would be the first in a new page, then we
		   need to flush the cache on the entries we've just written.
		   And then we'll need to recalculate 'pte', so clear it and
		   let it get set again in the if (!pte) block above.

		   If we're done (!nr_pages) we need to flush the cache too.

		   Also if we've been setting superpages, we may need to
		   recalculate 'pte' and switch back to smaller pages for the
		   end of the mapping, if the trailing size is not enough to
		   use another superpage (i.e. sg_res < lvl_pages). */
1871
		pte++;
1872 1873
		if (!nr_pages || first_pte_in_page(pte) ||
		    (largepage_lvl > 1 && sg_res < lvl_pages)) {
1874 1875 1876 1877
			domain_flush_cache(domain, first_pte,
					   (void *)pte - (void *)first_pte);
			pte = NULL;
		}
1878 1879

		if (!sg_res && nr_pages)
1880 1881 1882 1883 1884
			sg = sg_next(sg);
	}
	return 0;
}

1885 1886 1887
static inline int domain_sg_mapping(struct dmar_domain *domain, unsigned long iov_pfn,
				    struct scatterlist *sg, unsigned long nr_pages,
				    int prot)
1888
{
1889 1890
	return __domain_mapping(domain, iov_pfn, sg, 0, nr_pages, prot);
}
1891

1892 1893 1894 1895 1896
static inline int domain_pfn_mapping(struct dmar_domain *domain, unsigned long iov_pfn,
				     unsigned long phys_pfn, unsigned long nr_pages,
				     int prot)
{
	return __domain_mapping(domain, iov_pfn, NULL, phys_pfn, nr_pages, prot);
1897 1898
}

1899
static void iommu_detach_dev(struct intel_iommu *iommu, u8 bus, u8 devfn)
1900
{
1901 1902
	if (!iommu)
		return;
1903 1904 1905

	clear_context_table(iommu, bus, devfn);
	iommu->flush.flush_context(iommu, 0, 0, 0,
1906
					   DMA_CCMD_GLOBAL_INVL);
1907
	iommu->flush.flush_iotlb(iommu, 0, 0, 0, DMA_TLB_GLOBAL_FLUSH);
1908 1909
}

1910 1911 1912 1913 1914 1915 1916 1917 1918
static inline void unlink_domain_info(struct device_domain_info *info)
{
	assert_spin_locked(&device_domain_lock);
	list_del(&info->link);
	list_del(&info->global);
	if (info->dev)
		info->dev->dev.archdata.iommu = NULL;
}

1919 1920 1921 1922
static void domain_remove_dev_info(struct dmar_domain *domain)
{
	struct device_domain_info *info;
	unsigned long flags;
1923
	struct intel_iommu *iommu;
1924 1925 1926 1927 1928

	spin_lock_irqsave(&device_domain_lock, flags);
	while (!list_empty(&domain->devices)) {
		info = list_entry(domain->devices.next,
			struct device_domain_info, link);
1929
		unlink_domain_info(info);
1930 1931
		spin_unlock_irqrestore(&device_domain_lock, flags);

Y
Yu Zhao 已提交
1932
		iommu_disable_dev_iotlb(info);
1933
		iommu = device_to_iommu(info->segment, info->bus, info->devfn);
1934
		iommu_detach_dev(iommu, info->bus, info->devfn);
1935 1936 1937 1938 1939 1940 1941 1942 1943
		free_devinfo_mem(info);

		spin_lock_irqsave(&device_domain_lock, flags);
	}
	spin_unlock_irqrestore(&device_domain_lock, flags);
}

/*
 * find_domain
1944
 * Note: we use struct pci_dev->dev.archdata.iommu stores the info
1945
 */
K
Kay, Allen M 已提交
1946
static struct dmar_domain *
1947 1948 1949 1950 1951
find_domain(struct pci_dev *pdev)
{
	struct device_domain_info *info;

	/* No lock here, assumes no domain exit in normal case */
1952
	info = pdev->dev.archdata.iommu;
1953 1954 1955 1956 1957 1958 1959 1960 1961 1962 1963 1964 1965 1966 1967
	if (info)
		return info->domain;
	return NULL;
}

/* domain is initialized */
static struct dmar_domain *get_domain_for_dev(struct pci_dev *pdev, int gaw)
{
	struct dmar_domain *domain, *found = NULL;
	struct intel_iommu *iommu;
	struct dmar_drhd_unit *drhd;
	struct device_domain_info *info, *tmp;
	struct pci_dev *dev_tmp;
	unsigned long flags;
	int bus = 0, devfn = 0;
1968
	int segment;
1969
	int ret;
1970 1971 1972 1973 1974

	domain = find_domain(pdev);
	if (domain)
		return domain;

1975 1976
	segment = pci_domain_nr(pdev->bus);

1977 1978
	dev_tmp = pci_find_upstream_pcie_bridge(pdev);
	if (dev_tmp) {
1979
		if (pci_is_pcie(dev_tmp)) {
1980 1981 1982 1983 1984 1985 1986 1987
			bus = dev_tmp->subordinate->number;
			devfn = 0;
		} else {
			bus = dev_tmp->bus->number;
			devfn = dev_tmp->devfn;
		}
		spin_lock_irqsave(&device_domain_lock, flags);
		list_for_each_entry(info, &device_domain_list, global) {
1988 1989
			if (info->segment == segment &&
			    info->bus == bus && info->devfn == devfn) {
1990 1991 1992 1993 1994 1995 1996 1997 1998 1999 2000 2001
				found = info->domain;
				break;
			}
		}
		spin_unlock_irqrestore(&device_domain_lock, flags);
		/* pcie-pci bridge already has a domain, uses it */
		if (found) {
			domain = found;
			goto found_domain;
		}
	}

2002 2003 2004 2005
	domain = alloc_domain();
	if (!domain)
		goto error;

2006 2007 2008 2009 2010
	/* Allocate new domain for the device */
	drhd = dmar_find_matched_drhd_unit(pdev);
	if (!drhd) {
		printk(KERN_ERR "IOMMU: can't find DMAR for device %s\n",
			pci_name(pdev));
2011
		free_domain_mem(domain);
2012 2013 2014 2015
		return NULL;
	}
	iommu = drhd->iommu;

2016 2017
	ret = iommu_attach_domain(domain, iommu);
	if (ret) {
2018
		free_domain_mem(domain);
2019
		goto error;
2020
	}
2021 2022 2023 2024 2025 2026 2027 2028 2029 2030 2031 2032 2033

	if (domain_init(domain, gaw)) {
		domain_exit(domain);
		goto error;
	}

	/* register pcie-to-pci device */
	if (dev_tmp) {
		info = alloc_devinfo_mem();
		if (!info) {
			domain_exit(domain);
			goto error;
		}
2034
		info->segment = segment;
2035 2036 2037 2038 2039
		info->bus = bus;
		info->devfn = devfn;
		info->dev = NULL;
		info->domain = domain;
		/* This domain is shared by devices under p2p bridge */
W
Weidong Han 已提交
2040
		domain->flags |= DOMAIN_FLAG_P2P_MULTIPLE_DEVICES;
2041 2042 2043 2044 2045

		/* pcie-to-pci bridge already has a domain, uses it */
		found = NULL;
		spin_lock_irqsave(&device_domain_lock, flags);
		list_for_each_entry(tmp, &device_domain_list, global) {
2046 2047
			if (tmp->segment == segment &&
			    tmp->bus == bus && tmp->devfn == devfn) {
2048 2049 2050 2051 2052
				found = tmp->domain;
				break;
			}
		}
		if (found) {
2053
			spin_unlock_irqrestore(&device_domain_lock, flags);
2054 2055 2056 2057 2058 2059
			free_devinfo_mem(info);
			domain_exit(domain);
			domain = found;
		} else {
			list_add(&info->link, &domain->devices);
			list_add(&info->global, &device_domain_list);
2060
			spin_unlock_irqrestore(&device_domain_lock, flags);
2061 2062 2063 2064 2065 2066 2067
		}
	}

found_domain:
	info = alloc_devinfo_mem();
	if (!info)
		goto error;
2068
	info->segment = segment;
2069 2070 2071 2072 2073 2074 2075 2076 2077 2078 2079 2080 2081 2082 2083 2084 2085 2086
	info->bus = pdev->bus->number;
	info->devfn = pdev->devfn;
	info->dev = pdev;
	info->domain = domain;
	spin_lock_irqsave(&device_domain_lock, flags);
	/* somebody is fast */
	found = find_domain(pdev);
	if (found != NULL) {
		spin_unlock_irqrestore(&device_domain_lock, flags);
		if (found != domain) {
			domain_exit(domain);
			domain = found;
		}
		free_devinfo_mem(info);
		return domain;
	}
	list_add(&info->link, &domain->devices);
	list_add(&info->global, &device_domain_list);
2087
	pdev->dev.archdata.iommu = info;
2088 2089 2090 2091 2092 2093 2094
	spin_unlock_irqrestore(&device_domain_lock, flags);
	return domain;
error:
	/* recheck it here, maybe others set it */
	return find_domain(pdev);
}

2095
static int iommu_identity_mapping;
2096 2097 2098
#define IDENTMAP_ALL		1
#define IDENTMAP_GFX		2
#define IDENTMAP_AZALIA		4
2099

2100 2101 2102
static int iommu_domain_identity_map(struct dmar_domain *domain,
				     unsigned long long start,
				     unsigned long long end)
2103
{
2104 2105 2106 2107 2108
	unsigned long first_vpfn = start >> VTD_PAGE_SHIFT;
	unsigned long last_vpfn = end >> VTD_PAGE_SHIFT;

	if (!reserve_iova(&domain->iovad, dma_to_mm_pfn(first_vpfn),
			  dma_to_mm_pfn(last_vpfn))) {
2109
		printk(KERN_ERR "IOMMU: reserve iova failed\n");
2110
		return -ENOMEM;
2111 2112
	}

2113 2114
	pr_debug("Mapping reserved region %llx-%llx for domain %d\n",
		 start, end, domain->id);
2115 2116 2117 2118
	/*
	 * RMRR range might have overlap with physical memory range,
	 * clear it first
	 */
2119
	dma_pte_clear_range(domain, first_vpfn, last_vpfn);
2120

2121 2122
	return domain_pfn_mapping(domain, first_vpfn, first_vpfn,
				  last_vpfn - first_vpfn + 1,
2123
				  DMA_PTE_READ|DMA_PTE_WRITE);
2124 2125 2126 2127 2128 2129 2130 2131 2132
}

static int iommu_prepare_identity_map(struct pci_dev *pdev,
				      unsigned long long start,
				      unsigned long long end)
{
	struct dmar_domain *domain;
	int ret;

2133
	domain = get_domain_for_dev(pdev, DEFAULT_DOMAIN_ADDRESS_WIDTH);
2134 2135 2136
	if (!domain)
		return -ENOMEM;

2137 2138 2139 2140 2141 2142 2143 2144 2145 2146 2147 2148 2149
	/* For _hardware_ passthrough, don't bother. But for software
	   passthrough, we do it anyway -- it may indicate a memory
	   range which is reserved in E820, so which didn't get set
	   up to start with in si_domain */
	if (domain == si_domain && hw_pass_through) {
		printk("Ignoring identity map for HW passthrough device %s [0x%Lx - 0x%Lx]\n",
		       pci_name(pdev), start, end);
		return 0;
	}

	printk(KERN_INFO
	       "IOMMU: Setting identity map for device %s [0x%Lx - 0x%Lx]\n",
	       pci_name(pdev), start, end);
2150
	
2151 2152 2153 2154 2155 2156 2157 2158 2159 2160
	if (end < start) {
		WARN(1, "Your BIOS is broken; RMRR ends before it starts!\n"
			"BIOS vendor: %s; Ver: %s; Product Version: %s\n",
			dmi_get_system_info(DMI_BIOS_VENDOR),
			dmi_get_system_info(DMI_BIOS_VERSION),
		     dmi_get_system_info(DMI_PRODUCT_VERSION));
		ret = -EIO;
		goto error;
	}

2161 2162 2163 2164 2165 2166 2167 2168 2169 2170
	if (end >> agaw_to_width(domain->agaw)) {
		WARN(1, "Your BIOS is broken; RMRR exceeds permitted address width (%d bits)\n"
		     "BIOS vendor: %s; Ver: %s; Product Version: %s\n",
		     agaw_to_width(domain->agaw),
		     dmi_get_system_info(DMI_BIOS_VENDOR),
		     dmi_get_system_info(DMI_BIOS_VERSION),
		     dmi_get_system_info(DMI_PRODUCT_VERSION));
		ret = -EIO;
		goto error;
	}
2171

2172
	ret = iommu_domain_identity_map(domain, start, end);
2173 2174 2175 2176
	if (ret)
		goto error;

	/* context entry init */
F
Fenghua Yu 已提交
2177
	ret = domain_context_mapping(domain, pdev, CONTEXT_TT_MULTI_LEVEL);
2178 2179 2180 2181 2182 2183
	if (ret)
		goto error;

	return 0;

 error:
2184 2185 2186 2187 2188 2189 2190
	domain_exit(domain);
	return ret;
}

static inline int iommu_prepare_rmrr_dev(struct dmar_rmrr_unit *rmrr,
	struct pci_dev *pdev)
{
2191
	if (pdev->dev.archdata.iommu == DUMMY_DEVICE_DOMAIN_INFO)
2192 2193
		return 0;
	return iommu_prepare_identity_map(pdev, rmrr->base_address,
2194
		rmrr->end_address);
2195 2196
}

2197
#ifdef CONFIG_INTEL_IOMMU_FLOPPY_WA
2198 2199 2200 2201 2202 2203 2204 2205 2206
static inline void iommu_prepare_isa(void)
{
	struct pci_dev *pdev;
	int ret;

	pdev = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, NULL);
	if (!pdev)
		return;

2207
	printk(KERN_INFO "IOMMU: Prepare 0-16MiB unity mapping for LPC\n");
2208
	ret = iommu_prepare_identity_map(pdev, 0, 16*1024*1024 - 1);
2209 2210

	if (ret)
2211 2212
		printk(KERN_ERR "IOMMU: Failed to create 0-16MiB identity map; "
		       "floppy might not work\n");
2213 2214 2215 2216 2217 2218 2219

}
#else
static inline void iommu_prepare_isa(void)
{
	return;
}
2220
#endif /* !CONFIG_INTEL_IOMMU_FLPY_WA */
2221

2222
static int md_domain_init(struct dmar_domain *domain, int guest_width);
2223

2224
static int __init si_domain_init(int hw)
2225 2226 2227
{
	struct dmar_drhd_unit *drhd;
	struct intel_iommu *iommu;
2228
	int nid, ret = 0;
2229 2230 2231 2232 2233

	si_domain = alloc_domain();
	if (!si_domain)
		return -EFAULT;

2234
	pr_debug("Identity mapping domain is domain %d\n", si_domain->id);
2235 2236 2237 2238 2239 2240 2241 2242 2243 2244 2245 2246 2247 2248 2249 2250

	for_each_active_iommu(iommu, drhd) {
		ret = iommu_attach_domain(si_domain, iommu);
		if (ret) {
			domain_exit(si_domain);
			return -EFAULT;
		}
	}

	if (md_domain_init(si_domain, DEFAULT_DOMAIN_ADDRESS_WIDTH)) {
		domain_exit(si_domain);
		return -EFAULT;
	}

	si_domain->flags = DOMAIN_FLAG_STATIC_IDENTITY;

2251 2252 2253
	if (hw)
		return 0;

2254
	for_each_online_node(nid) {
2255 2256 2257 2258 2259 2260 2261 2262 2263
		unsigned long start_pfn, end_pfn;
		int i;

		for_each_mem_pfn_range(i, nid, &start_pfn, &end_pfn, NULL) {
			ret = iommu_domain_identity_map(si_domain,
					PFN_PHYS(start_pfn), PFN_PHYS(end_pfn));
			if (ret)
				return ret;
		}
2264 2265
	}

2266 2267 2268 2269 2270 2271 2272 2273 2274 2275 2276 2277
	return 0;
}

static void domain_remove_one_dev_info(struct dmar_domain *domain,
					  struct pci_dev *pdev);
static int identity_mapping(struct pci_dev *pdev)
{
	struct device_domain_info *info;

	if (likely(!iommu_identity_mapping))
		return 0;

2278 2279 2280
	info = pdev->dev.archdata.iommu;
	if (info && info != DUMMY_DEVICE_DOMAIN_INFO)
		return (info->domain == si_domain);
2281 2282 2283 2284 2285

	return 0;
}

static int domain_add_dev_info(struct dmar_domain *domain,
2286 2287
			       struct pci_dev *pdev,
			       int translation)
2288 2289 2290
{
	struct device_domain_info *info;
	unsigned long flags;
2291
	int ret;
2292 2293 2294 2295 2296 2297 2298 2299 2300 2301 2302 2303 2304 2305 2306 2307 2308

	info = alloc_devinfo_mem();
	if (!info)
		return -ENOMEM;

	info->segment = pci_domain_nr(pdev->bus);
	info->bus = pdev->bus->number;
	info->devfn = pdev->devfn;
	info->dev = pdev;
	info->domain = domain;

	spin_lock_irqsave(&device_domain_lock, flags);
	list_add(&info->link, &domain->devices);
	list_add(&info->global, &device_domain_list);
	pdev->dev.archdata.iommu = info;
	spin_unlock_irqrestore(&device_domain_lock, flags);

2309 2310 2311
	ret = domain_context_mapping(domain, pdev, translation);
	if (ret) {
		spin_lock_irqsave(&device_domain_lock, flags);
2312
		unlink_domain_info(info);
2313 2314 2315 2316 2317
		spin_unlock_irqrestore(&device_domain_lock, flags);
		free_devinfo_mem(info);
		return ret;
	}

2318 2319 2320
	return 0;
}

2321 2322
static int iommu_should_identity_map(struct pci_dev *pdev, int startup)
{
2323 2324 2325 2326 2327 2328 2329 2330
	if ((iommu_identity_mapping & IDENTMAP_AZALIA) && IS_AZALIA(pdev))
		return 1;

	if ((iommu_identity_mapping & IDENTMAP_GFX) && IS_GFX_DEVICE(pdev))
		return 1;

	if (!(iommu_identity_mapping & IDENTMAP_ALL))
		return 0;
2331

2332 2333 2334 2335 2336 2337 2338 2339 2340 2341 2342 2343 2344 2345 2346 2347 2348
	/*
	 * We want to start off with all devices in the 1:1 domain, and
	 * take them out later if we find they can't access all of memory.
	 *
	 * However, we can't do this for PCI devices behind bridges,
	 * because all PCI devices behind the same bridge will end up
	 * with the same source-id on their transactions.
	 *
	 * Practically speaking, we can't change things around for these
	 * devices at run-time, because we can't be sure there'll be no
	 * DMA transactions in flight for any of their siblings.
	 * 
	 * So PCI devices (unless they're on the root bus) as well as
	 * their parent PCI-PCI or PCIe-PCI bridges must be left _out_ of
	 * the 1:1 domain, just in _case_ one of their siblings turns out
	 * not to be able to map all of memory.
	 */
2349
	if (!pci_is_pcie(pdev)) {
2350 2351 2352 2353 2354 2355 2356 2357 2358 2359 2360 2361
		if (!pci_is_root_bus(pdev->bus))
			return 0;
		if (pdev->class >> 8 == PCI_CLASS_BRIDGE_PCI)
			return 0;
	} else if (pdev->pcie_type == PCI_EXP_TYPE_PCI_BRIDGE)
		return 0;

	/* 
	 * At boot time, we don't yet know if devices will be 64-bit capable.
	 * Assume that they will -- if they turn out not to be, then we can 
	 * take them out of the 1:1 domain later.
	 */
2362 2363 2364 2365 2366 2367 2368 2369 2370 2371 2372 2373 2374
	if (!startup) {
		/*
		 * If the device's dma_mask is less than the system's memory
		 * size then this is not a candidate for identity mapping.
		 */
		u64 dma_mask = pdev->dma_mask;

		if (pdev->dev.coherent_dma_mask &&
		    pdev->dev.coherent_dma_mask < dma_mask)
			dma_mask = pdev->dev.coherent_dma_mask;

		return dma_mask >= dma_get_required_mask(&pdev->dev);
	}
2375 2376 2377 2378

	return 1;
}

2379
static int __init iommu_prepare_static_identity_mapping(int hw)
2380 2381 2382 2383
{
	struct pci_dev *pdev = NULL;
	int ret;

2384
	ret = si_domain_init(hw);
2385 2386 2387 2388
	if (ret)
		return -EFAULT;

	for_each_pci_dev(pdev) {
2389
		if (iommu_should_identity_map(pdev, 1)) {
2390
			ret = domain_add_dev_info(si_domain, pdev,
2391 2392 2393 2394 2395 2396
					     hw ? CONTEXT_TT_PASS_THROUGH :
						  CONTEXT_TT_MULTI_LEVEL);
			if (ret) {
				/* device not associated with an iommu */
				if (ret == -ENODEV)
					continue;
2397
				return ret;
2398 2399 2400
			}
			pr_info("IOMMU: %s identity mapping for device %s\n",
				hw ? "hardware" : "software", pci_name(pdev));
2401
		}
2402 2403 2404 2405 2406
	}

	return 0;
}

2407
static int __init init_dmars(void)
2408 2409 2410 2411 2412
{
	struct dmar_drhd_unit *drhd;
	struct dmar_rmrr_unit *rmrr;
	struct pci_dev *pdev;
	struct intel_iommu *iommu;
2413
	int i, ret;
2414

2415 2416 2417 2418 2419 2420 2421
	/*
	 * for each drhd
	 *    allocate root
	 *    initialize and program root entry to not present
	 * endfor
	 */
	for_each_drhd_unit(drhd) {
M
mark gross 已提交
2422 2423 2424 2425 2426
		/*
		 * lock not needed as this is only incremented in the single
		 * threaded kernel __init code path all other access are read
		 * only
		 */
2427 2428 2429 2430 2431 2432
		if (g_num_of_iommus < IOMMU_UNITS_SUPPORTED) {
			g_num_of_iommus++;
			continue;
		}
		printk_once(KERN_ERR "intel-iommu: exceeded %d IOMMUs\n",
			  IOMMU_UNITS_SUPPORTED);
M
mark gross 已提交
2433 2434
	}

W
Weidong Han 已提交
2435 2436 2437 2438 2439 2440 2441 2442
	g_iommus = kcalloc(g_num_of_iommus, sizeof(struct intel_iommu *),
			GFP_KERNEL);
	if (!g_iommus) {
		printk(KERN_ERR "Allocating global iommu array failed\n");
		ret = -ENOMEM;
		goto error;
	}

2443 2444 2445
	deferred_flush = kzalloc(g_num_of_iommus *
		sizeof(struct deferred_flush_tables), GFP_KERNEL);
	if (!deferred_flush) {
M
mark gross 已提交
2446 2447 2448 2449 2450 2451 2452
		ret = -ENOMEM;
		goto error;
	}

	for_each_drhd_unit(drhd) {
		if (drhd->ignored)
			continue;
2453 2454

		iommu = drhd->iommu;
W
Weidong Han 已提交
2455
		g_iommus[iommu->seq_id] = iommu;
2456

2457 2458 2459 2460
		ret = iommu_init_domains(iommu);
		if (ret)
			goto error;

2461 2462 2463
		/*
		 * TBD:
		 * we could share the same root & context tables
L
Lucas De Marchi 已提交
2464
		 * among all IOMMU's. Need to Split it later.
2465 2466 2467 2468 2469 2470
		 */
		ret = iommu_alloc_root_entry(iommu);
		if (ret) {
			printk(KERN_ERR "IOMMU: allocate root entry failed\n");
			goto error;
		}
F
Fenghua Yu 已提交
2471
		if (!ecap_pass_through(iommu->ecap))
2472
			hw_pass_through = 0;
2473 2474
	}

2475 2476 2477
	/*
	 * Start from the sane iommu hardware state.
	 */
2478 2479 2480 2481 2482
	for_each_drhd_unit(drhd) {
		if (drhd->ignored)
			continue;

		iommu = drhd->iommu;
2483 2484 2485 2486 2487 2488 2489 2490 2491 2492 2493 2494 2495 2496 2497 2498 2499 2500 2501 2502 2503 2504 2505 2506 2507 2508

		/*
		 * If the queued invalidation is already initialized by us
		 * (for example, while enabling interrupt-remapping) then
		 * we got the things already rolling from a sane state.
		 */
		if (iommu->qi)
			continue;

		/*
		 * Clear any previous faults.
		 */
		dmar_fault(-1, iommu);
		/*
		 * Disable queued invalidation if supported and already enabled
		 * before OS handover.
		 */
		dmar_disable_qi(iommu);
	}

	for_each_drhd_unit(drhd) {
		if (drhd->ignored)
			continue;

		iommu = drhd->iommu;

2509 2510 2511 2512 2513 2514 2515
		if (dmar_enable_qi(iommu)) {
			/*
			 * Queued Invalidate not enabled, use Register Based
			 * Invalidate
			 */
			iommu->flush.flush_context = __iommu_flush_context;
			iommu->flush.flush_iotlb = __iommu_flush_iotlb;
Y
Yinghai Lu 已提交
2516
			printk(KERN_INFO "IOMMU %d 0x%Lx: using Register based "
2517
			       "invalidation\n",
Y
Yinghai Lu 已提交
2518
				iommu->seq_id,
2519
			       (unsigned long long)drhd->reg_base_addr);
2520 2521 2522
		} else {
			iommu->flush.flush_context = qi_flush_context;
			iommu->flush.flush_iotlb = qi_flush_iotlb;
Y
Yinghai Lu 已提交
2523
			printk(KERN_INFO "IOMMU %d 0x%Lx: using Queued "
2524
			       "invalidation\n",
Y
Yinghai Lu 已提交
2525
				iommu->seq_id,
2526
			       (unsigned long long)drhd->reg_base_addr);
2527 2528 2529
		}
	}

2530
	if (iommu_pass_through)
2531 2532
		iommu_identity_mapping |= IDENTMAP_ALL;

2533
#ifdef CONFIG_INTEL_IOMMU_BROKEN_GFX_WA
2534
	iommu_identity_mapping |= IDENTMAP_GFX;
2535
#endif
2536 2537 2538

	check_tylersburg_isoch();

2539
	/*
2540 2541 2542
	 * If pass through is not set or not enabled, setup context entries for
	 * identity mappings for rmrr, gfx, and isa and may fall back to static
	 * identity mapping if iommu_identity_mapping is set.
2543
	 */
2544 2545
	if (iommu_identity_mapping) {
		ret = iommu_prepare_static_identity_mapping(hw_pass_through);
F
Fenghua Yu 已提交
2546
		if (ret) {
2547 2548
			printk(KERN_CRIT "Failed to setup IOMMU pass-through\n");
			goto error;
2549 2550 2551
		}
	}
	/*
2552 2553 2554 2555 2556 2557 2558 2559 2560 2561 2562 2563
	 * For each rmrr
	 *   for each dev attached to rmrr
	 *   do
	 *     locate drhd for dev, alloc domain for dev
	 *     allocate free domain
	 *     allocate page table entries for rmrr
	 *     if context not allocated for bus
	 *           allocate and init context
	 *           set present in root table for this bus
	 *     init context with domain, translation etc
	 *    endfor
	 * endfor
2564
	 */
2565 2566 2567 2568 2569 2570 2571 2572 2573 2574 2575 2576 2577 2578
	printk(KERN_INFO "IOMMU: Setting RMRR:\n");
	for_each_rmrr_units(rmrr) {
		for (i = 0; i < rmrr->devices_cnt; i++) {
			pdev = rmrr->devices[i];
			/*
			 * some BIOS lists non-exist devices in DMAR
			 * table.
			 */
			if (!pdev)
				continue;
			ret = iommu_prepare_rmrr_dev(rmrr, pdev);
			if (ret)
				printk(KERN_ERR
				       "IOMMU: mapping reserved region failed\n");
2579
		}
F
Fenghua Yu 已提交
2580
	}
2581

2582 2583
	iommu_prepare_isa();

2584 2585 2586 2587 2588 2589 2590 2591
	/*
	 * for each drhd
	 *   enable fault log
	 *   global invalidate context cache
	 *   global invalidate iotlb
	 *   enable translation
	 */
	for_each_drhd_unit(drhd) {
2592 2593 2594 2595 2596 2597 2598
		if (drhd->ignored) {
			/*
			 * we always have to disable PMRs or DMA may fail on
			 * this device
			 */
			if (force_on)
				iommu_disable_protect_mem_regions(drhd->iommu);
2599
			continue;
2600
		}
2601 2602 2603 2604
		iommu = drhd->iommu;

		iommu_flush_write_buffer(iommu);

2605 2606 2607 2608
		ret = dmar_set_interrupt(iommu);
		if (ret)
			goto error;

2609 2610
		iommu_set_root_entry(iommu);

2611
		iommu->flush.flush_context(iommu, 0, 0, 0, DMA_CCMD_GLOBAL_INVL);
2612
		iommu->flush.flush_iotlb(iommu, 0, 0, 0, DMA_TLB_GLOBAL_FLUSH);
M
mark gross 已提交
2613

2614 2615 2616
		ret = iommu_enable_translation(iommu);
		if (ret)
			goto error;
2617 2618

		iommu_disable_protect_mem_regions(iommu);
2619 2620 2621 2622 2623 2624 2625 2626 2627 2628
	}

	return 0;
error:
	for_each_drhd_unit(drhd) {
		if (drhd->ignored)
			continue;
		iommu = drhd->iommu;
		free_iommu(iommu);
	}
W
Weidong Han 已提交
2629
	kfree(g_iommus);
2630 2631 2632
	return ret;
}

2633
/* This takes a number of _MM_ pages, not VTD pages */
2634 2635 2636
static struct iova *intel_alloc_iova(struct device *dev,
				     struct dmar_domain *domain,
				     unsigned long nrpages, uint64_t dma_mask)
2637 2638 2639 2640
{
	struct pci_dev *pdev = to_pci_dev(dev);
	struct iova *iova = NULL;

2641 2642 2643 2644
	/* Restrict dma_mask to the width that the iommu can handle */
	dma_mask = min_t(uint64_t, DOMAIN_MAX_ADDR(domain->gaw), dma_mask);

	if (!dmar_forcedac && dma_mask > DMA_BIT_MASK(32)) {
2645 2646
		/*
		 * First try to allocate an io virtual address in
2647
		 * DMA_BIT_MASK(32) and if that fails then try allocating
J
Joe Perches 已提交
2648
		 * from higher range
2649
		 */
2650 2651 2652 2653 2654 2655 2656 2657 2658
		iova = alloc_iova(&domain->iovad, nrpages,
				  IOVA_PFN(DMA_BIT_MASK(32)), 1);
		if (iova)
			return iova;
	}
	iova = alloc_iova(&domain->iovad, nrpages, IOVA_PFN(dma_mask), 1);
	if (unlikely(!iova)) {
		printk(KERN_ERR "Allocating %ld-page iova for %s failed",
		       nrpages, pci_name(pdev));
2659 2660 2661 2662 2663 2664
		return NULL;
	}

	return iova;
}

2665
static struct dmar_domain *__get_valid_domain_for_dev(struct pci_dev *pdev)
2666 2667 2668 2669 2670 2671 2672 2673 2674
{
	struct dmar_domain *domain;
	int ret;

	domain = get_domain_for_dev(pdev,
			DEFAULT_DOMAIN_ADDRESS_WIDTH);
	if (!domain) {
		printk(KERN_ERR
			"Allocating domain for %s failed", pci_name(pdev));
A
Al Viro 已提交
2675
		return NULL;
2676 2677 2678
	}

	/* make sure context mapping is ok */
W
Weidong Han 已提交
2679
	if (unlikely(!domain_context_mapped(pdev))) {
F
Fenghua Yu 已提交
2680 2681
		ret = domain_context_mapping(domain, pdev,
					     CONTEXT_TT_MULTI_LEVEL);
2682 2683 2684 2685
		if (ret) {
			printk(KERN_ERR
				"Domain context map for %s failed",
				pci_name(pdev));
A
Al Viro 已提交
2686
			return NULL;
2687
		}
2688 2689
	}

2690 2691 2692
	return domain;
}

2693 2694 2695 2696 2697 2698 2699 2700 2701 2702 2703 2704
static inline struct dmar_domain *get_valid_domain_for_dev(struct pci_dev *dev)
{
	struct device_domain_info *info;

	/* No lock here, assumes no domain exit in normal case */
	info = dev->dev.archdata.iommu;
	if (likely(info))
		return info->domain;

	return __get_valid_domain_for_dev(dev);
}

2705 2706 2707 2708 2709 2710
static int iommu_dummy(struct pci_dev *pdev)
{
	return pdev->dev.archdata.iommu == DUMMY_DEVICE_DOMAIN_INFO;
}

/* Check if the pdev needs to go through non-identity map and unmap process.*/
2711
static int iommu_no_mapping(struct device *dev)
2712
{
2713
	struct pci_dev *pdev;
2714 2715
	int found;

2716 2717 2718 2719
	if (unlikely(dev->bus != &pci_bus_type))
		return 1;

	pdev = to_pci_dev(dev);
2720 2721 2722
	if (iommu_dummy(pdev))
		return 1;

2723
	if (!iommu_identity_mapping)
2724
		return 0;
2725 2726 2727

	found = identity_mapping(pdev);
	if (found) {
2728
		if (iommu_should_identity_map(pdev, 0))
2729 2730 2731 2732 2733 2734 2735 2736 2737 2738 2739 2740 2741 2742 2743 2744
			return 1;
		else {
			/*
			 * 32 bit DMA is removed from si_domain and fall back
			 * to non-identity mapping.
			 */
			domain_remove_one_dev_info(si_domain, pdev);
			printk(KERN_INFO "32bit %s uses non-identity mapping\n",
			       pci_name(pdev));
			return 0;
		}
	} else {
		/*
		 * In case of a detached 64 bit DMA device from vm, the device
		 * is put into si_domain for identity mapping.
		 */
2745
		if (iommu_should_identity_map(pdev, 0)) {
2746
			int ret;
2747 2748 2749 2750
			ret = domain_add_dev_info(si_domain, pdev,
						  hw_pass_through ?
						  CONTEXT_TT_PASS_THROUGH :
						  CONTEXT_TT_MULTI_LEVEL);
2751 2752 2753 2754 2755 2756 2757 2758
			if (!ret) {
				printk(KERN_INFO "64bit %s uses identity mapping\n",
				       pci_name(pdev));
				return 1;
			}
		}
	}

2759
	return 0;
2760 2761
}

2762 2763
static dma_addr_t __intel_map_single(struct device *hwdev, phys_addr_t paddr,
				     size_t size, int dir, u64 dma_mask)
2764 2765 2766
{
	struct pci_dev *pdev = to_pci_dev(hwdev);
	struct dmar_domain *domain;
F
Fenghua Yu 已提交
2767
	phys_addr_t start_paddr;
2768 2769
	struct iova *iova;
	int prot = 0;
I
Ingo Molnar 已提交
2770
	int ret;
2771
	struct intel_iommu *iommu;
2772
	unsigned long paddr_pfn = paddr >> PAGE_SHIFT;
2773 2774

	BUG_ON(dir == DMA_NONE);
2775

2776
	if (iommu_no_mapping(hwdev))
I
Ingo Molnar 已提交
2777
		return paddr;
2778 2779 2780 2781 2782

	domain = get_valid_domain_for_dev(pdev);
	if (!domain)
		return 0;

2783
	iommu = domain_get_iommu(domain);
2784
	size = aligned_nrpages(paddr, size);
2785

2786
	iova = intel_alloc_iova(hwdev, domain, dma_to_mm_pfn(size), dma_mask);
2787 2788 2789
	if (!iova)
		goto error;

2790 2791 2792 2793 2794
	/*
	 * Check if DMAR supports zero-length reads on write only
	 * mappings..
	 */
	if (dir == DMA_TO_DEVICE || dir == DMA_BIDIRECTIONAL || \
2795
			!cap_zlr(iommu->cap))
2796 2797 2798 2799
		prot |= DMA_PTE_READ;
	if (dir == DMA_FROM_DEVICE || dir == DMA_BIDIRECTIONAL)
		prot |= DMA_PTE_WRITE;
	/*
I
Ingo Molnar 已提交
2800
	 * paddr - (paddr + size) might be partial page, we should map the whole
2801
	 * page.  Note: if two part of one page are separately mapped, we
I
Ingo Molnar 已提交
2802
	 * might have two guest_addr mapping to the same host paddr, but this
2803 2804
	 * is not a big problem
	 */
2805
	ret = domain_pfn_mapping(domain, mm_to_dma_pfn(iova->pfn_lo),
2806
				 mm_to_dma_pfn(paddr_pfn), size, prot);
2807 2808 2809
	if (ret)
		goto error;

2810 2811
	/* it's a non-present to present mapping. Only flush if caching mode */
	if (cap_caching_mode(iommu->cap))
2812
		iommu_flush_iotlb_psi(iommu, domain->id, mm_to_dma_pfn(iova->pfn_lo), size, 1);
2813
	else
2814
		iommu_flush_write_buffer(iommu);
2815

2816 2817 2818
	start_paddr = (phys_addr_t)iova->pfn_lo << PAGE_SHIFT;
	start_paddr += paddr & ~PAGE_MASK;
	return start_paddr;
2819 2820

error:
2821 2822
	if (iova)
		__free_iova(&domain->iovad, iova);
2823
	printk(KERN_ERR"Device %s request: %zx@%llx dir %d --- failed\n",
F
Fenghua Yu 已提交
2824
		pci_name(pdev), size, (unsigned long long)paddr, dir);
2825 2826 2827
	return 0;
}

2828 2829 2830 2831
static dma_addr_t intel_map_page(struct device *dev, struct page *page,
				 unsigned long offset, size_t size,
				 enum dma_data_direction dir,
				 struct dma_attrs *attrs)
2832
{
2833 2834
	return __intel_map_single(dev, page_to_phys(page) + offset, size,
				  dir, to_pci_dev(dev)->dma_mask);
2835 2836
}

M
mark gross 已提交
2837 2838
static void flush_unmaps(void)
{
2839
	int i, j;
M
mark gross 已提交
2840 2841 2842 2843 2844

	timer_on = 0;

	/* just flush them all */
	for (i = 0; i < g_num_of_iommus; i++) {
2845 2846 2847
		struct intel_iommu *iommu = g_iommus[i];
		if (!iommu)
			continue;
2848

2849 2850 2851
		if (!deferred_flush[i].next)
			continue;

2852 2853 2854
		/* In caching mode, global flushes turn emulation expensive */
		if (!cap_caching_mode(iommu->cap))
			iommu->flush.flush_iotlb(iommu, 0, 0, 0,
Y
Yu Zhao 已提交
2855
					 DMA_TLB_GLOBAL_FLUSH);
2856
		for (j = 0; j < deferred_flush[i].next; j++) {
Y
Yu Zhao 已提交
2857 2858
			unsigned long mask;
			struct iova *iova = deferred_flush[i].iova[j];
2859 2860 2861 2862 2863 2864 2865 2866 2867 2868 2869
			struct dmar_domain *domain = deferred_flush[i].domain[j];

			/* On real hardware multiple invalidations are expensive */
			if (cap_caching_mode(iommu->cap))
				iommu_flush_iotlb_psi(iommu, domain->id,
				iova->pfn_lo, iova->pfn_hi - iova->pfn_lo + 1, 0);
			else {
				mask = ilog2(mm_to_dma_pfn(iova->pfn_hi - iova->pfn_lo + 1));
				iommu_flush_dev_iotlb(deferred_flush[i].domain[j],
						(uint64_t)iova->pfn_lo << PAGE_SHIFT, mask);
			}
Y
Yu Zhao 已提交
2870
			__free_iova(&deferred_flush[i].domain[j]->iovad, iova);
2871
		}
2872
		deferred_flush[i].next = 0;
M
mark gross 已提交
2873 2874 2875 2876 2877 2878 2879
	}

	list_size = 0;
}

static void flush_unmaps_timeout(unsigned long data)
{
2880 2881 2882
	unsigned long flags;

	spin_lock_irqsave(&async_umap_flush_lock, flags);
M
mark gross 已提交
2883
	flush_unmaps();
2884
	spin_unlock_irqrestore(&async_umap_flush_lock, flags);
M
mark gross 已提交
2885 2886 2887 2888 2889
}

static void add_unmap(struct dmar_domain *dom, struct iova *iova)
{
	unsigned long flags;
2890
	int next, iommu_id;
2891
	struct intel_iommu *iommu;
M
mark gross 已提交
2892 2893

	spin_lock_irqsave(&async_umap_flush_lock, flags);
2894 2895 2896
	if (list_size == HIGH_WATER_MARK)
		flush_unmaps();

2897 2898
	iommu = domain_get_iommu(dom);
	iommu_id = iommu->seq_id;
2899

2900 2901 2902 2903
	next = deferred_flush[iommu_id].next;
	deferred_flush[iommu_id].domain[next] = dom;
	deferred_flush[iommu_id].iova[next] = iova;
	deferred_flush[iommu_id].next++;
M
mark gross 已提交
2904 2905 2906 2907 2908 2909 2910 2911 2912

	if (!timer_on) {
		mod_timer(&unmap_timer, jiffies + msecs_to_jiffies(10));
		timer_on = 1;
	}
	list_size++;
	spin_unlock_irqrestore(&async_umap_flush_lock, flags);
}

2913 2914 2915
static void intel_unmap_page(struct device *dev, dma_addr_t dev_addr,
			     size_t size, enum dma_data_direction dir,
			     struct dma_attrs *attrs)
2916 2917
{
	struct pci_dev *pdev = to_pci_dev(dev);
2918
	struct dmar_domain *domain;
2919
	unsigned long start_pfn, last_pfn;
2920
	struct iova *iova;
2921
	struct intel_iommu *iommu;
2922

2923
	if (iommu_no_mapping(dev))
2924
		return;
2925

2926 2927 2928
	domain = find_domain(pdev);
	BUG_ON(!domain);

2929 2930
	iommu = domain_get_iommu(domain);

2931
	iova = find_iova(&domain->iovad, IOVA_PFN(dev_addr));
2932 2933
	if (WARN_ONCE(!iova, "Driver unmaps unmatched page at PFN %llx\n",
		      (unsigned long long)dev_addr))
2934 2935
		return;

2936 2937
	start_pfn = mm_to_dma_pfn(iova->pfn_lo);
	last_pfn = mm_to_dma_pfn(iova->pfn_hi + 1) - 1;
2938

2939 2940
	pr_debug("Device %s unmapping: pfn %lx-%lx\n",
		 pci_name(pdev), start_pfn, last_pfn);
2941

2942
	/*  clear the whole page */
2943 2944
	dma_pte_clear_range(domain, start_pfn, last_pfn);

2945
	/* free page tables */
2946 2947
	dma_pte_free_pagetable(domain, start_pfn, last_pfn);

M
mark gross 已提交
2948
	if (intel_iommu_strict) {
2949
		iommu_flush_iotlb_psi(iommu, domain->id, start_pfn,
2950
				      last_pfn - start_pfn + 1, 0);
M
mark gross 已提交
2951 2952 2953 2954 2955 2956 2957 2958 2959
		/* free iova */
		__free_iova(&domain->iovad, iova);
	} else {
		add_unmap(domain, iova);
		/*
		 * queue up the release of the unmap to save the 1/6th of the
		 * cpu used up by the iotlb flush operation...
		 */
	}
2960 2961
}

2962
static void *intel_alloc_coherent(struct device *hwdev, size_t size,
2963 2964
				  dma_addr_t *dma_handle, gfp_t flags,
				  struct dma_attrs *attrs)
2965 2966 2967 2968
{
	void *vaddr;
	int order;

F
Fenghua Yu 已提交
2969
	size = PAGE_ALIGN(size);
2970
	order = get_order(size);
2971 2972 2973 2974 2975 2976 2977 2978 2979

	if (!iommu_no_mapping(hwdev))
		flags &= ~(GFP_DMA | GFP_DMA32);
	else if (hwdev->coherent_dma_mask < dma_get_required_mask(hwdev)) {
		if (hwdev->coherent_dma_mask < DMA_BIT_MASK(32))
			flags |= GFP_DMA;
		else
			flags |= GFP_DMA32;
	}
2980 2981 2982 2983 2984 2985

	vaddr = (void *)__get_free_pages(flags, order);
	if (!vaddr)
		return NULL;
	memset(vaddr, 0, size);

2986 2987 2988
	*dma_handle = __intel_map_single(hwdev, virt_to_bus(vaddr), size,
					 DMA_BIDIRECTIONAL,
					 hwdev->coherent_dma_mask);
2989 2990 2991 2992 2993 2994
	if (*dma_handle)
		return vaddr;
	free_pages((unsigned long)vaddr, order);
	return NULL;
}

2995
static void intel_free_coherent(struct device *hwdev, size_t size, void *vaddr,
2996
				dma_addr_t dma_handle, struct dma_attrs *attrs)
2997 2998 2999
{
	int order;

F
Fenghua Yu 已提交
3000
	size = PAGE_ALIGN(size);
3001 3002
	order = get_order(size);

3003
	intel_unmap_page(hwdev, dma_handle, size, DMA_BIDIRECTIONAL, NULL);
3004 3005 3006
	free_pages((unsigned long)vaddr, order);
}

3007 3008 3009
static void intel_unmap_sg(struct device *hwdev, struct scatterlist *sglist,
			   int nelems, enum dma_data_direction dir,
			   struct dma_attrs *attrs)
3010 3011 3012
{
	struct pci_dev *pdev = to_pci_dev(hwdev);
	struct dmar_domain *domain;
3013
	unsigned long start_pfn, last_pfn;
3014
	struct iova *iova;
3015
	struct intel_iommu *iommu;
3016

3017
	if (iommu_no_mapping(hwdev))
3018 3019 3020
		return;

	domain = find_domain(pdev);
3021 3022 3023
	BUG_ON(!domain);

	iommu = domain_get_iommu(domain);
3024

F
FUJITA Tomonori 已提交
3025
	iova = find_iova(&domain->iovad, IOVA_PFN(sglist[0].dma_address));
3026 3027
	if (WARN_ONCE(!iova, "Driver unmaps unmatched sglist at PFN %llx\n",
		      (unsigned long long)sglist[0].dma_address))
3028 3029
		return;

3030 3031
	start_pfn = mm_to_dma_pfn(iova->pfn_lo);
	last_pfn = mm_to_dma_pfn(iova->pfn_hi + 1) - 1;
3032 3033

	/*  clear the whole page */
3034 3035
	dma_pte_clear_range(domain, start_pfn, last_pfn);

3036
	/* free page tables */
3037
	dma_pte_free_pagetable(domain, start_pfn, last_pfn);
3038

3039 3040
	if (intel_iommu_strict) {
		iommu_flush_iotlb_psi(iommu, domain->id, start_pfn,
3041
				      last_pfn - start_pfn + 1, 0);
3042 3043 3044 3045 3046 3047 3048 3049 3050
		/* free iova */
		__free_iova(&domain->iovad, iova);
	} else {
		add_unmap(domain, iova);
		/*
		 * queue up the release of the unmap to save the 1/6th of the
		 * cpu used up by the iotlb flush operation...
		 */
	}
3051 3052 3053
}

static int intel_nontranslate_map_sg(struct device *hddev,
F
FUJITA Tomonori 已提交
3054
	struct scatterlist *sglist, int nelems, int dir)
3055 3056
{
	int i;
F
FUJITA Tomonori 已提交
3057
	struct scatterlist *sg;
3058

F
FUJITA Tomonori 已提交
3059
	for_each_sg(sglist, sg, nelems, i) {
F
FUJITA Tomonori 已提交
3060
		BUG_ON(!sg_page(sg));
3061
		sg->dma_address = page_to_phys(sg_page(sg)) + sg->offset;
F
FUJITA Tomonori 已提交
3062
		sg->dma_length = sg->length;
3063 3064 3065 3066
	}
	return nelems;
}

3067 3068
static int intel_map_sg(struct device *hwdev, struct scatterlist *sglist, int nelems,
			enum dma_data_direction dir, struct dma_attrs *attrs)
3069 3070 3071 3072
{
	int i;
	struct pci_dev *pdev = to_pci_dev(hwdev);
	struct dmar_domain *domain;
3073 3074 3075 3076
	size_t size = 0;
	int prot = 0;
	struct iova *iova = NULL;
	int ret;
F
FUJITA Tomonori 已提交
3077
	struct scatterlist *sg;
3078
	unsigned long start_vpfn;
3079
	struct intel_iommu *iommu;
3080 3081

	BUG_ON(dir == DMA_NONE);
3082
	if (iommu_no_mapping(hwdev))
F
FUJITA Tomonori 已提交
3083
		return intel_nontranslate_map_sg(hwdev, sglist, nelems, dir);
3084

3085 3086 3087 3088
	domain = get_valid_domain_for_dev(pdev);
	if (!domain)
		return 0;

3089 3090
	iommu = domain_get_iommu(domain);

3091
	for_each_sg(sglist, sg, nelems, i)
3092
		size += aligned_nrpages(sg->offset, sg->length);
3093

3094 3095
	iova = intel_alloc_iova(hwdev, domain, dma_to_mm_pfn(size),
				pdev->dma_mask);
3096
	if (!iova) {
F
FUJITA Tomonori 已提交
3097
		sglist->dma_length = 0;
3098 3099 3100 3101 3102 3103 3104 3105
		return 0;
	}

	/*
	 * Check if DMAR supports zero-length reads on write only
	 * mappings..
	 */
	if (dir == DMA_TO_DEVICE || dir == DMA_BIDIRECTIONAL || \
3106
			!cap_zlr(iommu->cap))
3107 3108 3109 3110
		prot |= DMA_PTE_READ;
	if (dir == DMA_FROM_DEVICE || dir == DMA_BIDIRECTIONAL)
		prot |= DMA_PTE_WRITE;

3111
	start_vpfn = mm_to_dma_pfn(iova->pfn_lo);
3112

3113
	ret = domain_sg_mapping(domain, start_vpfn, sglist, size, prot);
3114 3115 3116 3117 3118 3119 3120 3121 3122 3123
	if (unlikely(ret)) {
		/*  clear the page */
		dma_pte_clear_range(domain, start_vpfn,
				    start_vpfn + size - 1);
		/* free page tables */
		dma_pte_free_pagetable(domain, start_vpfn,
				       start_vpfn + size - 1);
		/* free iova */
		__free_iova(&domain->iovad, iova);
		return 0;
3124 3125
	}

3126 3127
	/* it's a non-present to present mapping. Only flush if caching mode */
	if (cap_caching_mode(iommu->cap))
3128
		iommu_flush_iotlb_psi(iommu, domain->id, start_vpfn, size, 1);
3129
	else
3130
		iommu_flush_write_buffer(iommu);
3131

3132 3133 3134
	return nelems;
}

3135 3136 3137 3138 3139
static int intel_mapping_error(struct device *dev, dma_addr_t dma_addr)
{
	return !dma_addr;
}

3140
struct dma_map_ops intel_dma_ops = {
3141 3142
	.alloc = intel_alloc_coherent,
	.free = intel_free_coherent,
3143 3144
	.map_sg = intel_map_sg,
	.unmap_sg = intel_unmap_sg,
3145 3146
	.map_page = intel_map_page,
	.unmap_page = intel_unmap_page,
3147
	.mapping_error = intel_mapping_error,
3148 3149 3150 3151 3152 3153 3154 3155 3156 3157 3158 3159 3160 3161 3162 3163 3164 3165 3166 3167 3168 3169 3170 3171 3172 3173 3174 3175 3176 3177 3178 3179 3180 3181 3182 3183 3184 3185 3186 3187 3188 3189 3190 3191 3192 3193 3194 3195 3196 3197 3198 3199 3200 3201 3202 3203 3204 3205 3206 3207 3208 3209 3210 3211 3212 3213 3214 3215 3216 3217 3218 3219 3220 3221 3222 3223 3224 3225 3226 3227 3228 3229 3230 3231
};

static inline int iommu_domain_cache_init(void)
{
	int ret = 0;

	iommu_domain_cache = kmem_cache_create("iommu_domain",
					 sizeof(struct dmar_domain),
					 0,
					 SLAB_HWCACHE_ALIGN,

					 NULL);
	if (!iommu_domain_cache) {
		printk(KERN_ERR "Couldn't create iommu_domain cache\n");
		ret = -ENOMEM;
	}

	return ret;
}

static inline int iommu_devinfo_cache_init(void)
{
	int ret = 0;

	iommu_devinfo_cache = kmem_cache_create("iommu_devinfo",
					 sizeof(struct device_domain_info),
					 0,
					 SLAB_HWCACHE_ALIGN,
					 NULL);
	if (!iommu_devinfo_cache) {
		printk(KERN_ERR "Couldn't create devinfo cache\n");
		ret = -ENOMEM;
	}

	return ret;
}

static inline int iommu_iova_cache_init(void)
{
	int ret = 0;

	iommu_iova_cache = kmem_cache_create("iommu_iova",
					 sizeof(struct iova),
					 0,
					 SLAB_HWCACHE_ALIGN,
					 NULL);
	if (!iommu_iova_cache) {
		printk(KERN_ERR "Couldn't create iova cache\n");
		ret = -ENOMEM;
	}

	return ret;
}

static int __init iommu_init_mempool(void)
{
	int ret;
	ret = iommu_iova_cache_init();
	if (ret)
		return ret;

	ret = iommu_domain_cache_init();
	if (ret)
		goto domain_error;

	ret = iommu_devinfo_cache_init();
	if (!ret)
		return ret;

	kmem_cache_destroy(iommu_domain_cache);
domain_error:
	kmem_cache_destroy(iommu_iova_cache);

	return -ENOMEM;
}

static void __init iommu_exit_mempool(void)
{
	kmem_cache_destroy(iommu_devinfo_cache);
	kmem_cache_destroy(iommu_domain_cache);
	kmem_cache_destroy(iommu_iova_cache);

}

3232 3233 3234 3235 3236 3237 3238 3239 3240 3241 3242 3243 3244 3245 3246 3247 3248 3249 3250 3251 3252 3253 3254 3255 3256 3257 3258 3259
static void quirk_ioat_snb_local_iommu(struct pci_dev *pdev)
{
	struct dmar_drhd_unit *drhd;
	u32 vtbar;
	int rc;

	/* We know that this device on this chipset has its own IOMMU.
	 * If we find it under a different IOMMU, then the BIOS is lying
	 * to us. Hope that the IOMMU for this device is actually
	 * disabled, and it needs no translation...
	 */
	rc = pci_bus_read_config_dword(pdev->bus, PCI_DEVFN(0, 0), 0xb0, &vtbar);
	if (rc) {
		/* "can't" happen */
		dev_info(&pdev->dev, "failed to run vt-d quirk\n");
		return;
	}
	vtbar &= 0xffff0000;

	/* we know that the this iommu should be at offset 0xa000 from vtbar */
	drhd = dmar_find_matched_drhd_unit(pdev);
	if (WARN_TAINT_ONCE(!drhd || drhd->reg_base_addr - vtbar != 0xa000,
			    TAINT_FIRMWARE_WORKAROUND,
			    "BIOS assigned incorrect VT-d unit for Intel(R) QuickData Technology device\n"))
		pdev->dev.archdata.iommu = DUMMY_DEVICE_DOMAIN_INFO;
}
DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IOAT_SNB, quirk_ioat_snb_local_iommu);

3260 3261 3262 3263 3264 3265 3266 3267 3268 3269 3270 3271 3272 3273 3274 3275 3276 3277 3278 3279 3280 3281 3282
static void __init init_no_remapping_devices(void)
{
	struct dmar_drhd_unit *drhd;

	for_each_drhd_unit(drhd) {
		if (!drhd->include_all) {
			int i;
			for (i = 0; i < drhd->devices_cnt; i++)
				if (drhd->devices[i] != NULL)
					break;
			/* ignore DMAR unit if no pci devices exist */
			if (i == drhd->devices_cnt)
				drhd->ignored = 1;
		}
	}

	for_each_drhd_unit(drhd) {
		int i;
		if (drhd->ignored || drhd->include_all)
			continue;

		for (i = 0; i < drhd->devices_cnt; i++)
			if (drhd->devices[i] &&
3283
			    !IS_GFX_DEVICE(drhd->devices[i]))
3284 3285 3286 3287 3288
				break;

		if (i < drhd->devices_cnt)
			continue;

3289 3290 3291 3292 3293 3294 3295 3296 3297 3298 3299
		/* This IOMMU has *only* gfx devices. Either bypass it or
		   set the gfx_mapped flag, as appropriate */
		if (dmar_map_gfx) {
			intel_iommu_gfx_mapped = 1;
		} else {
			drhd->ignored = 1;
			for (i = 0; i < drhd->devices_cnt; i++) {
				if (!drhd->devices[i])
					continue;
				drhd->devices[i]->dev.archdata.iommu = DUMMY_DEVICE_DOMAIN_INFO;
			}
3300 3301 3302 3303
		}
	}
}

3304 3305 3306 3307 3308 3309 3310 3311 3312 3313
#ifdef CONFIG_SUSPEND
static int init_iommu_hw(void)
{
	struct dmar_drhd_unit *drhd;
	struct intel_iommu *iommu = NULL;

	for_each_active_iommu(iommu, drhd)
		if (iommu->qi)
			dmar_reenable_qi(iommu);

3314 3315 3316 3317 3318 3319 3320 3321 3322 3323 3324
	for_each_iommu(iommu, drhd) {
		if (drhd->ignored) {
			/*
			 * we always have to disable PMRs or DMA may fail on
			 * this device
			 */
			if (force_on)
				iommu_disable_protect_mem_regions(iommu);
			continue;
		}
	
3325 3326 3327 3328 3329
		iommu_flush_write_buffer(iommu);

		iommu_set_root_entry(iommu);

		iommu->flush.flush_context(iommu, 0, 0, 0,
3330
					   DMA_CCMD_GLOBAL_INVL);
3331
		iommu->flush.flush_iotlb(iommu, 0, 0, 0,
3332
					 DMA_TLB_GLOBAL_FLUSH);
3333 3334
		if (iommu_enable_translation(iommu))
			return 1;
3335
		iommu_disable_protect_mem_regions(iommu);
3336 3337 3338 3339 3340 3341 3342 3343 3344 3345 3346 3347
	}

	return 0;
}

static void iommu_flush_all(void)
{
	struct dmar_drhd_unit *drhd;
	struct intel_iommu *iommu;

	for_each_active_iommu(iommu, drhd) {
		iommu->flush.flush_context(iommu, 0, 0, 0,
3348
					   DMA_CCMD_GLOBAL_INVL);
3349
		iommu->flush.flush_iotlb(iommu, 0, 0, 0,
3350
					 DMA_TLB_GLOBAL_FLUSH);
3351 3352 3353
	}
}

3354
static int iommu_suspend(void)
3355 3356 3357 3358 3359 3360 3361 3362 3363 3364 3365 3366 3367 3368 3369 3370 3371
{
	struct dmar_drhd_unit *drhd;
	struct intel_iommu *iommu = NULL;
	unsigned long flag;

	for_each_active_iommu(iommu, drhd) {
		iommu->iommu_state = kzalloc(sizeof(u32) * MAX_SR_DMAR_REGS,
						 GFP_ATOMIC);
		if (!iommu->iommu_state)
			goto nomem;
	}

	iommu_flush_all();

	for_each_active_iommu(iommu, drhd) {
		iommu_disable_translation(iommu);

3372
		raw_spin_lock_irqsave(&iommu->register_lock, flag);
3373 3374 3375 3376 3377 3378 3379 3380 3381 3382

		iommu->iommu_state[SR_DMAR_FECTL_REG] =
			readl(iommu->reg + DMAR_FECTL_REG);
		iommu->iommu_state[SR_DMAR_FEDATA_REG] =
			readl(iommu->reg + DMAR_FEDATA_REG);
		iommu->iommu_state[SR_DMAR_FEADDR_REG] =
			readl(iommu->reg + DMAR_FEADDR_REG);
		iommu->iommu_state[SR_DMAR_FEUADDR_REG] =
			readl(iommu->reg + DMAR_FEUADDR_REG);

3383
		raw_spin_unlock_irqrestore(&iommu->register_lock, flag);
3384 3385 3386 3387 3388 3389 3390 3391 3392 3393
	}
	return 0;

nomem:
	for_each_active_iommu(iommu, drhd)
		kfree(iommu->iommu_state);

	return -ENOMEM;
}

3394
static void iommu_resume(void)
3395 3396 3397 3398 3399 3400
{
	struct dmar_drhd_unit *drhd;
	struct intel_iommu *iommu = NULL;
	unsigned long flag;

	if (init_iommu_hw()) {
3401 3402 3403 3404
		if (force_on)
			panic("tboot: IOMMU setup failed, DMAR can not resume!\n");
		else
			WARN(1, "IOMMU setup failed, DMAR can not resume!\n");
3405
		return;
3406 3407 3408 3409
	}

	for_each_active_iommu(iommu, drhd) {

3410
		raw_spin_lock_irqsave(&iommu->register_lock, flag);
3411 3412 3413 3414 3415 3416 3417 3418 3419 3420

		writel(iommu->iommu_state[SR_DMAR_FECTL_REG],
			iommu->reg + DMAR_FECTL_REG);
		writel(iommu->iommu_state[SR_DMAR_FEDATA_REG],
			iommu->reg + DMAR_FEDATA_REG);
		writel(iommu->iommu_state[SR_DMAR_FEADDR_REG],
			iommu->reg + DMAR_FEADDR_REG);
		writel(iommu->iommu_state[SR_DMAR_FEUADDR_REG],
			iommu->reg + DMAR_FEUADDR_REG);

3421
		raw_spin_unlock_irqrestore(&iommu->register_lock, flag);
3422 3423 3424 3425 3426 3427
	}

	for_each_active_iommu(iommu, drhd)
		kfree(iommu->iommu_state);
}

3428
static struct syscore_ops iommu_syscore_ops = {
3429 3430 3431 3432
	.resume		= iommu_resume,
	.suspend	= iommu_suspend,
};

3433
static void __init init_iommu_pm_ops(void)
3434
{
3435
	register_syscore_ops(&iommu_syscore_ops);
3436 3437 3438
}

#else
3439
static inline void init_iommu_pm_ops(void) {}
3440 3441
#endif	/* CONFIG_PM */

3442 3443 3444 3445 3446 3447 3448 3449 3450 3451 3452 3453 3454 3455 3456 3457 3458 3459 3460 3461 3462 3463 3464 3465 3466 3467 3468 3469 3470 3471 3472 3473 3474 3475 3476 3477 3478 3479 3480 3481 3482 3483 3484 3485 3486 3487 3488 3489 3490 3491 3492 3493 3494 3495 3496 3497 3498 3499 3500 3501 3502 3503 3504 3505 3506 3507 3508 3509 3510 3511 3512 3513 3514 3515 3516 3517 3518 3519 3520 3521 3522 3523 3524 3525 3526 3527 3528 3529 3530 3531 3532 3533 3534 3535 3536 3537 3538 3539 3540 3541 3542 3543 3544 3545 3546 3547 3548 3549 3550 3551 3552 3553 3554 3555 3556 3557 3558 3559 3560 3561 3562 3563 3564 3565
LIST_HEAD(dmar_rmrr_units);

static void __init dmar_register_rmrr_unit(struct dmar_rmrr_unit *rmrr)
{
	list_add(&rmrr->list, &dmar_rmrr_units);
}


int __init dmar_parse_one_rmrr(struct acpi_dmar_header *header)
{
	struct acpi_dmar_reserved_memory *rmrr;
	struct dmar_rmrr_unit *rmrru;

	rmrru = kzalloc(sizeof(*rmrru), GFP_KERNEL);
	if (!rmrru)
		return -ENOMEM;

	rmrru->hdr = header;
	rmrr = (struct acpi_dmar_reserved_memory *)header;
	rmrru->base_address = rmrr->base_address;
	rmrru->end_address = rmrr->end_address;

	dmar_register_rmrr_unit(rmrru);
	return 0;
}

static int __init
rmrr_parse_dev(struct dmar_rmrr_unit *rmrru)
{
	struct acpi_dmar_reserved_memory *rmrr;
	int ret;

	rmrr = (struct acpi_dmar_reserved_memory *) rmrru->hdr;
	ret = dmar_parse_dev_scope((void *)(rmrr + 1),
		((void *)rmrr) + rmrr->header.length,
		&rmrru->devices_cnt, &rmrru->devices, rmrr->segment);

	if (ret || (rmrru->devices_cnt == 0)) {
		list_del(&rmrru->list);
		kfree(rmrru);
	}
	return ret;
}

static LIST_HEAD(dmar_atsr_units);

int __init dmar_parse_one_atsr(struct acpi_dmar_header *hdr)
{
	struct acpi_dmar_atsr *atsr;
	struct dmar_atsr_unit *atsru;

	atsr = container_of(hdr, struct acpi_dmar_atsr, header);
	atsru = kzalloc(sizeof(*atsru), GFP_KERNEL);
	if (!atsru)
		return -ENOMEM;

	atsru->hdr = hdr;
	atsru->include_all = atsr->flags & 0x1;

	list_add(&atsru->list, &dmar_atsr_units);

	return 0;
}

static int __init atsr_parse_dev(struct dmar_atsr_unit *atsru)
{
	int rc;
	struct acpi_dmar_atsr *atsr;

	if (atsru->include_all)
		return 0;

	atsr = container_of(atsru->hdr, struct acpi_dmar_atsr, header);
	rc = dmar_parse_dev_scope((void *)(atsr + 1),
				(void *)atsr + atsr->header.length,
				&atsru->devices_cnt, &atsru->devices,
				atsr->segment);
	if (rc || !atsru->devices_cnt) {
		list_del(&atsru->list);
		kfree(atsru);
	}

	return rc;
}

int dmar_find_matched_atsr_unit(struct pci_dev *dev)
{
	int i;
	struct pci_bus *bus;
	struct acpi_dmar_atsr *atsr;
	struct dmar_atsr_unit *atsru;

	dev = pci_physfn(dev);

	list_for_each_entry(atsru, &dmar_atsr_units, list) {
		atsr = container_of(atsru->hdr, struct acpi_dmar_atsr, header);
		if (atsr->segment == pci_domain_nr(dev->bus))
			goto found;
	}

	return 0;

found:
	for (bus = dev->bus; bus; bus = bus->parent) {
		struct pci_dev *bridge = bus->self;

		if (!bridge || !pci_is_pcie(bridge) ||
		    bridge->pcie_type == PCI_EXP_TYPE_PCI_BRIDGE)
			return 0;

		if (bridge->pcie_type == PCI_EXP_TYPE_ROOT_PORT) {
			for (i = 0; i < atsru->devices_cnt; i++)
				if (atsru->devices[i] == bridge)
					return 1;
			break;
		}
	}

	if (atsru->include_all)
		return 1;

	return 0;
}

3566
int __init dmar_parse_rmrr_atsr_dev(void)
3567 3568 3569 3570 3571 3572 3573 3574 3575 3576 3577 3578 3579 3580 3581 3582 3583 3584 3585 3586
{
	struct dmar_rmrr_unit *rmrr, *rmrr_n;
	struct dmar_atsr_unit *atsr, *atsr_n;
	int ret = 0;

	list_for_each_entry_safe(rmrr, rmrr_n, &dmar_rmrr_units, list) {
		ret = rmrr_parse_dev(rmrr);
		if (ret)
			return ret;
	}

	list_for_each_entry_safe(atsr, atsr_n, &dmar_atsr_units, list) {
		ret = atsr_parse_dev(atsr);
		if (ret)
			return ret;
	}

	return ret;
}

F
Fenghua Yu 已提交
3587 3588 3589 3590 3591 3592 3593 3594 3595 3596 3597 3598 3599
/*
 * Here we only respond to action of unbound device from driver.
 *
 * Added device is not attached to its DMAR domain here yet. That will happen
 * when mapping the device to iova.
 */
static int device_notifier(struct notifier_block *nb,
				  unsigned long action, void *data)
{
	struct device *dev = data;
	struct pci_dev *pdev = to_pci_dev(dev);
	struct dmar_domain *domain;

3600 3601 3602
	if (iommu_no_mapping(dev))
		return 0;

F
Fenghua Yu 已提交
3603 3604 3605 3606
	domain = find_domain(pdev);
	if (!domain)
		return 0;

3607
	if (action == BUS_NOTIFY_UNBOUND_DRIVER && !iommu_pass_through) {
F
Fenghua Yu 已提交
3608 3609
		domain_remove_one_dev_info(domain, pdev);

3610 3611 3612 3613 3614 3615
		if (!(domain->flags & DOMAIN_FLAG_VIRTUAL_MACHINE) &&
		    !(domain->flags & DOMAIN_FLAG_STATIC_IDENTITY) &&
		    list_empty(&domain->devices))
			domain_exit(domain);
	}

F
Fenghua Yu 已提交
3616 3617 3618 3619 3620 3621 3622
	return 0;
}

static struct notifier_block device_nb = {
	.notifier_call = device_notifier,
};

3623 3624 3625 3626
int __init intel_iommu_init(void)
{
	int ret = 0;

3627 3628 3629 3630 3631 3632
	/* VT-d is required for a TXT/tboot launch, so enforce that */
	force_on = tboot_force_iommu();

	if (dmar_table_init()) {
		if (force_on)
			panic("tboot: Failed to initialize DMAR table\n");
3633
		return 	-ENODEV;
3634
	}
3635

3636
	if (dmar_dev_scope_init() < 0) {
3637 3638
		if (force_on)
			panic("tboot: Failed to initialize DMAR device scope\n");
3639
		return 	-ENODEV;
3640
	}
3641

3642
	if (no_iommu || dmar_disabled)
3643 3644
		return -ENODEV;

3645 3646 3647 3648 3649 3650
	if (iommu_init_mempool()) {
		if (force_on)
			panic("tboot: Failed to initialize iommu memory\n");
		return 	-ENODEV;
	}

3651 3652 3653 3654 3655 3656
	if (list_empty(&dmar_rmrr_units))
		printk(KERN_INFO "DMAR: No RMRR found\n");

	if (list_empty(&dmar_atsr_units))
		printk(KERN_INFO "DMAR: No ATSR found\n");

3657 3658 3659 3660 3661
	if (dmar_init_reserved_ranges()) {
		if (force_on)
			panic("tboot: Failed to reserve iommu ranges\n");
		return 	-ENODEV;
	}
3662 3663 3664

	init_no_remapping_devices();

3665
	ret = init_dmars();
3666
	if (ret) {
3667 3668
		if (force_on)
			panic("tboot: Failed to initialize DMARs\n");
3669 3670 3671 3672 3673 3674 3675 3676
		printk(KERN_ERR "IOMMU: dmar init failed\n");
		put_iova_domain(&reserved_iova_list);
		iommu_exit_mempool();
		return ret;
	}
	printk(KERN_INFO
	"PCI-DMA: Intel(R) Virtualization Technology for Directed I/O\n");

M
mark gross 已提交
3677
	init_timer(&unmap_timer);
3678 3679 3680
#ifdef CONFIG_SWIOTLB
	swiotlb = 0;
#endif
3681
	dma_ops = &intel_dma_ops;
F
Fenghua Yu 已提交
3682

3683
	init_iommu_pm_ops();
3684

3685
	bus_set_iommu(&pci_bus_type, &intel_iommu_ops);
3686

F
Fenghua Yu 已提交
3687 3688
	bus_register_notifier(&pci_bus_type, &device_nb);

3689 3690
	intel_iommu_enabled = 1;

3691 3692
	return 0;
}
3693

3694 3695 3696 3697 3698 3699 3700 3701 3702 3703 3704 3705 3706 3707 3708
static void iommu_detach_dependent_devices(struct intel_iommu *iommu,
					   struct pci_dev *pdev)
{
	struct pci_dev *tmp, *parent;

	if (!iommu || !pdev)
		return;

	/* dependent device detach */
	tmp = pci_find_upstream_pcie_bridge(pdev);
	/* Secondary interface's bus number and devfn 0 */
	if (tmp) {
		parent = pdev->bus->self;
		while (parent != tmp) {
			iommu_detach_dev(iommu, parent->bus->number,
3709
					 parent->devfn);
3710 3711
			parent = parent->bus->self;
		}
3712
		if (pci_is_pcie(tmp)) /* this is a PCIe-to-PCI bridge */
3713 3714 3715
			iommu_detach_dev(iommu,
				tmp->subordinate->number, 0);
		else /* this is a legacy PCI bridge */
3716 3717
			iommu_detach_dev(iommu, tmp->bus->number,
					 tmp->devfn);
3718 3719 3720
	}
}

3721
static void domain_remove_one_dev_info(struct dmar_domain *domain,
3722 3723 3724 3725 3726 3727 3728 3729
					  struct pci_dev *pdev)
{
	struct device_domain_info *info;
	struct intel_iommu *iommu;
	unsigned long flags;
	int found = 0;
	struct list_head *entry, *tmp;

3730 3731
	iommu = device_to_iommu(pci_domain_nr(pdev->bus), pdev->bus->number,
				pdev->devfn);
3732 3733 3734 3735 3736 3737
	if (!iommu)
		return;

	spin_lock_irqsave(&device_domain_lock, flags);
	list_for_each_safe(entry, tmp, &domain->devices) {
		info = list_entry(entry, struct device_domain_info, link);
3738 3739
		if (info->segment == pci_domain_nr(pdev->bus) &&
		    info->bus == pdev->bus->number &&
3740
		    info->devfn == pdev->devfn) {
3741
			unlink_domain_info(info);
3742 3743
			spin_unlock_irqrestore(&device_domain_lock, flags);

Y
Yu Zhao 已提交
3744
			iommu_disable_dev_iotlb(info);
3745
			iommu_detach_dev(iommu, info->bus, info->devfn);
3746
			iommu_detach_dependent_devices(iommu, pdev);
3747 3748 3749 3750 3751 3752 3753 3754 3755 3756 3757 3758 3759 3760
			free_devinfo_mem(info);

			spin_lock_irqsave(&device_domain_lock, flags);

			if (found)
				break;
			else
				continue;
		}

		/* if there is no other devices under the same iommu
		 * owned by this domain, clear this iommu in iommu_bmp
		 * update iommu count and coherency
		 */
3761 3762
		if (iommu == device_to_iommu(info->segment, info->bus,
					    info->devfn))
3763 3764 3765
			found = 1;
	}

3766 3767
	spin_unlock_irqrestore(&device_domain_lock, flags);

3768 3769 3770
	if (found == 0) {
		unsigned long tmp_flags;
		spin_lock_irqsave(&domain->iommu_lock, tmp_flags);
3771
		clear_bit(iommu->seq_id, domain->iommu_bmp);
3772
		domain->iommu_count--;
3773
		domain_update_iommu_cap(domain);
3774
		spin_unlock_irqrestore(&domain->iommu_lock, tmp_flags);
3775

3776 3777 3778 3779 3780 3781 3782
		if (!(domain->flags & DOMAIN_FLAG_VIRTUAL_MACHINE) &&
		    !(domain->flags & DOMAIN_FLAG_STATIC_IDENTITY)) {
			spin_lock_irqsave(&iommu->lock, tmp_flags);
			clear_bit(domain->id, iommu->domain_ids);
			iommu->domains[domain->id] = NULL;
			spin_unlock_irqrestore(&iommu->lock, tmp_flags);
		}
3783 3784 3785 3786 3787 3788 3789 3790 3791 3792 3793 3794 3795
	}
}

static void vm_domain_remove_all_dev_info(struct dmar_domain *domain)
{
	struct device_domain_info *info;
	struct intel_iommu *iommu;
	unsigned long flags1, flags2;

	spin_lock_irqsave(&device_domain_lock, flags1);
	while (!list_empty(&domain->devices)) {
		info = list_entry(domain->devices.next,
			struct device_domain_info, link);
3796
		unlink_domain_info(info);
3797 3798
		spin_unlock_irqrestore(&device_domain_lock, flags1);

Y
Yu Zhao 已提交
3799
		iommu_disable_dev_iotlb(info);
3800
		iommu = device_to_iommu(info->segment, info->bus, info->devfn);
3801
		iommu_detach_dev(iommu, info->bus, info->devfn);
3802
		iommu_detach_dependent_devices(iommu, info->dev);
3803 3804

		/* clear this iommu in iommu_bmp, update iommu count
3805
		 * and capabilities
3806 3807 3808
		 */
		spin_lock_irqsave(&domain->iommu_lock, flags2);
		if (test_and_clear_bit(iommu->seq_id,
3809
				       domain->iommu_bmp)) {
3810
			domain->iommu_count--;
3811
			domain_update_iommu_cap(domain);
3812 3813 3814 3815 3816 3817 3818 3819 3820
		}
		spin_unlock_irqrestore(&domain->iommu_lock, flags2);

		free_devinfo_mem(info);
		spin_lock_irqsave(&device_domain_lock, flags1);
	}
	spin_unlock_irqrestore(&device_domain_lock, flags1);
}

3821 3822 3823 3824 3825 3826 3827 3828 3829 3830 3831 3832
/* domain id for virtual machine, it won't be set in context */
static unsigned long vm_domid;

static struct dmar_domain *iommu_alloc_vm_domain(void)
{
	struct dmar_domain *domain;

	domain = alloc_domain_mem();
	if (!domain)
		return NULL;

	domain->id = vm_domid++;
3833
	domain->nid = -1;
3834
	memset(domain->iommu_bmp, 0, sizeof(domain->iommu_bmp));
3835 3836 3837 3838 3839
	domain->flags = DOMAIN_FLAG_VIRTUAL_MACHINE;

	return domain;
}

3840
static int md_domain_init(struct dmar_domain *domain, int guest_width)
3841 3842 3843 3844 3845 3846 3847 3848 3849 3850 3851 3852 3853 3854 3855 3856 3857
{
	int adjust_width;

	init_iova_domain(&domain->iovad, DMA_32BIT_PFN);
	spin_lock_init(&domain->iommu_lock);

	domain_reserve_special_ranges(domain);

	/* calculate AGAW */
	domain->gaw = guest_width;
	adjust_width = guestwidth_to_adjustwidth(guest_width);
	domain->agaw = width_to_agaw(adjust_width);

	INIT_LIST_HEAD(&domain->devices);

	domain->iommu_count = 0;
	domain->iommu_coherency = 0;
3858
	domain->iommu_snooping = 0;
3859
	domain->iommu_superpage = 0;
3860
	domain->max_addr = 0;
3861
	domain->nid = -1;
3862 3863

	/* always allocate the top pgd */
3864
	domain->pgd = (struct dma_pte *)alloc_pgtable_page(domain->nid);
3865 3866 3867 3868 3869 3870 3871 3872 3873 3874 3875 3876 3877 3878 3879 3880 3881 3882 3883 3884
	if (!domain->pgd)
		return -ENOMEM;
	domain_flush_cache(domain, domain->pgd, PAGE_SIZE);
	return 0;
}

static void iommu_free_vm_domain(struct dmar_domain *domain)
{
	unsigned long flags;
	struct dmar_drhd_unit *drhd;
	struct intel_iommu *iommu;
	unsigned long i;
	unsigned long ndomains;

	for_each_drhd_unit(drhd) {
		if (drhd->ignored)
			continue;
		iommu = drhd->iommu;

		ndomains = cap_ndoms(iommu->cap);
3885
		for_each_set_bit(i, iommu->domain_ids, ndomains) {
3886 3887 3888 3889 3890 3891 3892 3893 3894 3895 3896 3897 3898 3899 3900 3901 3902 3903 3904 3905 3906 3907
			if (iommu->domains[i] == domain) {
				spin_lock_irqsave(&iommu->lock, flags);
				clear_bit(i, iommu->domain_ids);
				iommu->domains[i] = NULL;
				spin_unlock_irqrestore(&iommu->lock, flags);
				break;
			}
		}
	}
}

static void vm_domain_exit(struct dmar_domain *domain)
{
	/* Domain 0 is reserved, so dont process it */
	if (!domain)
		return;

	vm_domain_remove_all_dev_info(domain);
	/* destroy iovas */
	put_iova_domain(&domain->iovad);

	/* clear ptes */
3908
	dma_pte_clear_range(domain, 0, DOMAIN_MAX_PFN(domain->gaw));
3909 3910

	/* free page tables */
3911
	dma_pte_free_pagetable(domain, 0, DOMAIN_MAX_PFN(domain->gaw));
3912 3913 3914 3915 3916

	iommu_free_vm_domain(domain);
	free_domain_mem(domain);
}

3917
static int intel_iommu_domain_init(struct iommu_domain *domain)
K
Kay, Allen M 已提交
3918
{
3919
	struct dmar_domain *dmar_domain;
K
Kay, Allen M 已提交
3920

3921 3922
	dmar_domain = iommu_alloc_vm_domain();
	if (!dmar_domain) {
K
Kay, Allen M 已提交
3923
		printk(KERN_ERR
3924 3925
			"intel_iommu_domain_init: dmar_domain == NULL\n");
		return -ENOMEM;
K
Kay, Allen M 已提交
3926
	}
3927
	if (md_domain_init(dmar_domain, DEFAULT_DOMAIN_ADDRESS_WIDTH)) {
K
Kay, Allen M 已提交
3928
		printk(KERN_ERR
3929 3930 3931
			"intel_iommu_domain_init() failed\n");
		vm_domain_exit(dmar_domain);
		return -ENOMEM;
K
Kay, Allen M 已提交
3932
	}
3933
	domain_update_iommu_cap(dmar_domain);
3934
	domain->priv = dmar_domain;
3935

3936 3937 3938 3939
	domain->geometry.aperture_start = 0;
	domain->geometry.aperture_end   = __DOMAIN_MAX_ADDR(dmar_domain->gaw);
	domain->geometry.force_aperture = true;

3940
	return 0;
K
Kay, Allen M 已提交
3941 3942
}

3943
static void intel_iommu_domain_destroy(struct iommu_domain *domain)
K
Kay, Allen M 已提交
3944
{
3945 3946 3947 3948
	struct dmar_domain *dmar_domain = domain->priv;

	domain->priv = NULL;
	vm_domain_exit(dmar_domain);
K
Kay, Allen M 已提交
3949 3950
}

3951 3952
static int intel_iommu_attach_device(struct iommu_domain *domain,
				     struct device *dev)
K
Kay, Allen M 已提交
3953
{
3954 3955
	struct dmar_domain *dmar_domain = domain->priv;
	struct pci_dev *pdev = to_pci_dev(dev);
3956 3957
	struct intel_iommu *iommu;
	int addr_width;
3958 3959 3960 3961 3962 3963 3964

	/* normally pdev is not mapped */
	if (unlikely(domain_context_mapped(pdev))) {
		struct dmar_domain *old_domain;

		old_domain = find_domain(pdev);
		if (old_domain) {
3965 3966 3967
			if (dmar_domain->flags & DOMAIN_FLAG_VIRTUAL_MACHINE ||
			    dmar_domain->flags & DOMAIN_FLAG_STATIC_IDENTITY)
				domain_remove_one_dev_info(old_domain, pdev);
3968 3969 3970 3971 3972
			else
				domain_remove_dev_info(old_domain);
		}
	}

3973 3974
	iommu = device_to_iommu(pci_domain_nr(pdev->bus), pdev->bus->number,
				pdev->devfn);
3975 3976 3977 3978 3979
	if (!iommu)
		return -ENODEV;

	/* check if this iommu agaw is sufficient for max mapped address */
	addr_width = agaw_to_width(iommu->agaw);
3980 3981 3982 3983 3984
	if (addr_width > cap_mgaw(iommu->cap))
		addr_width = cap_mgaw(iommu->cap);

	if (dmar_domain->max_addr > (1LL << addr_width)) {
		printk(KERN_ERR "%s: iommu width (%d) is not "
3985
		       "sufficient for the mapped address (%llx)\n",
3986
		       __func__, addr_width, dmar_domain->max_addr);
3987 3988
		return -EFAULT;
	}
3989 3990 3991 3992 3993 3994 3995 3996 3997 3998
	dmar_domain->gaw = addr_width;

	/*
	 * Knock out extra levels of page tables if necessary
	 */
	while (iommu->agaw < dmar_domain->agaw) {
		struct dma_pte *pte;

		pte = dmar_domain->pgd;
		if (dma_pte_present(pte)) {
3999 4000
			dmar_domain->pgd = (struct dma_pte *)
				phys_to_virt(dma_pte_addr(pte));
4001
			free_pgtable_page(pte);
4002 4003 4004
		}
		dmar_domain->agaw--;
	}
4005

4006
	return domain_add_dev_info(dmar_domain, pdev, CONTEXT_TT_MULTI_LEVEL);
K
Kay, Allen M 已提交
4007 4008
}

4009 4010
static void intel_iommu_detach_device(struct iommu_domain *domain,
				      struct device *dev)
K
Kay, Allen M 已提交
4011
{
4012 4013 4014
	struct dmar_domain *dmar_domain = domain->priv;
	struct pci_dev *pdev = to_pci_dev(dev);

4015
	domain_remove_one_dev_info(dmar_domain, pdev);
4016
}
4017

4018 4019
static int intel_iommu_map(struct iommu_domain *domain,
			   unsigned long iova, phys_addr_t hpa,
4020
			   size_t size, int iommu_prot)
4021
{
4022
	struct dmar_domain *dmar_domain = domain->priv;
4023
	u64 max_addr;
4024
	int prot = 0;
4025
	int ret;
4026

4027 4028 4029 4030
	if (iommu_prot & IOMMU_READ)
		prot |= DMA_PTE_READ;
	if (iommu_prot & IOMMU_WRITE)
		prot |= DMA_PTE_WRITE;
4031 4032
	if ((iommu_prot & IOMMU_CACHE) && dmar_domain->iommu_snooping)
		prot |= DMA_PTE_SNP;
4033

4034
	max_addr = iova + size;
4035
	if (dmar_domain->max_addr < max_addr) {
4036 4037 4038
		u64 end;

		/* check if minimum agaw is sufficient for mapped address */
4039
		end = __DOMAIN_MAX_ADDR(dmar_domain->gaw) + 1;
4040
		if (end < max_addr) {
4041
			printk(KERN_ERR "%s: iommu width (%d) is not "
4042
			       "sufficient for the mapped address (%llx)\n",
4043
			       __func__, dmar_domain->gaw, max_addr);
4044 4045
			return -EFAULT;
		}
4046
		dmar_domain->max_addr = max_addr;
4047
	}
4048 4049
	/* Round up size to next multiple of PAGE_SIZE, if it and
	   the low bits of hpa would take us onto the next page */
4050
	size = aligned_nrpages(hpa, size);
4051 4052
	ret = domain_pfn_mapping(dmar_domain, iova >> VTD_PAGE_SHIFT,
				 hpa >> VTD_PAGE_SHIFT, size, prot);
4053
	return ret;
K
Kay, Allen M 已提交
4054 4055
}

4056 4057
static size_t intel_iommu_unmap(struct iommu_domain *domain,
			     unsigned long iova, size_t size)
K
Kay, Allen M 已提交
4058
{
4059
	struct dmar_domain *dmar_domain = domain->priv;
4060
	int order;
4061

4062
	order = dma_pte_clear_range(dmar_domain, iova >> VTD_PAGE_SHIFT,
4063
			    (iova + size - 1) >> VTD_PAGE_SHIFT);
4064

4065 4066
	if (dmar_domain->max_addr == iova + size)
		dmar_domain->max_addr = iova;
4067

4068
	return PAGE_SIZE << order;
K
Kay, Allen M 已提交
4069 4070
}

4071 4072
static phys_addr_t intel_iommu_iova_to_phys(struct iommu_domain *domain,
					    unsigned long iova)
K
Kay, Allen M 已提交
4073
{
4074
	struct dmar_domain *dmar_domain = domain->priv;
K
Kay, Allen M 已提交
4075
	struct dma_pte *pte;
4076
	u64 phys = 0;
K
Kay, Allen M 已提交
4077

4078
	pte = pfn_to_dma_pte(dmar_domain, iova >> VTD_PAGE_SHIFT, 0);
K
Kay, Allen M 已提交
4079
	if (pte)
4080
		phys = dma_pte_addr(pte);
K
Kay, Allen M 已提交
4081

4082
	return phys;
K
Kay, Allen M 已提交
4083
}
4084

S
Sheng Yang 已提交
4085 4086 4087 4088 4089 4090 4091
static int intel_iommu_domain_has_cap(struct iommu_domain *domain,
				      unsigned long cap)
{
	struct dmar_domain *dmar_domain = domain->priv;

	if (cap == IOMMU_CAP_CACHE_COHERENCY)
		return dmar_domain->iommu_snooping;
4092
	if (cap == IOMMU_CAP_INTR_REMAP)
4093
		return irq_remapping_enabled;
S
Sheng Yang 已提交
4094 4095 4096 4097

	return 0;
}

4098
static void swap_pci_ref(struct pci_dev **from, struct pci_dev *to)
4099
{
4100 4101 4102
	pci_dev_put(*from);
	*from = to;
}
4103

4104
#define REQ_ACS_FLAGS	(PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF)
4105

4106 4107 4108 4109 4110 4111
static int intel_iommu_add_device(struct device *dev)
{
	struct pci_dev *pdev = to_pci_dev(dev);
	struct pci_dev *bridge, *dma_pdev;
	struct iommu_group *group;
	int ret;
4112

4113 4114
	if (!device_to_iommu(pci_domain_nr(pdev->bus),
			     pdev->bus->number, pdev->devfn))
4115 4116 4117 4118
		return -ENODEV;

	bridge = pci_find_upstream_pcie_bridge(pdev);
	if (bridge) {
4119 4120 4121 4122 4123 4124 4125 4126 4127
		if (pci_is_pcie(bridge))
			dma_pdev = pci_get_domain_bus_and_slot(
						pci_domain_nr(pdev->bus),
						bridge->subordinate->number, 0);
		else
			dma_pdev = pci_dev_get(bridge);
	} else
		dma_pdev = pci_dev_get(pdev);

4128 4129 4130 4131 4132 4133 4134 4135 4136 4137 4138 4139 4140 4141 4142 4143 4144
	swap_pci_ref(&dma_pdev, pci_get_dma_source(dma_pdev));

	if (dma_pdev->multifunction &&
	    !pci_acs_enabled(dma_pdev, REQ_ACS_FLAGS))
		swap_pci_ref(&dma_pdev,
			     pci_get_slot(dma_pdev->bus,
					  PCI_DEVFN(PCI_SLOT(dma_pdev->devfn),
					  0)));

	while (!pci_is_root_bus(dma_pdev->bus)) {
		if (pci_acs_path_enabled(dma_pdev->bus->self,
					 NULL, REQ_ACS_FLAGS))
			break;

		swap_pci_ref(&dma_pdev, pci_dev_get(dma_pdev->bus->self));
	}

4145 4146 4147 4148 4149 4150
	group = iommu_group_get(&dma_pdev->dev);
	pci_dev_put(dma_pdev);
	if (!group) {
		group = iommu_group_alloc();
		if (IS_ERR(group))
			return PTR_ERR(group);
4151 4152
	}

4153
	ret = iommu_group_add_device(group, dev);
4154

4155 4156 4157
	iommu_group_put(group);
	return ret;
}
4158

4159 4160 4161
static void intel_iommu_remove_device(struct device *dev)
{
	iommu_group_remove_device(dev);
4162 4163
}

4164 4165 4166 4167 4168
static struct iommu_ops intel_iommu_ops = {
	.domain_init	= intel_iommu_domain_init,
	.domain_destroy = intel_iommu_domain_destroy,
	.attach_dev	= intel_iommu_attach_device,
	.detach_dev	= intel_iommu_detach_device,
4169 4170
	.map		= intel_iommu_map,
	.unmap		= intel_iommu_unmap,
4171
	.iova_to_phys	= intel_iommu_iova_to_phys,
S
Sheng Yang 已提交
4172
	.domain_has_cap = intel_iommu_domain_has_cap,
4173 4174
	.add_device	= intel_iommu_add_device,
	.remove_device	= intel_iommu_remove_device,
4175
	.pgsize_bitmap	= INTEL_IOMMU_PGSIZES,
4176
};
4177 4178 4179 4180 4181 4182 4183 4184 4185

static void __devinit quirk_iommu_rwbf(struct pci_dev *dev)
{
	/*
	 * Mobile 4 Series Chipset neglects to set RWBF capability,
	 * but needs it:
	 */
	printk(KERN_INFO "DMAR: Forcing write-buffer flush capability\n");
	rwbf_quirk = 1;
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	/* https://bugzilla.redhat.com/show_bug.cgi?id=538163 */
	if (dev->revision == 0x07) {
		printk(KERN_INFO "DMAR: Disabling IOMMU for graphics on this chipset\n");
		dmar_map_gfx = 0;
	}
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}

DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2a40, quirk_iommu_rwbf);
4195

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#define GGC 0x52
#define GGC_MEMORY_SIZE_MASK	(0xf << 8)
#define GGC_MEMORY_SIZE_NONE	(0x0 << 8)
#define GGC_MEMORY_SIZE_1M	(0x1 << 8)
#define GGC_MEMORY_SIZE_2M	(0x3 << 8)
#define GGC_MEMORY_VT_ENABLED	(0x8 << 8)
#define GGC_MEMORY_SIZE_2M_VT	(0x9 << 8)
#define GGC_MEMORY_SIZE_3M_VT	(0xa << 8)
#define GGC_MEMORY_SIZE_4M_VT	(0xb << 8)

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static void __devinit quirk_calpella_no_shadow_gtt(struct pci_dev *dev)
{
	unsigned short ggc;

4210
	if (pci_read_config_word(dev, GGC, &ggc))
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		return;

4213
	if (!(ggc & GGC_MEMORY_VT_ENABLED)) {
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		printk(KERN_INFO "DMAR: BIOS has allocated no shadow GTT; disabling IOMMU for graphics\n");
		dmar_map_gfx = 0;
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	} else if (dmar_map_gfx) {
		/* we have to ensure the gfx device is idle before we flush */
		printk(KERN_INFO "DMAR: Disabling batched IOTLB flush on Ironlake\n");
		intel_iommu_strict = 1;
       }
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}
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0040, quirk_calpella_no_shadow_gtt);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0044, quirk_calpella_no_shadow_gtt);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0062, quirk_calpella_no_shadow_gtt);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x006a, quirk_calpella_no_shadow_gtt);

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/* On Tylersburg chipsets, some BIOSes have been known to enable the
   ISOCH DMAR unit for the Azalia sound device, but not give it any
   TLB entries, which causes it to deadlock. Check for that.  We do
   this in a function called from init_dmars(), instead of in a PCI
   quirk, because we don't want to print the obnoxious "BIOS broken"
   message if VT-d is actually disabled.
*/
static void __init check_tylersburg_isoch(void)
{
	struct pci_dev *pdev;
	uint32_t vtisochctrl;

	/* If there's no Azalia in the system anyway, forget it. */
	pdev = pci_get_device(PCI_VENDOR_ID_INTEL, 0x3a3e, NULL);
	if (!pdev)
		return;
	pci_dev_put(pdev);

	/* System Management Registers. Might be hidden, in which case
	   we can't do the sanity check. But that's OK, because the
	   known-broken BIOSes _don't_ actually hide it, so far. */
	pdev = pci_get_device(PCI_VENDOR_ID_INTEL, 0x342e, NULL);
	if (!pdev)
		return;

	if (pci_read_config_dword(pdev, 0x188, &vtisochctrl)) {
		pci_dev_put(pdev);
		return;
	}

	pci_dev_put(pdev);

	/* If Azalia DMA is routed to the non-isoch DMAR unit, fine. */
	if (vtisochctrl & 1)
		return;

	/* Drop all bits other than the number of TLB entries */
	vtisochctrl &= 0x1c;

	/* If we have the recommended number of TLB entries (16), fine. */
	if (vtisochctrl == 0x10)
		return;

	/* Zero TLB entries? You get to ride the short bus to school. */
	if (!vtisochctrl) {
		WARN(1, "Your BIOS is broken; DMA routed to ISOCH DMAR unit but no TLB space.\n"
		     "BIOS vendor: %s; Ver: %s; Product Version: %s\n",
		     dmi_get_system_info(DMI_BIOS_VENDOR),
		     dmi_get_system_info(DMI_BIOS_VERSION),
		     dmi_get_system_info(DMI_PRODUCT_VERSION));
		iommu_identity_mapping |= IDENTMAP_AZALIA;
		return;
	}
	
	printk(KERN_WARNING "DMAR: Recommended TLB entries for ISOCH unit is 16; your BIOS set %d\n",
	       vtisochctrl);
}