spi-pxa2xx.c 29.9 KB
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/*
 * Copyright (C) 2005 Stephen Street / StreetFire Sound Labs
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
 */

#include <linux/init.h>
#include <linux/module.h>
#include <linux/device.h>
#include <linux/ioport.h>
#include <linux/errno.h>
#include <linux/interrupt.h>
#include <linux/platform_device.h>
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#include <linux/spi/pxa2xx_spi.h>
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#include <linux/spi/spi.h>
#include <linux/workqueue.h>
#include <linux/delay.h>
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#include <linux/gpio.h>
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#include <linux/slab.h>
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#include <linux/clk.h>
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#include <linux/pm_runtime.h>
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#include <asm/io.h>
#include <asm/irq.h>
#include <asm/delay.h>

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#include "spi-pxa2xx.h"
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MODULE_AUTHOR("Stephen Street");
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MODULE_DESCRIPTION("PXA2xx SSP SPI Controller");
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MODULE_LICENSE("GPL");
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MODULE_ALIAS("platform:pxa2xx-spi");
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#define MAX_BUSES 3

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#define TIMOUT_DFLT		1000

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/*
 * for testing SSCR1 changes that require SSP restart, basically
 * everything except the service and interrupt enables, the pxa270 developer
 * manual says only SSCR1_SCFR, SSCR1_SPH, SSCR1_SPO need to be in this
 * list, but the PXA255 dev man says all bits without really meaning the
 * service and interrupt enables
 */
#define SSCR1_CHANGE_MASK (SSCR1_TTELP | SSCR1_TTE | SSCR1_SCFR \
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				| SSCR1_ECRA | SSCR1_ECRB | SSCR1_SCLKDIR \
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				| SSCR1_SFRMDIR | SSCR1_RWOT | SSCR1_TRAIL \
				| SSCR1_IFS | SSCR1_STRF | SSCR1_EFWR \
				| SSCR1_RFT | SSCR1_TFT | SSCR1_MWDS \
				| SSCR1_SPH | SSCR1_SPO | SSCR1_LBM)
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static void cs_assert(struct driver_data *drv_data)
{
	struct chip_data *chip = drv_data->cur_chip;

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	if (drv_data->ssp_type == CE4100_SSP) {
		write_SSSR(drv_data->cur_chip->frm, drv_data->ioaddr);
		return;
	}

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	if (chip->cs_control) {
		chip->cs_control(PXA2XX_CS_ASSERT);
		return;
	}

	if (gpio_is_valid(chip->gpio_cs))
		gpio_set_value(chip->gpio_cs, chip->gpio_cs_inverted);
}

static void cs_deassert(struct driver_data *drv_data)
{
	struct chip_data *chip = drv_data->cur_chip;

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	if (drv_data->ssp_type == CE4100_SSP)
		return;

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	if (chip->cs_control) {
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		chip->cs_control(PXA2XX_CS_DEASSERT);
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		return;
	}

	if (gpio_is_valid(chip->gpio_cs))
		gpio_set_value(chip->gpio_cs, !chip->gpio_cs_inverted);
}

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int pxa2xx_spi_flush(struct driver_data *drv_data)
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{
	unsigned long limit = loops_per_jiffy << 1;

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	void __iomem *reg = drv_data->ioaddr;
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	do {
		while (read_SSSR(reg) & SSSR_RNE) {
			read_SSDR(reg);
		}
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	} while ((read_SSSR(reg) & SSSR_BSY) && --limit);
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	write_SSSR_CS(drv_data, SSSR_ROR);
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	return limit;
}

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static int null_writer(struct driver_data *drv_data)
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{
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	void __iomem *reg = drv_data->ioaddr;
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	u8 n_bytes = drv_data->n_bytes;
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	if (((read_SSSR(reg) & SSSR_TFL_MASK) == SSSR_TFL_MASK)
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		|| (drv_data->tx == drv_data->tx_end))
		return 0;

	write_SSDR(0, reg);
	drv_data->tx += n_bytes;

	return 1;
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}

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static int null_reader(struct driver_data *drv_data)
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{
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	void __iomem *reg = drv_data->ioaddr;
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	u8 n_bytes = drv_data->n_bytes;
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	while ((read_SSSR(reg) & SSSR_RNE)
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		&& (drv_data->rx < drv_data->rx_end)) {
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		read_SSDR(reg);
		drv_data->rx += n_bytes;
	}
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	return drv_data->rx == drv_data->rx_end;
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}

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static int u8_writer(struct driver_data *drv_data)
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{
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	void __iomem *reg = drv_data->ioaddr;
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	if (((read_SSSR(reg) & SSSR_TFL_MASK) == SSSR_TFL_MASK)
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		|| (drv_data->tx == drv_data->tx_end))
		return 0;

	write_SSDR(*(u8 *)(drv_data->tx), reg);
	++drv_data->tx;

	return 1;
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}

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static int u8_reader(struct driver_data *drv_data)
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{
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	void __iomem *reg = drv_data->ioaddr;
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	while ((read_SSSR(reg) & SSSR_RNE)
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		&& (drv_data->rx < drv_data->rx_end)) {
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		*(u8 *)(drv_data->rx) = read_SSDR(reg);
		++drv_data->rx;
	}
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	return drv_data->rx == drv_data->rx_end;
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}

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static int u16_writer(struct driver_data *drv_data)
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{
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	void __iomem *reg = drv_data->ioaddr;
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	if (((read_SSSR(reg) & SSSR_TFL_MASK) == SSSR_TFL_MASK)
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		|| (drv_data->tx == drv_data->tx_end))
		return 0;

	write_SSDR(*(u16 *)(drv_data->tx), reg);
	drv_data->tx += 2;

	return 1;
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}

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static int u16_reader(struct driver_data *drv_data)
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{
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	void __iomem *reg = drv_data->ioaddr;
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	while ((read_SSSR(reg) & SSSR_RNE)
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		&& (drv_data->rx < drv_data->rx_end)) {
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		*(u16 *)(drv_data->rx) = read_SSDR(reg);
		drv_data->rx += 2;
	}
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	return drv_data->rx == drv_data->rx_end;
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}
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static int u32_writer(struct driver_data *drv_data)
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{
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	void __iomem *reg = drv_data->ioaddr;
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	if (((read_SSSR(reg) & SSSR_TFL_MASK) == SSSR_TFL_MASK)
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		|| (drv_data->tx == drv_data->tx_end))
		return 0;

	write_SSDR(*(u32 *)(drv_data->tx), reg);
	drv_data->tx += 4;

	return 1;
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}

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static int u32_reader(struct driver_data *drv_data)
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{
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	void __iomem *reg = drv_data->ioaddr;
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	while ((read_SSSR(reg) & SSSR_RNE)
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		&& (drv_data->rx < drv_data->rx_end)) {
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		*(u32 *)(drv_data->rx) = read_SSDR(reg);
		drv_data->rx += 4;
	}
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	return drv_data->rx == drv_data->rx_end;
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}

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void *pxa2xx_spi_next_transfer(struct driver_data *drv_data)
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{
	struct spi_message *msg = drv_data->cur_msg;
	struct spi_transfer *trans = drv_data->cur_transfer;

	/* Move to next transfer */
	if (trans->transfer_list.next != &msg->transfers) {
		drv_data->cur_transfer =
			list_entry(trans->transfer_list.next,
					struct spi_transfer,
					transfer_list);
		return RUNNING_STATE;
	} else
		return DONE_STATE;
}

/* caller already set message->status; dma and pio irqs are blocked */
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static void giveback(struct driver_data *drv_data)
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{
	struct spi_transfer* last_transfer;
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	struct spi_message *msg;
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	msg = drv_data->cur_msg;
	drv_data->cur_msg = NULL;
	drv_data->cur_transfer = NULL;

	last_transfer = list_entry(msg->transfers.prev,
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					struct spi_transfer,
					transfer_list);

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	/* Delay if requested before any change in chip select */
	if (last_transfer->delay_usecs)
		udelay(last_transfer->delay_usecs);

	/* Drop chip select UNLESS cs_change is true or we are returning
	 * a message with an error, or next message is for another chip
	 */
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	if (!last_transfer->cs_change)
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		cs_deassert(drv_data);
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	else {
		struct spi_message *next_msg;

		/* Holding of cs was hinted, but we need to make sure
		 * the next message is for the same chip.  Don't waste
		 * time with the following tests unless this was hinted.
		 *
		 * We cannot postpone this until pump_messages, because
		 * after calling msg->complete (below) the driver that
		 * sent the current message could be unloaded, which
		 * could invalidate the cs_control() callback...
		 */

		/* get a pointer to the next message, if any */
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		next_msg = spi_get_next_queued_message(drv_data->master);
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		/* see if the next and current messages point
		 * to the same chip
		 */
		if (next_msg && next_msg->spi != msg->spi)
			next_msg = NULL;
		if (!next_msg || msg->state == ERROR_STATE)
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			cs_deassert(drv_data);
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	}
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	spi_finalize_current_message(drv_data->master);
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	drv_data->cur_chip = NULL;
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}

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static void reset_sccr1(struct driver_data *drv_data)
{
	void __iomem *reg = drv_data->ioaddr;
	struct chip_data *chip = drv_data->cur_chip;
	u32 sccr1_reg;

	sccr1_reg = read_SSCR1(reg) & ~drv_data->int_cr1;
	sccr1_reg &= ~SSCR1_RFT;
	sccr1_reg |= chip->threshold;
	write_SSCR1(sccr1_reg, reg);
}

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static void int_error_stop(struct driver_data *drv_data, const char* msg)
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{
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	void __iomem *reg = drv_data->ioaddr;
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	/* Stop and reset SSP */
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	write_SSSR_CS(drv_data, drv_data->clear_sr);
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	reset_sccr1(drv_data);
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	if (!pxa25x_ssp_comp(drv_data))
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		write_SSTO(0, reg);
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	pxa2xx_spi_flush(drv_data);
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	write_SSCR0(read_SSCR0(reg) & ~SSCR0_SSE, reg);
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	dev_err(&drv_data->pdev->dev, "%s\n", msg);
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	drv_data->cur_msg->state = ERROR_STATE;
	tasklet_schedule(&drv_data->pump_transfers);
}
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static void int_transfer_complete(struct driver_data *drv_data)
{
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	void __iomem *reg = drv_data->ioaddr;
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	/* Stop SSP */
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	write_SSSR_CS(drv_data, drv_data->clear_sr);
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	reset_sccr1(drv_data);
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	if (!pxa25x_ssp_comp(drv_data))
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		write_SSTO(0, reg);
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	/* Update total byte transferred return count actual bytes read */
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	drv_data->cur_msg->actual_length += drv_data->len -
				(drv_data->rx_end - drv_data->rx);
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	/* Transfer delays and chip select release are
	 * handled in pump_transfers or giveback
	 */
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	/* Move to next transfer */
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	drv_data->cur_msg->state = pxa2xx_spi_next_transfer(drv_data);
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	/* Schedule transfer tasklet */
	tasklet_schedule(&drv_data->pump_transfers);
}
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static irqreturn_t interrupt_transfer(struct driver_data *drv_data)
{
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	void __iomem *reg = drv_data->ioaddr;
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	u32 irq_mask = (read_SSCR1(reg) & SSCR1_TIE) ?
			drv_data->mask_sr : drv_data->mask_sr & ~SSSR_TFS;
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	u32 irq_status = read_SSSR(reg) & irq_mask;
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	if (irq_status & SSSR_ROR) {
		int_error_stop(drv_data, "interrupt_transfer: fifo overrun");
		return IRQ_HANDLED;
	}
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	if (irq_status & SSSR_TINT) {
		write_SSSR(SSSR_TINT, reg);
		if (drv_data->read(drv_data)) {
			int_transfer_complete(drv_data);
			return IRQ_HANDLED;
		}
	}
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	/* Drain rx fifo, Fill tx fifo and prevent overruns */
	do {
		if (drv_data->read(drv_data)) {
			int_transfer_complete(drv_data);
			return IRQ_HANDLED;
		}
	} while (drv_data->write(drv_data));
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	if (drv_data->read(drv_data)) {
		int_transfer_complete(drv_data);
		return IRQ_HANDLED;
	}
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	if (drv_data->tx == drv_data->tx_end) {
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		u32 bytes_left;
		u32 sccr1_reg;

		sccr1_reg = read_SSCR1(reg);
		sccr1_reg &= ~SSCR1_TIE;

		/*
		 * PXA25x_SSP has no timeout, set up rx threshould for the
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		 * remaining RX bytes.
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		 */
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		if (pxa25x_ssp_comp(drv_data)) {
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			sccr1_reg &= ~SSCR1_RFT;

			bytes_left = drv_data->rx_end - drv_data->rx;
			switch (drv_data->n_bytes) {
			case 4:
				bytes_left >>= 1;
			case 2:
				bytes_left >>= 1;
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			}
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			if (bytes_left > RX_THRESH_DFLT)
				bytes_left = RX_THRESH_DFLT;

			sccr1_reg |= SSCR1_RxTresh(bytes_left);
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		}
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		write_SSCR1(sccr1_reg, reg);
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	}

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	/* We did something */
	return IRQ_HANDLED;
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}

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static irqreturn_t ssp_int(int irq, void *dev_id)
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{
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	struct driver_data *drv_data = dev_id;
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	void __iomem *reg = drv_data->ioaddr;
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	u32 sccr1_reg;
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	u32 mask = drv_data->mask_sr;
	u32 status;

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	/*
	 * The IRQ might be shared with other peripherals so we must first
	 * check that are we RPM suspended or not. If we are we assume that
	 * the IRQ was not for us (we shouldn't be RPM suspended when the
	 * interrupt is enabled).
	 */
	if (pm_runtime_suspended(&drv_data->pdev->dev))
		return IRQ_NONE;

	sccr1_reg = read_SSCR1(reg);
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	status = read_SSSR(reg);

	/* Ignore possible writes if we don't need to write */
	if (!(sccr1_reg & SSCR1_TIE))
		mask &= ~SSSR_TFS;

	if (!(status & mask))
		return IRQ_NONE;
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	if (!drv_data->cur_msg) {
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		write_SSCR0(read_SSCR0(reg) & ~SSCR0_SSE, reg);
		write_SSCR1(read_SSCR1(reg) & ~drv_data->int_cr1, reg);
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		if (!pxa25x_ssp_comp(drv_data))
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			write_SSTO(0, reg);
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		write_SSSR_CS(drv_data, drv_data->clear_sr);
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		dev_err(&drv_data->pdev->dev, "bad message state "
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			"in interrupt handler\n");
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		/* Never fail */
		return IRQ_HANDLED;
	}

	return drv_data->transfer_handler(drv_data);
}

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static unsigned int ssp_get_clk_div(struct driver_data *drv_data, int rate)
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{
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	unsigned long ssp_clk = drv_data->max_clk_rate;
	const struct ssp_device *ssp = drv_data->ssp;

	rate = min_t(int, ssp_clk, rate);
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	if (ssp->type == PXA25x_SSP || ssp->type == CE4100_SSP)
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		return ((ssp_clk / (2 * rate) - 1) & 0xff) << 8;
	else
		return ((ssp_clk / rate - 1) & 0xfff) << 8;
}

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static void pump_transfers(unsigned long data)
{
	struct driver_data *drv_data = (struct driver_data *)data;
	struct spi_message *message = NULL;
	struct spi_transfer *transfer = NULL;
	struct spi_transfer *previous = NULL;
	struct chip_data *chip = NULL;
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	void __iomem *reg = drv_data->ioaddr;
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	u32 clk_div = 0;
	u8 bits = 0;
	u32 speed = 0;
	u32 cr0;
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	u32 cr1;
	u32 dma_thresh = drv_data->cur_chip->dma_threshold;
	u32 dma_burst = drv_data->cur_chip->dma_burst_size;
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	/* Get current state information */
	message = drv_data->cur_msg;
	transfer = drv_data->cur_transfer;
	chip = drv_data->cur_chip;

	/* Handle for abort */
	if (message->state == ERROR_STATE) {
		message->status = -EIO;
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		giveback(drv_data);
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		return;
	}

	/* Handle end of message */
	if (message->state == DONE_STATE) {
		message->status = 0;
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		giveback(drv_data);
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		return;
	}

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	/* Delay if requested at end of transfer before CS change */
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	if (message->state == RUNNING_STATE) {
		previous = list_entry(transfer->transfer_list.prev,
					struct spi_transfer,
					transfer_list);
		if (previous->delay_usecs)
			udelay(previous->delay_usecs);
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		/* Drop chip select only if cs_change is requested */
		if (previous->cs_change)
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			cs_deassert(drv_data);
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	}

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	/* Check if we can DMA this transfer */
	if (!pxa2xx_spi_dma_is_possible(transfer->len) && chip->enable_dma) {
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		/* reject already-mapped transfers; PIO won't always work */
		if (message->is_dma_mapped
				|| transfer->rx_dma || transfer->tx_dma) {
			dev_err(&drv_data->pdev->dev,
				"pump_transfers: mapped transfer length "
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				"of %u is greater than %d\n",
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				transfer->len, MAX_DMA_LEN);
			message->status = -EINVAL;
			giveback(drv_data);
			return;
		}

		/* warn ... we force this to PIO mode */
		if (printk_ratelimit())
			dev_warn(&message->spi->dev, "pump_transfers: "
				"DMA disabled for transfer length %ld "
				"greater than %d\n",
				(long)drv_data->len, MAX_DMA_LEN);
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	}

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	/* Setup the transfer state based on the type of transfer */
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	if (pxa2xx_spi_flush(drv_data) == 0) {
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		dev_err(&drv_data->pdev->dev, "pump_transfers: flush failed\n");
		message->status = -EIO;
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		giveback(drv_data);
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		return;
	}
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	drv_data->n_bytes = chip->n_bytes;
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	drv_data->tx = (void *)transfer->tx_buf;
	drv_data->tx_end = drv_data->tx + transfer->len;
	drv_data->rx = transfer->rx_buf;
	drv_data->rx_end = drv_data->rx + transfer->len;
	drv_data->rx_dma = transfer->rx_dma;
	drv_data->tx_dma = transfer->tx_dma;
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	drv_data->len = transfer->len;
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	drv_data->write = drv_data->tx ? chip->write : null_writer;
	drv_data->read = drv_data->rx ? chip->read : null_reader;
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	/* Change speed and bit per word on a per transfer */
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	cr0 = chip->cr0;
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	if (transfer->speed_hz || transfer->bits_per_word) {

		bits = chip->bits_per_word;
		speed = chip->speed_hz;

		if (transfer->speed_hz)
			speed = transfer->speed_hz;

		if (transfer->bits_per_word)
			bits = transfer->bits_per_word;

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		clk_div = ssp_get_clk_div(drv_data, speed);
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		if (bits <= 8) {
			drv_data->n_bytes = 1;
			drv_data->read = drv_data->read != null_reader ?
						u8_reader : null_reader;
			drv_data->write = drv_data->write != null_writer ?
						u8_writer : null_writer;
		} else if (bits <= 16) {
			drv_data->n_bytes = 2;
			drv_data->read = drv_data->read != null_reader ?
						u16_reader : null_reader;
			drv_data->write = drv_data->write != null_writer ?
						u16_writer : null_writer;
		} else if (bits <= 32) {
			drv_data->n_bytes = 4;
			drv_data->read = drv_data->read != null_reader ?
						u32_reader : null_reader;
			drv_data->write = drv_data->write != null_writer ?
						u32_writer : null_writer;
		}
598 599 600
		/* if bits/word is changed in dma mode, then must check the
		 * thresholds and burst also */
		if (chip->enable_dma) {
601 602
			if (pxa2xx_spi_set_dma_burst_and_threshold(chip,
							message->spi,
603 604 605 606
							bits, &dma_burst,
							&dma_thresh))
				if (printk_ratelimit())
					dev_warn(&message->spi->dev,
N
Ned Forrester 已提交
607
						"pump_transfers: "
608 609 610
						"DMA burst size reduced to "
						"match bits_per_word\n");
		}
611 612 613

		cr0 = clk_div
			| SSCR0_Motorola
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Stephen Street 已提交
614
			| SSCR0_DataSize(bits > 16 ? bits - 16 : bits)
615 616 617 618
			| SSCR0_SSE
			| (bits > 16 ? SSCR0_EDSS : 0);
	}

619 620
	message->state = RUNNING_STATE;

N
Ned Forrester 已提交
621
	drv_data->dma_mapped = 0;
622 623
	if (pxa2xx_spi_dma_is_possible(drv_data->len))
		drv_data->dma_mapped = pxa2xx_spi_map_dma_buffers(drv_data);
N
Ned Forrester 已提交
624
	if (drv_data->dma_mapped) {
625 626

		/* Ensure we have the correct interrupt handler */
627 628 629
		drv_data->transfer_handler = pxa2xx_spi_dma_transfer;

		pxa2xx_spi_dma_prepare(drv_data, dma_burst);
630

631 632
		/* Clear status and start DMA engine */
		cr1 = chip->cr1 | dma_thresh | drv_data->dma_cr1;
633
		write_SSSR(drv_data->clear_sr, reg);
634 635

		pxa2xx_spi_dma_start(drv_data);
636 637 638 639
	} else {
		/* Ensure we have the correct interrupt handler	*/
		drv_data->transfer_handler = interrupt_transfer;

640 641
		/* Clear status  */
		cr1 = chip->cr1 | chip->threshold | drv_data->int_cr1;
642
		write_SSSR_CS(drv_data, drv_data->clear_sr);
643 644 645 646 647 648 649
	}

	/* see if we need to reload the config registers */
	if ((read_SSCR0(reg) != cr0)
		|| (read_SSCR1(reg) & SSCR1_CHANGE_MASK) !=
			(cr1 & SSCR1_CHANGE_MASK)) {

650
		/* stop the SSP, and update the other bits */
651
		write_SSCR0(cr0 & ~SSCR0_SSE, reg);
652
		if (!pxa25x_ssp_comp(drv_data))
653
			write_SSTO(chip->timeout, reg);
654 655 656
		/* first set CR1 without interrupt and service enables */
		write_SSCR1(cr1 & SSCR1_CHANGE_MASK, reg);
		/* restart the SSP */
657
		write_SSCR0(cr0, reg);
658

659
	} else {
660
		if (!pxa25x_ssp_comp(drv_data))
661
			write_SSTO(chip->timeout, reg);
662
	}
663

664
	cs_assert(drv_data);
665 666 667 668

	/* after chip select, release the data by enabling service
	 * requests and interrupts, without changing any mode bits */
	write_SSCR1(cr1, reg);
669 670
}

671 672
static int pxa2xx_spi_transfer_one_message(struct spi_master *master,
					   struct spi_message *msg)
673
{
674
	struct driver_data *drv_data = spi_master_get_devdata(master);
675

676
	drv_data->cur_msg = msg;
677 678 679 680 681 682
	/* Initial message state*/
	drv_data->cur_msg->state = START_STATE;
	drv_data->cur_transfer = list_entry(drv_data->cur_msg->transfers.next,
						struct spi_transfer,
						transfer_list);

683 684
	/* prepare to setup the SSP, in pump_transfers, using the per
	 * chip configuration */
685 686 687 688 689 690 691
	drv_data->cur_chip = spi_get_ctldata(drv_data->cur_msg->spi);

	/* Mark as busy and launch transfers */
	tasklet_schedule(&drv_data->pump_transfers);
	return 0;
}

692 693 694 695 696 697 698 699 700 701 702 703 704 705 706 707 708 709 710 711 712
static int pxa2xx_spi_prepare_transfer(struct spi_master *master)
{
	struct driver_data *drv_data = spi_master_get_devdata(master);

	pm_runtime_get_sync(&drv_data->pdev->dev);
	return 0;
}

static int pxa2xx_spi_unprepare_transfer(struct spi_master *master)
{
	struct driver_data *drv_data = spi_master_get_devdata(master);

	/* Disable the SSP now */
	write_SSCR0(read_SSCR0(drv_data->ioaddr) & ~SSCR0_SSE,
		    drv_data->ioaddr);

	pm_runtime_mark_last_busy(&drv_data->pdev->dev);
	pm_runtime_put_autosuspend(&drv_data->pdev->dev);
	return 0;
}

713 714 715 716 717 718 719 720 721 722 723 724 725 726 727 728 729 730 731 732 733 734 735 736 737 738 739 740 741 742 743 744 745 746 747 748 749 750
static int setup_cs(struct spi_device *spi, struct chip_data *chip,
		    struct pxa2xx_spi_chip *chip_info)
{
	int err = 0;

	if (chip == NULL || chip_info == NULL)
		return 0;

	/* NOTE: setup() can be called multiple times, possibly with
	 * different chip_info, release previously requested GPIO
	 */
	if (gpio_is_valid(chip->gpio_cs))
		gpio_free(chip->gpio_cs);

	/* If (*cs_control) is provided, ignore GPIO chip select */
	if (chip_info->cs_control) {
		chip->cs_control = chip_info->cs_control;
		return 0;
	}

	if (gpio_is_valid(chip_info->gpio_cs)) {
		err = gpio_request(chip_info->gpio_cs, "SPI_CS");
		if (err) {
			dev_err(&spi->dev, "failed to request chip select "
					"GPIO%d\n", chip_info->gpio_cs);
			return err;
		}

		chip->gpio_cs = chip_info->gpio_cs;
		chip->gpio_cs_inverted = spi->mode & SPI_CS_HIGH;

		err = gpio_direction_output(chip->gpio_cs,
					!chip->gpio_cs_inverted);
	}

	return err;
}

751 752 753 754 755 756
static int setup(struct spi_device *spi)
{
	struct pxa2xx_spi_chip *chip_info = NULL;
	struct chip_data *chip;
	struct driver_data *drv_data = spi_master_get_devdata(spi->master);
	unsigned int clk_div;
757 758
	uint tx_thres = TX_THRESH_DFLT;
	uint rx_thres = RX_THRESH_DFLT;
759

760
	if (!pxa25x_ssp_comp(drv_data)
761 762 763 764
		&& (spi->bits_per_word < 4 || spi->bits_per_word > 32)) {
		dev_err(&spi->dev, "failed setup: ssp_type=%d, bits/wrd=%d "
				"b/w not 4-32 for type non-PXA25x_SSP\n",
				drv_data->ssp_type, spi->bits_per_word);
765
		return -EINVAL;
766
	} else if (pxa25x_ssp_comp(drv_data)
767 768 769 770 771
			&& (spi->bits_per_word < 4
				|| spi->bits_per_word > 16)) {
		dev_err(&spi->dev, "failed setup: ssp_type=%d, bits/wrd=%d "
				"b/w not 4-16 for type PXA25x_SSP\n",
				drv_data->ssp_type, spi->bits_per_word);
772
		return -EINVAL;
773
	}
774

775
	/* Only alloc on first setup */
776
	chip = spi_get_ctldata(spi);
777
	if (!chip) {
778
		chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL);
779 780 781
		if (!chip) {
			dev_err(&spi->dev,
				"failed setup: can't allocate chip data\n");
782
			return -ENOMEM;
783
		}
784

785 786 787 788 789 790 791 792 793 794 795
		if (drv_data->ssp_type == CE4100_SSP) {
			if (spi->chip_select > 4) {
				dev_err(&spi->dev, "failed setup: "
				"cs number must not be > 4.\n");
				kfree(chip);
				return -EINVAL;
			}

			chip->frm = spi->chip_select;
		} else
			chip->gpio_cs = -1;
796
		chip->enable_dma = 0;
797
		chip->timeout = TIMOUT_DFLT;
798 799
	}

800 801 802 803
	/* protocol drivers may change the chip settings, so...
	 * if chip_info exists, use it */
	chip_info = spi->controller_data;

804
	/* chip_info isn't always needed */
805
	chip->cr1 = 0;
806
	if (chip_info) {
807 808 809 810 811 812 813
		if (chip_info->timeout)
			chip->timeout = chip_info->timeout;
		if (chip_info->tx_threshold)
			tx_thres = chip_info->tx_threshold;
		if (chip_info->rx_threshold)
			rx_thres = chip_info->rx_threshold;
		chip->enable_dma = drv_data->master_info->enable_dma;
814 815 816 817 818
		chip->dma_threshold = 0;
		if (chip_info->enable_loopback)
			chip->cr1 = SSCR1_LBM;
	}

819 820 821
	chip->threshold = (SSCR1_RxTresh(rx_thres) & SSCR1_RFT) |
			(SSCR1_TxTresh(tx_thres) & SSCR1_TFT);

822 823 824 825 826
	/* set dma burst and threshold outside of chip_info path so that if
	 * chip_info goes away after setting chip->enable_dma, the
	 * burst and threshold can still respond to changes in bits_per_word */
	if (chip->enable_dma) {
		/* set up legal burst and threshold for dma */
827 828
		if (pxa2xx_spi_set_dma_burst_and_threshold(chip, spi,
						spi->bits_per_word,
829 830 831 832 833 834 835
						&chip->dma_burst_size,
						&chip->dma_threshold)) {
			dev_warn(&spi->dev, "in setup: DMA burst size reduced "
					"to match bits_per_word\n");
		}
	}

836
	clk_div = ssp_get_clk_div(drv_data, spi->max_speed_hz);
837
	chip->speed_hz = spi->max_speed_hz;
838 839 840

	chip->cr0 = clk_div
			| SSCR0_Motorola
S
Stephen Street 已提交
841 842
			| SSCR0_DataSize(spi->bits_per_word > 16 ?
				spi->bits_per_word - 16 : spi->bits_per_word)
843 844
			| SSCR0_SSE
			| (spi->bits_per_word > 16 ? SSCR0_EDSS : 0);
845 846 847
	chip->cr1 &= ~(SSCR1_SPO | SSCR1_SPH);
	chip->cr1 |= (((spi->mode & SPI_CPHA) != 0) ? SSCR1_SPH : 0)
			| (((spi->mode & SPI_CPOL) != 0) ? SSCR1_SPO : 0);
848

849 850 851
	if (spi->mode & SPI_LOOP)
		chip->cr1 |= SSCR1_LBM;

852
	/* NOTE:  PXA25x_SSP _could_ use external clocking ... */
853
	if (!pxa25x_ssp_comp(drv_data))
854
		dev_dbg(&spi->dev, "%ld Hz actual, %s\n",
855
			drv_data->max_clk_rate
856 857
				/ (1 + ((chip->cr0 & SSCR0_SCR(0xfff)) >> 8)),
			chip->enable_dma ? "DMA" : "PIO");
858
	else
859
		dev_dbg(&spi->dev, "%ld Hz actual, %s\n",
860
			drv_data->max_clk_rate / 2
861 862
				/ (1 + ((chip->cr0 & SSCR0_SCR(0x0ff)) >> 8)),
			chip->enable_dma ? "DMA" : "PIO");
863 864 865 866 867 868 869 870 871 872 873 874 875 876 877 878 879 880

	if (spi->bits_per_word <= 8) {
		chip->n_bytes = 1;
		chip->read = u8_reader;
		chip->write = u8_writer;
	} else if (spi->bits_per_word <= 16) {
		chip->n_bytes = 2;
		chip->read = u16_reader;
		chip->write = u16_writer;
	} else if (spi->bits_per_word <= 32) {
		chip->cr0 |= SSCR0_EDSS;
		chip->n_bytes = 4;
		chip->read = u32_reader;
		chip->write = u32_writer;
	} else {
		dev_err(&spi->dev, "invalid wordsize\n");
		return -ENODEV;
	}
881
	chip->bits_per_word = spi->bits_per_word;
882 883 884

	spi_set_ctldata(spi, chip);

885 886 887
	if (drv_data->ssp_type == CE4100_SSP)
		return 0;

888
	return setup_cs(spi, chip, chip_info);
889 890
}

891
static void cleanup(struct spi_device *spi)
892
{
893
	struct chip_data *chip = spi_get_ctldata(spi);
894
	struct driver_data *drv_data = spi_master_get_devdata(spi->master);
895

896 897 898
	if (!chip)
		return;

899
	if (drv_data->ssp_type != CE4100_SSP && gpio_is_valid(chip->gpio_cs))
900 901
		gpio_free(chip->gpio_cs);

902 903 904
	kfree(chip);
}

905
static int pxa2xx_spi_probe(struct platform_device *pdev)
906 907 908 909
{
	struct device *dev = &pdev->dev;
	struct pxa2xx_spi_master *platform_info;
	struct spi_master *master;
G
Guennadi Liakhovetski 已提交
910
	struct driver_data *drv_data;
911
	struct ssp_device *ssp;
G
Guennadi Liakhovetski 已提交
912
	int status;
913

914 915 916 917 918
	platform_info = dev_get_platdata(dev);
	if (!platform_info) {
		dev_err(&pdev->dev, "missing platform data\n");
		return -ENODEV;
	}
919

H
Haojian Zhuang 已提交
920
	ssp = pxa_ssp_request(pdev->id, pdev->name);
921 922 923 924 925
	if (!ssp)
		ssp = &platform_info->ssp;

	if (!ssp->mmio_base) {
		dev_err(&pdev->dev, "failed to get ssp\n");
926 927 928 929 930 931
		return -ENODEV;
	}

	/* Allocate master with space for drv_data and null dma buffer */
	master = spi_alloc_master(dev, sizeof(struct driver_data) + 16);
	if (!master) {
G
Guennadi Liakhovetski 已提交
932
		dev_err(&pdev->dev, "cannot alloc spi_master\n");
H
Haojian Zhuang 已提交
933
		pxa_ssp_free(ssp);
934 935 936 937 938 939
		return -ENOMEM;
	}
	drv_data = spi_master_get_devdata(master);
	drv_data->master = master;
	drv_data->master_info = platform_info;
	drv_data->pdev = pdev;
940
	drv_data->ssp = ssp;
941

942 943
	master->dev.parent = &pdev->dev;
	master->dev.of_node = pdev->dev.of_node;
944
	/* the spi->mode bits understood by this driver: */
945
	master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LOOP;
946

947
	master->bus_num = ssp->port_id;
948
	master->num_chipselect = platform_info->num_chipselect;
949
	master->dma_alignment = DMA_ALIGNMENT;
950 951
	master->cleanup = cleanup;
	master->setup = setup;
952
	master->transfer_one_message = pxa2xx_spi_transfer_one_message;
953 954
	master->prepare_transfer_hardware = pxa2xx_spi_prepare_transfer;
	master->unprepare_transfer_hardware = pxa2xx_spi_unprepare_transfer;
955

956
	drv_data->ssp_type = ssp->type;
957
	drv_data->null_dma_buf = (u32 *)PTR_ALIGN(&drv_data[1], DMA_ALIGNMENT);
958

959 960
	drv_data->ioaddr = ssp->mmio_base;
	drv_data->ssdr_physical = ssp->phys_base + SSDR;
961
	if (pxa25x_ssp_comp(drv_data)) {
962 963 964 965 966 967
		drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE;
		drv_data->dma_cr1 = 0;
		drv_data->clear_sr = SSSR_ROR;
		drv_data->mask_sr = SSSR_RFS | SSSR_TFS | SSSR_ROR;
	} else {
		drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE | SSCR1_TINTE;
968
		drv_data->dma_cr1 = DEFAULT_DMA_CR1;
969 970 971 972
		drv_data->clear_sr = SSSR_ROR | SSSR_TINT;
		drv_data->mask_sr = SSSR_TINT | SSSR_RFS | SSSR_TFS | SSSR_ROR;
	}

973 974
	status = request_irq(ssp->irq, ssp_int, IRQF_SHARED, dev_name(dev),
			drv_data);
975
	if (status < 0) {
G
Guennadi Liakhovetski 已提交
976
		dev_err(&pdev->dev, "cannot get IRQ %d\n", ssp->irq);
977 978 979 980 981 982 983
		goto out_error_master_alloc;
	}

	/* Setup DMA if requested */
	drv_data->tx_channel = -1;
	drv_data->rx_channel = -1;
	if (platform_info->enable_dma) {
984 985 986 987
		status = pxa2xx_spi_dma_setup(drv_data);
		if (status) {
			dev_warn(dev, "failed to setup DMA, using PIO\n");
			platform_info->enable_dma = false;
988 989 990 991
		}
	}

	/* Enable SOC clock */
992 993 994
	clk_prepare_enable(ssp->clk);

	drv_data->max_clk_rate = clk_get_rate(ssp->clk);
995 996 997

	/* Load default SSP configuration */
	write_SSCR0(0, drv_data->ioaddr);
998 999 1000
	write_SSCR1(SSCR1_RxTresh(RX_THRESH_DFLT) |
				SSCR1_TxTresh(TX_THRESH_DFLT),
				drv_data->ioaddr);
1001
	write_SSCR0(SSCR0_SCR(2)
1002 1003 1004
			| SSCR0_Motorola
			| SSCR0_DataSize(8),
			drv_data->ioaddr);
1005
	if (!pxa25x_ssp_comp(drv_data))
1006 1007 1008
		write_SSTO(0, drv_data->ioaddr);
	write_SSPSP(0, drv_data->ioaddr);

1009 1010
	tasklet_init(&drv_data->pump_transfers, pump_transfers,
		     (unsigned long)drv_data);
1011 1012 1013 1014 1015 1016

	/* Register with the SPI framework */
	platform_set_drvdata(pdev, drv_data);
	status = spi_register_master(master);
	if (status != 0) {
		dev_err(&pdev->dev, "problem registering spi master\n");
1017
		goto out_error_clock_enabled;
1018 1019
	}

1020 1021 1022 1023 1024
	pm_runtime_set_autosuspend_delay(&pdev->dev, 50);
	pm_runtime_use_autosuspend(&pdev->dev);
	pm_runtime_set_active(&pdev->dev);
	pm_runtime_enable(&pdev->dev);

1025 1026 1027
	return status;

out_error_clock_enabled:
1028
	clk_disable_unprepare(ssp->clk);
1029
	pxa2xx_spi_dma_release(drv_data);
1030
	free_irq(ssp->irq, drv_data);
1031 1032 1033

out_error_master_alloc:
	spi_master_put(master);
H
Haojian Zhuang 已提交
1034
	pxa_ssp_free(ssp);
1035 1036 1037 1038 1039 1040
	return status;
}

static int pxa2xx_spi_remove(struct platform_device *pdev)
{
	struct driver_data *drv_data = platform_get_drvdata(pdev);
1041
	struct ssp_device *ssp;
1042 1043 1044

	if (!drv_data)
		return 0;
1045
	ssp = drv_data->ssp;
1046

1047 1048
	pm_runtime_get_sync(&pdev->dev);

1049 1050
	/* Disable the SSP at the peripheral and SOC level */
	write_SSCR0(0, drv_data->ioaddr);
1051
	clk_disable_unprepare(ssp->clk);
1052 1053

	/* Release DMA */
1054 1055
	if (drv_data->master_info->enable_dma)
		pxa2xx_spi_dma_release(drv_data);
1056

1057 1058 1059
	pm_runtime_put_noidle(&pdev->dev);
	pm_runtime_disable(&pdev->dev);

1060
	/* Release IRQ */
1061 1062 1063
	free_irq(ssp->irq, drv_data);

	/* Release SSP */
H
Haojian Zhuang 已提交
1064
	pxa_ssp_free(ssp);
1065 1066 1067 1068 1069 1070 1071 1072 1073 1074 1075 1076 1077 1078 1079 1080 1081 1082 1083

	/* Disconnect from the SPI framework */
	spi_unregister_master(drv_data->master);

	/* Prevent double remove */
	platform_set_drvdata(pdev, NULL);

	return 0;
}

static void pxa2xx_spi_shutdown(struct platform_device *pdev)
{
	int status = 0;

	if ((status = pxa2xx_spi_remove(pdev)) != 0)
		dev_err(&pdev->dev, "shutdown failed with %d\n", status);
}

#ifdef CONFIG_PM
1084
static int pxa2xx_spi_suspend(struct device *dev)
1085
{
1086
	struct driver_data *drv_data = dev_get_drvdata(dev);
1087
	struct ssp_device *ssp = drv_data->ssp;
1088 1089
	int status = 0;

1090
	status = spi_master_suspend(drv_data->master);
1091 1092 1093
	if (status != 0)
		return status;
	write_SSCR0(0, drv_data->ioaddr);
1094
	clk_disable_unprepare(ssp->clk);
1095 1096 1097 1098

	return 0;
}

1099
static int pxa2xx_spi_resume(struct device *dev)
1100
{
1101
	struct driver_data *drv_data = dev_get_drvdata(dev);
1102
	struct ssp_device *ssp = drv_data->ssp;
1103 1104
	int status = 0;

1105
	pxa2xx_spi_dma_resume(drv_data);
1106

1107
	/* Enable the SSP clock */
1108
	clk_prepare_enable(ssp->clk);
1109 1110

	/* Start the queue running */
1111
	status = spi_master_resume(drv_data->master);
1112
	if (status != 0) {
1113
		dev_err(dev, "problem starting queue (%d)\n", status);
1114 1115 1116 1117 1118
		return status;
	}

	return 0;
}
1119 1120 1121 1122 1123 1124 1125 1126 1127 1128 1129 1130 1131 1132 1133 1134 1135 1136 1137
#endif

#ifdef CONFIG_PM_RUNTIME
static int pxa2xx_spi_runtime_suspend(struct device *dev)
{
	struct driver_data *drv_data = dev_get_drvdata(dev);

	clk_disable_unprepare(drv_data->ssp->clk);
	return 0;
}

static int pxa2xx_spi_runtime_resume(struct device *dev)
{
	struct driver_data *drv_data = dev_get_drvdata(dev);

	clk_prepare_enable(drv_data->ssp->clk);
	return 0;
}
#endif
1138

1139
static const struct dev_pm_ops pxa2xx_spi_pm_ops = {
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	SET_SYSTEM_SLEEP_PM_OPS(pxa2xx_spi_suspend, pxa2xx_spi_resume)
	SET_RUNTIME_PM_OPS(pxa2xx_spi_runtime_suspend,
			   pxa2xx_spi_runtime_resume, NULL)
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};
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static struct platform_driver driver = {
	.driver = {
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		.name	= "pxa2xx-spi",
		.owner	= THIS_MODULE,
		.pm	= &pxa2xx_spi_pm_ops,
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	},
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	.probe = pxa2xx_spi_probe,
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	.remove = pxa2xx_spi_remove,
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	.shutdown = pxa2xx_spi_shutdown,
};

static int __init pxa2xx_spi_init(void)
{
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	return platform_driver_register(&driver);
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}
A
Antonio Ospite 已提交
1160
subsys_initcall(pxa2xx_spi_init);
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static void __exit pxa2xx_spi_exit(void)
{
	platform_driver_unregister(&driver);
}
module_exit(pxa2xx_spi_exit);