ahci.c 37.9 KB
Newer Older
L
Linus Torvalds 已提交
1 2 3
/*
 *  ahci.c - AHCI SATA support
 *
4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29
 *  Maintained by:  Jeff Garzik <jgarzik@pobox.com>
 *    		    Please ALWAYS copy linux-ide@vger.kernel.org
 *		    on emails.
 *
 *  Copyright 2004-2005 Red Hat, Inc.
 *
 *
 *  This program is free software; you can redistribute it and/or modify
 *  it under the terms of the GNU General Public License as published by
 *  the Free Software Foundation; either version 2, or (at your option)
 *  any later version.
 *
 *  This program is distributed in the hope that it will be useful,
 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *  GNU General Public License for more details.
 *
 *  You should have received a copy of the GNU General Public License
 *  along with this program; see the file COPYING.  If not, write to
 *  the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
 *
 *
 * libata documentation is available via 'make {ps|pdf}docs',
 * as Documentation/DocBook/libata.*
 *
 * AHCI hardware documentation:
L
Linus Torvalds 已提交
30
 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
31
 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
L
Linus Torvalds 已提交
32 33 34 35 36 37 38 39 40 41
 *
 */

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/blkdev.h>
#include <linux/delay.h>
#include <linux/interrupt.h>
42
#include <linux/dma-mapping.h>
43
#include <linux/device.h>
44
#include <linux/dmi.h>
45
#include <linux/gfp.h>
L
Linus Torvalds 已提交
46
#include <scsi/scsi_host.h>
47
#include <scsi/scsi_cmnd.h>
L
Linus Torvalds 已提交
48
#include <linux/libata.h>
49
#include "ahci.h"
L
Linus Torvalds 已提交
50 51

#define DRV_NAME	"ahci"
T
Tejun Heo 已提交
52
#define DRV_VERSION	"3.0"
L
Linus Torvalds 已提交
53 54 55

enum {
	AHCI_PCI_BAR		= 5,
T
Tejun Heo 已提交
56 57 58 59 60 61 62
};

enum board_ids {
	/* board IDs by feature in alphabetical order */
	board_ahci,
	board_ahci_ign_iferr,
	board_ahci_nosntf,
L
Linus Torvalds 已提交
63

T
Tejun Heo 已提交
64 65
	/* board IDs for specific chipsets in alphabetical order */
	board_ahci_mcp65,
66 67
	board_ahci_mcp77,
	board_ahci_mcp89,
T
Tejun Heo 已提交
68 69 70 71 72 73 74 75 76
	board_ahci_mv,
	board_ahci_sb600,
	board_ahci_sb700,	/* for SB700 and SB800 */
	board_ahci_vt8251,

	/* aliases */
	board_ahci_mcp_linux	= board_ahci_mcp65,
	board_ahci_mcp67	= board_ahci_mcp65,
	board_ahci_mcp73	= board_ahci_mcp65,
77
	board_ahci_mcp79	= board_ahci_mcp77,
L
Linus Torvalds 已提交
78 79
};

80
static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
81 82
static int ahci_sb600_softreset(struct ata_link *link, unsigned int *class,
			  unsigned long deadline);
83 84 85 86
static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
				 unsigned long deadline);
static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
				unsigned long deadline);
87
#ifdef CONFIG_PM
88 89
static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
static int ahci_pci_device_resume(struct pci_dev *pdev);
90
#endif
91

92 93
static struct ata_port_operations ahci_vt8251_ops = {
	.inherits		= &ahci_ops,
94
	.hardreset		= ahci_vt8251_hardreset,
95
};
96

97 98
static struct ata_port_operations ahci_p5wdh_ops = {
	.inherits		= &ahci_ops,
99
	.hardreset		= ahci_p5wdh_hardreset,
100 101
};

102 103 104 105 106 107
static struct ata_port_operations ahci_sb600_ops = {
	.inherits		= &ahci_ops,
	.softreset		= ahci_sb600_softreset,
	.pmp_softreset		= ahci_sb600_softreset,
};

108 109
#define AHCI_HFLAGS(flags)	.private_data	= (void *)(flags)

110
static const struct ata_port_info ahci_port_info[] = {
T
Tejun Heo 已提交
111
	/* by features */
112
	[board_ahci] =
L
Linus Torvalds 已提交
113
	{
T
Tejun Heo 已提交
114
		.flags		= AHCI_FLAG_COMMON,
115
		.pio_mask	= ATA_PIO4,
116
		.udma_mask	= ATA_UDMA6,
L
Linus Torvalds 已提交
117 118
		.port_ops	= &ahci_ops,
	},
T
Tejun Heo 已提交
119
	[board_ahci_ign_iferr] =
120
	{
T
Tejun Heo 已提交
121
		AHCI_HFLAGS	(AHCI_HFLAG_IGN_IRQ_IF_ERR),
122
		.flags		= AHCI_FLAG_COMMON,
123
		.pio_mask	= ATA_PIO4,
124
		.udma_mask	= ATA_UDMA6,
T
Tejun Heo 已提交
125
		.port_ops	= &ahci_ops,
126
	},
T
Tejun Heo 已提交
127
	[board_ahci_nosntf] =
128
	{
T
Tejun Heo 已提交
129
		AHCI_HFLAGS	(AHCI_HFLAG_NO_SNTF),
130
		.flags		= AHCI_FLAG_COMMON,
131
		.pio_mask	= ATA_PIO4,
132
		.udma_mask	= ATA_UDMA6,
133 134
		.port_ops	= &ahci_ops,
	},
T
Tejun Heo 已提交
135 136
	/* by chipsets */
	[board_ahci_mcp65] =
137
	{
138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155
		AHCI_HFLAGS	(AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP |
				 AHCI_HFLAG_YES_NCQ),
		.flags		= AHCI_FLAG_COMMON,
		.pio_mask	= ATA_PIO4,
		.udma_mask	= ATA_UDMA6,
		.port_ops	= &ahci_ops,
	},
	[board_ahci_mcp77] =
	{
		AHCI_HFLAGS	(AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP),
		.flags		= AHCI_FLAG_COMMON,
		.pio_mask	= ATA_PIO4,
		.udma_mask	= ATA_UDMA6,
		.port_ops	= &ahci_ops,
	},
	[board_ahci_mcp89] =
	{
		AHCI_HFLAGS	(AHCI_HFLAG_NO_FPDMA_AA),
156
		.flags		= AHCI_FLAG_COMMON,
157
		.pio_mask	= ATA_PIO4,
158
		.udma_mask	= ATA_UDMA6,
T
Tejun Heo 已提交
159
		.port_ops	= &ahci_ops,
160
	},
161
	[board_ahci_mv] =
162
	{
163
		AHCI_HFLAGS	(AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI |
T
Tejun Heo 已提交
164
				 AHCI_HFLAG_MV_PATA | AHCI_HFLAG_NO_PMP),
165
		.flags		= ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
166
				  ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA,
167
		.pio_mask	= ATA_PIO4,
168 169 170
		.udma_mask	= ATA_UDMA6,
		.port_ops	= &ahci_ops,
	},
T
Tejun Heo 已提交
171
	[board_ahci_sb600] =
172
	{
T
Tejun Heo 已提交
173 174 175
		AHCI_HFLAGS	(AHCI_HFLAG_IGN_SERR_INTERNAL |
				 AHCI_HFLAG_NO_MSI | AHCI_HFLAG_SECT255 |
				 AHCI_HFLAG_32BIT_ONLY),
176
		.flags		= AHCI_FLAG_COMMON,
177
		.pio_mask	= ATA_PIO4,
178
		.udma_mask	= ATA_UDMA6,
179
		.port_ops	= &ahci_sb600_ops,
180
	},
T
Tejun Heo 已提交
181
	[board_ahci_sb700] =	/* for SB700 and SB800 */
182
	{
T
Tejun Heo 已提交
183
		AHCI_HFLAGS	(AHCI_HFLAG_IGN_SERR_INTERNAL),
184 185 186
		.flags		= AHCI_FLAG_COMMON,
		.pio_mask	= ATA_PIO4,
		.udma_mask	= ATA_UDMA6,
T
Tejun Heo 已提交
187
		.port_ops	= &ahci_sb600_ops,
188
	},
T
Tejun Heo 已提交
189
	[board_ahci_vt8251] =
190
	{
T
Tejun Heo 已提交
191
		AHCI_HFLAGS	(AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_PMP),
192 193 194
		.flags		= AHCI_FLAG_COMMON,
		.pio_mask	= ATA_PIO4,
		.udma_mask	= ATA_UDMA6,
T
Tejun Heo 已提交
195
		.port_ops	= &ahci_vt8251_ops,
196
	},
L
Linus Torvalds 已提交
197 198
};

199
static const struct pci_device_id ahci_pci_tbl[] = {
J
Jeff Garzik 已提交
200
	/* Intel */
201 202 203 204 205
	{ PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */
	{ PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */
	{ PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */
	{ PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */
	{ PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */
206
	{ PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */
207 208 209 210
	{ PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */
	{ PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */
	{ PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */
	{ PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */
T
Tejun Heo 已提交
211
	{ PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */
212
	{ PCI_VDEVICE(INTEL, 0x2822), board_ahci_nosntf }, /* ICH8 */
T
Tejun Heo 已提交
213 214 215 216 217 218 219 220 221 222 223 224 225 226 227
	{ PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */
	{ PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */
	{ PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */
	{ PCI_VDEVICE(INTEL, 0x2922), board_ahci }, /* ICH9 */
	{ PCI_VDEVICE(INTEL, 0x2923), board_ahci }, /* ICH9 */
	{ PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */
	{ PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */
	{ PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */
	{ PCI_VDEVICE(INTEL, 0x2929), board_ahci }, /* ICH9M */
	{ PCI_VDEVICE(INTEL, 0x292a), board_ahci }, /* ICH9M */
	{ PCI_VDEVICE(INTEL, 0x292b), board_ahci }, /* ICH9M */
	{ PCI_VDEVICE(INTEL, 0x292c), board_ahci }, /* ICH9M */
	{ PCI_VDEVICE(INTEL, 0x292f), board_ahci }, /* ICH9M */
	{ PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */
	{ PCI_VDEVICE(INTEL, 0x294e), board_ahci }, /* ICH9M */
228 229
	{ PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */
	{ PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */
230
	{ PCI_VDEVICE(INTEL, 0x3a05), board_ahci }, /* ICH10 */
231
	{ PCI_VDEVICE(INTEL, 0x3a22), board_ahci }, /* ICH10 */
232
	{ PCI_VDEVICE(INTEL, 0x3a25), board_ahci }, /* ICH10 */
233 234
	{ PCI_VDEVICE(INTEL, 0x3b22), board_ahci }, /* PCH AHCI */
	{ PCI_VDEVICE(INTEL, 0x3b23), board_ahci }, /* PCH AHCI */
235
	{ PCI_VDEVICE(INTEL, 0x3b24), board_ahci }, /* PCH RAID */
236
	{ PCI_VDEVICE(INTEL, 0x3b25), board_ahci }, /* PCH RAID */
237
	{ PCI_VDEVICE(INTEL, 0x3b29), board_ahci }, /* PCH AHCI */
238
	{ PCI_VDEVICE(INTEL, 0x3b2b), board_ahci }, /* PCH RAID */
239
	{ PCI_VDEVICE(INTEL, 0x3b2c), board_ahci }, /* PCH RAID */
240
	{ PCI_VDEVICE(INTEL, 0x3b2f), board_ahci }, /* PCH AHCI */
241 242 243 244 245 246
	{ PCI_VDEVICE(INTEL, 0x1c02), board_ahci }, /* CPT AHCI */
	{ PCI_VDEVICE(INTEL, 0x1c03), board_ahci }, /* CPT AHCI */
	{ PCI_VDEVICE(INTEL, 0x1c04), board_ahci }, /* CPT RAID */
	{ PCI_VDEVICE(INTEL, 0x1c05), board_ahci }, /* CPT RAID */
	{ PCI_VDEVICE(INTEL, 0x1c06), board_ahci }, /* CPT RAID */
	{ PCI_VDEVICE(INTEL, 0x1c07), board_ahci }, /* CPT RAID */
J
Jeff Garzik 已提交
247

248 249 250
	/* JMicron 360/1/3/5/6, match class to avoid IDE function */
	{ PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
	  PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr },
J
Jeff Garzik 已提交
251 252

	/* ATI */
253
	{ PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */
254 255 256 257 258 259
	{ PCI_VDEVICE(ATI, 0x4390), board_ahci_sb700 }, /* ATI SB700/800 */
	{ PCI_VDEVICE(ATI, 0x4391), board_ahci_sb700 }, /* ATI SB700/800 */
	{ PCI_VDEVICE(ATI, 0x4392), board_ahci_sb700 }, /* ATI SB700/800 */
	{ PCI_VDEVICE(ATI, 0x4393), board_ahci_sb700 }, /* ATI SB700/800 */
	{ PCI_VDEVICE(ATI, 0x4394), board_ahci_sb700 }, /* ATI SB700/800 */
	{ PCI_VDEVICE(ATI, 0x4395), board_ahci_sb700 }, /* ATI SB700/800 */
J
Jeff Garzik 已提交
260

261
	/* AMD */
262
	{ PCI_VDEVICE(AMD, 0x7800), board_ahci }, /* AMD Hudson-2 */
263 264 265 266
	/* AMD is using RAID class only for ahci controllers */
	{ PCI_VENDOR_ID_AMD, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
	  PCI_CLASS_STORAGE_RAID << 8, 0xffffff, board_ahci },

J
Jeff Garzik 已提交
267
	/* VIA */
268
	{ PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */
T
Tejun Heo 已提交
269
	{ PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */
J
Jeff Garzik 已提交
270 271

	/* NVIDIA */
T
Tejun Heo 已提交
272 273 274 275 276 277 278 279
	{ PCI_VDEVICE(NVIDIA, 0x044c), board_ahci_mcp65 },	/* MCP65 */
	{ PCI_VDEVICE(NVIDIA, 0x044d), board_ahci_mcp65 },	/* MCP65 */
	{ PCI_VDEVICE(NVIDIA, 0x044e), board_ahci_mcp65 },	/* MCP65 */
	{ PCI_VDEVICE(NVIDIA, 0x044f), board_ahci_mcp65 },	/* MCP65 */
	{ PCI_VDEVICE(NVIDIA, 0x045c), board_ahci_mcp65 },	/* MCP65 */
	{ PCI_VDEVICE(NVIDIA, 0x045d), board_ahci_mcp65 },	/* MCP65 */
	{ PCI_VDEVICE(NVIDIA, 0x045e), board_ahci_mcp65 },	/* MCP65 */
	{ PCI_VDEVICE(NVIDIA, 0x045f), board_ahci_mcp65 },	/* MCP65 */
T
Tejun Heo 已提交
280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355
	{ PCI_VDEVICE(NVIDIA, 0x0550), board_ahci_mcp67 },	/* MCP67 */
	{ PCI_VDEVICE(NVIDIA, 0x0551), board_ahci_mcp67 },	/* MCP67 */
	{ PCI_VDEVICE(NVIDIA, 0x0552), board_ahci_mcp67 },	/* MCP67 */
	{ PCI_VDEVICE(NVIDIA, 0x0553), board_ahci_mcp67 },	/* MCP67 */
	{ PCI_VDEVICE(NVIDIA, 0x0554), board_ahci_mcp67 },	/* MCP67 */
	{ PCI_VDEVICE(NVIDIA, 0x0555), board_ahci_mcp67 },	/* MCP67 */
	{ PCI_VDEVICE(NVIDIA, 0x0556), board_ahci_mcp67 },	/* MCP67 */
	{ PCI_VDEVICE(NVIDIA, 0x0557), board_ahci_mcp67 },	/* MCP67 */
	{ PCI_VDEVICE(NVIDIA, 0x0558), board_ahci_mcp67 },	/* MCP67 */
	{ PCI_VDEVICE(NVIDIA, 0x0559), board_ahci_mcp67 },	/* MCP67 */
	{ PCI_VDEVICE(NVIDIA, 0x055a), board_ahci_mcp67 },	/* MCP67 */
	{ PCI_VDEVICE(NVIDIA, 0x055b), board_ahci_mcp67 },	/* MCP67 */
	{ PCI_VDEVICE(NVIDIA, 0x0580), board_ahci_mcp_linux },	/* Linux ID */
	{ PCI_VDEVICE(NVIDIA, 0x0581), board_ahci_mcp_linux },	/* Linux ID */
	{ PCI_VDEVICE(NVIDIA, 0x0582), board_ahci_mcp_linux },	/* Linux ID */
	{ PCI_VDEVICE(NVIDIA, 0x0583), board_ahci_mcp_linux },	/* Linux ID */
	{ PCI_VDEVICE(NVIDIA, 0x0584), board_ahci_mcp_linux },	/* Linux ID */
	{ PCI_VDEVICE(NVIDIA, 0x0585), board_ahci_mcp_linux },	/* Linux ID */
	{ PCI_VDEVICE(NVIDIA, 0x0586), board_ahci_mcp_linux },	/* Linux ID */
	{ PCI_VDEVICE(NVIDIA, 0x0587), board_ahci_mcp_linux },	/* Linux ID */
	{ PCI_VDEVICE(NVIDIA, 0x0588), board_ahci_mcp_linux },	/* Linux ID */
	{ PCI_VDEVICE(NVIDIA, 0x0589), board_ahci_mcp_linux },	/* Linux ID */
	{ PCI_VDEVICE(NVIDIA, 0x058a), board_ahci_mcp_linux },	/* Linux ID */
	{ PCI_VDEVICE(NVIDIA, 0x058b), board_ahci_mcp_linux },	/* Linux ID */
	{ PCI_VDEVICE(NVIDIA, 0x058c), board_ahci_mcp_linux },	/* Linux ID */
	{ PCI_VDEVICE(NVIDIA, 0x058d), board_ahci_mcp_linux },	/* Linux ID */
	{ PCI_VDEVICE(NVIDIA, 0x058e), board_ahci_mcp_linux },	/* Linux ID */
	{ PCI_VDEVICE(NVIDIA, 0x058f), board_ahci_mcp_linux },	/* Linux ID */
	{ PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci_mcp73 },	/* MCP73 */
	{ PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci_mcp73 },	/* MCP73 */
	{ PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci_mcp73 },	/* MCP73 */
	{ PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci_mcp73 },	/* MCP73 */
	{ PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci_mcp73 },	/* MCP73 */
	{ PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci_mcp73 },	/* MCP73 */
	{ PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci_mcp73 },	/* MCP73 */
	{ PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci_mcp73 },	/* MCP73 */
	{ PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci_mcp73 },	/* MCP73 */
	{ PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci_mcp73 },	/* MCP73 */
	{ PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci_mcp73 },	/* MCP73 */
	{ PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci_mcp73 },	/* MCP73 */
	{ PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci_mcp77 },	/* MCP77 */
	{ PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci_mcp77 },	/* MCP77 */
	{ PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci_mcp77 },	/* MCP77 */
	{ PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci_mcp77 },	/* MCP77 */
	{ PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci_mcp77 },	/* MCP77 */
	{ PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci_mcp77 },	/* MCP77 */
	{ PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci_mcp77 },	/* MCP77 */
	{ PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci_mcp77 },	/* MCP77 */
	{ PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci_mcp77 },	/* MCP77 */
	{ PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci_mcp77 },	/* MCP77 */
	{ PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci_mcp77 },	/* MCP77 */
	{ PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci_mcp77 },	/* MCP77 */
	{ PCI_VDEVICE(NVIDIA, 0x0ab4), board_ahci_mcp79 },	/* MCP79 */
	{ PCI_VDEVICE(NVIDIA, 0x0ab5), board_ahci_mcp79 },	/* MCP79 */
	{ PCI_VDEVICE(NVIDIA, 0x0ab6), board_ahci_mcp79 },	/* MCP79 */
	{ PCI_VDEVICE(NVIDIA, 0x0ab7), board_ahci_mcp79 },	/* MCP79 */
	{ PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci_mcp79 },	/* MCP79 */
	{ PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci_mcp79 },	/* MCP79 */
	{ PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci_mcp79 },	/* MCP79 */
	{ PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci_mcp79 },	/* MCP79 */
	{ PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci_mcp79 },	/* MCP79 */
	{ PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci_mcp79 },	/* MCP79 */
	{ PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci_mcp79 },	/* MCP79 */
	{ PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci_mcp79 },	/* MCP79 */
	{ PCI_VDEVICE(NVIDIA, 0x0d84), board_ahci_mcp89 },	/* MCP89 */
	{ PCI_VDEVICE(NVIDIA, 0x0d85), board_ahci_mcp89 },	/* MCP89 */
	{ PCI_VDEVICE(NVIDIA, 0x0d86), board_ahci_mcp89 },	/* MCP89 */
	{ PCI_VDEVICE(NVIDIA, 0x0d87), board_ahci_mcp89 },	/* MCP89 */
	{ PCI_VDEVICE(NVIDIA, 0x0d88), board_ahci_mcp89 },	/* MCP89 */
	{ PCI_VDEVICE(NVIDIA, 0x0d89), board_ahci_mcp89 },	/* MCP89 */
	{ PCI_VDEVICE(NVIDIA, 0x0d8a), board_ahci_mcp89 },	/* MCP89 */
	{ PCI_VDEVICE(NVIDIA, 0x0d8b), board_ahci_mcp89 },	/* MCP89 */
	{ PCI_VDEVICE(NVIDIA, 0x0d8c), board_ahci_mcp89 },	/* MCP89 */
	{ PCI_VDEVICE(NVIDIA, 0x0d8d), board_ahci_mcp89 },	/* MCP89 */
	{ PCI_VDEVICE(NVIDIA, 0x0d8e), board_ahci_mcp89 },	/* MCP89 */
	{ PCI_VDEVICE(NVIDIA, 0x0d8f), board_ahci_mcp89 },	/* MCP89 */
J
Jeff Garzik 已提交
356

J
Jeff Garzik 已提交
357
	/* SiS */
358 359 360
	{ PCI_VDEVICE(SI, 0x1184), board_ahci },		/* SiS 966 */
	{ PCI_VDEVICE(SI, 0x1185), board_ahci },		/* SiS 968 */
	{ PCI_VDEVICE(SI, 0x0186), board_ahci },		/* SiS 968 */
J
Jeff Garzik 已提交
361

362 363
	/* Marvell */
	{ PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv },	/* 6145 */
364
	{ PCI_VDEVICE(MARVELL, 0x6121), board_ahci_mv },	/* 6121 */
365

366 367 368
	/* Promise */
	{ PCI_VDEVICE(PROMISE, 0x3f20), board_ahci },	/* PDC42819 */

369 370
	/* Generic, PCI class code for AHCI */
	{ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
371
	  PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci },
372

L
Linus Torvalds 已提交
373 374 375 376 377 378 379 380
	{ }	/* terminate list */
};


static struct pci_driver ahci_pci_driver = {
	.name			= DRV_NAME,
	.id_table		= ahci_pci_tbl,
	.probe			= ahci_init_one,
381
	.remove			= ata_pci_remove_one,
382
#ifdef CONFIG_PM
383
	.suspend		= ahci_pci_device_suspend,
384 385 386
	.resume			= ahci_pci_device_resume,
#endif
};
L
Linus Torvalds 已提交
387

388 389 390 391 392 393 394
#if defined(CONFIG_PATA_MARVELL) || defined(CONFIG_PATA_MARVELL_MODULE)
static int marvell_enable;
#else
static int marvell_enable = 1;
#endif
module_param(marvell_enable, int, 0644);
MODULE_PARM_DESC(marvell_enable, "Marvell SATA via AHCI (1 = enabled)");
395

L
Linus Torvalds 已提交
396

397 398 399 400 401
static void ahci_pci_save_initial_config(struct pci_dev *pdev,
					 struct ahci_host_priv *hpriv)
{
	unsigned int force_port_map = 0;
	unsigned int mask_port_map = 0;
402

403 404 405
	if (pdev->vendor == PCI_VENDOR_ID_JMICRON && pdev->device == 0x2361) {
		dev_info(&pdev->dev, "JMB361 has only one port\n");
		force_port_map = 1;
L
Linus Torvalds 已提交
406 407
	}

408 409 410 411
	/*
	 * Temporary Marvell 6145 hack: PATA port presence
	 * is asserted through the standard AHCI port
	 * presence register, as bit 4 (counting from 0)
412
	 */
413 414 415 416 417 418 419 420
	if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
		if (pdev->device == 0x6121)
			mask_port_map = 0x3;
		else
			mask_port_map = 0xf;
		dev_info(&pdev->dev,
			  "Disabling your PATA port. Use the boot option 'ahci.marvell_enable=0' to avoid this.\n");
	}
L
Linus Torvalds 已提交
421

422 423
	ahci_save_initial_config(&pdev->dev, hpriv, force_port_map,
				 mask_port_map);
L
Linus Torvalds 已提交
424 425
}

426
static int ahci_pci_reset_controller(struct ata_host *host)
L
Linus Torvalds 已提交
427
{
428
	struct pci_dev *pdev = to_pci_dev(host->dev);
T
Tejun Heo 已提交
429

430
	ahci_reset_controller(host);
L
Linus Torvalds 已提交
431

432 433 434
	if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
		struct ahci_host_priv *hpriv = host->private_data;
		u16 tmp16;
435

436 437 438 439 440 441
		/* configure PCS */
		pci_read_config_word(pdev, 0x92, &tmp16);
		if ((tmp16 & hpriv->port_map) != hpriv->port_map) {
			tmp16 |= hpriv->port_map;
			pci_write_config_word(pdev, 0x92, tmp16);
		}
442 443
	}

L
Linus Torvalds 已提交
444 445 446
	return 0;
}

447
static void ahci_pci_init_controller(struct ata_host *host)
T
Tejun Heo 已提交
448
{
449 450 451
	struct ahci_host_priv *hpriv = host->private_data;
	struct pci_dev *pdev = to_pci_dev(host->dev);
	void __iomem *port_mmio;
T
Tejun Heo 已提交
452
	u32 tmp;
453
	int mv;
T
Tejun Heo 已提交
454

455 456 457 458 459 460
	if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
		if (pdev->device == 0x6121)
			mv = 2;
		else
			mv = 4;
		port_mmio = __ahci_port_base(host, mv);
T
Tejun Heo 已提交
461

462
		writel(0, port_mmio + PORT_IRQ_MASK);
T
Tejun Heo 已提交
463

464 465 466 467 468
		/* clear port IRQ */
		tmp = readl(port_mmio + PORT_IRQ_STAT);
		VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
		if (tmp)
			writel(tmp, port_mmio + PORT_IRQ_STAT);
T
Tejun Heo 已提交
469 470
	}

471
	ahci_init_controller(host);
472 473
}

474
static int ahci_sb600_check_ready(struct ata_link *link)
T
Tejun Heo 已提交
475
{
476 477 478 479 480 481 482 483 484 485
	void __iomem *port_mmio = ahci_port_base(link->ap);
	u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
	u32 irq_status = readl(port_mmio + PORT_IRQ_STAT);

	/*
	 * There is no need to check TFDATA if BAD PMP is found due to HW bug,
	 * which can save timeout delay.
	 */
	if (irq_status & PORT_IRQ_BAD_PMP)
		return -EIO;
T
Tejun Heo 已提交
486

487
	return ata_check_ready(status);
T
Tejun Heo 已提交
488 489
}

490 491
static int ahci_sb600_softreset(struct ata_link *link, unsigned int *class,
				unsigned long deadline)
492
{
493
	struct ata_port *ap = link->ap;
494
	void __iomem *port_mmio = ahci_port_base(ap);
495
	int pmp = sata_srst_pmp(link);
496
	int rc;
497
	u32 irq_sts;
498

499
	DPRINTK("ENTER\n");
500

501 502
	rc = ahci_do_softreset(link, class, pmp, deadline,
			       ahci_sb600_check_ready);
503

504 505 506 507 508 509 510 511 512 513 514 515 516 517 518
	/*
	 * Soft reset fails on some ATI chips with IPMS set when PMP
	 * is enabled but SATA HDD/ODD is connected to SATA port,
	 * do soft reset again to port 0.
	 */
	if (rc == -EIO) {
		irq_sts = readl(port_mmio + PORT_IRQ_STAT);
		if (irq_sts & PORT_IRQ_BAD_PMP) {
			ata_link_printk(link, KERN_WARNING,
					"applying SB600 PMP SRST workaround "
					"and retrying\n");
			rc = ahci_do_softreset(link, class, 0, deadline,
					       ahci_check_ready);
		}
	}
519

520
	return rc;
521 522
}

523 524
static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
				 unsigned long deadline)
525
{
526 527
	struct ata_port *ap = link->ap;
	bool online;
528 529
	int rc;

530
	DPRINTK("ENTER\n");
531

532
	ahci_stop_engine(ap);
533

534 535
	rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
				 deadline, &online, NULL);
536 537 538

	ahci_start_engine(ap);

539
	DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
540

541 542 543 544
	/* vt8251 doesn't clear BSY on signature FIS reception,
	 * request follow-up softreset.
	 */
	return online ? -EAGAIN : rc;
T
Tejun Heo 已提交
545 546
}

547 548
static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
				unsigned long deadline)
T
Tejun Heo 已提交
549
{
550
	struct ata_port *ap = link->ap;
551
	struct ahci_port_priv *pp = ap->private_data;
552 553 554 555
	u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
	struct ata_taskfile tf;
	bool online;
	int rc;
T
Tejun Heo 已提交
556

557
	ahci_stop_engine(ap);
558

559 560 561 562
	/* clear D2H reception area to properly wait for D2H FIS */
	ata_tf_init(link->device, &tf);
	tf.command = 0x80;
	ata_tf_to_fis(&tf, 0, 0, d2h_fis);
T
Tejun Heo 已提交
563

564 565
	rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
				 deadline, &online, NULL);
566

567
	ahci_start_engine(ap);
568

569 570 571 572 573 574 575 576 577 578 579 580 581 582 583 584 585 586
	/* The pseudo configuration device on SIMG4726 attached to
	 * ASUS P5W-DH Deluxe doesn't send signature FIS after
	 * hardreset if no device is attached to the first downstream
	 * port && the pseudo device locks up on SRST w/ PMP==0.  To
	 * work around this, wait for !BSY only briefly.  If BSY isn't
	 * cleared, perform CLO and proceed to IDENTIFY (achieved by
	 * ATA_LFLAG_NO_SRST and ATA_LFLAG_ASSUME_ATA).
	 *
	 * Wait for two seconds.  Devices attached to downstream port
	 * which can't process the following IDENTIFY after this will
	 * have to be reset again.  For most cases, this should
	 * suffice while making probing snappish enough.
	 */
	if (online) {
		rc = ata_wait_after_reset(link, jiffies + 2 * HZ,
					  ahci_check_ready);
		if (rc)
			ahci_kick_engine(ap);
587 588 589 590
	}
	return rc;
}

591
#ifdef CONFIG_PM
592 593
static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
{
J
Jeff Garzik 已提交
594
	struct ata_host *host = dev_get_drvdata(&pdev->dev);
595
	struct ahci_host_priv *hpriv = host->private_data;
596
	void __iomem *mmio = hpriv->mmio;
597 598
	u32 ctl;

599 600 601 602 603 604 605
	if (mesg.event & PM_EVENT_SUSPEND &&
	    hpriv->flags & AHCI_HFLAG_NO_SUSPEND) {
		dev_printk(KERN_ERR, &pdev->dev,
			   "BIOS update required for suspend/resume\n");
		return -EIO;
	}

606
	if (mesg.event & PM_EVENT_SLEEP) {
607 608 609 610 611 612 613 614 615 616 617 618 619 620 621
		/* AHCI spec rev1.1 section 8.3.3:
		 * Software must disable interrupts prior to requesting a
		 * transition of the HBA to D3 state.
		 */
		ctl = readl(mmio + HOST_CTL);
		ctl &= ~HOST_IRQ_EN;
		writel(ctl, mmio + HOST_CTL);
		readl(mmio + HOST_CTL); /* flush */
	}

	return ata_pci_device_suspend(pdev, mesg);
}

static int ahci_pci_device_resume(struct pci_dev *pdev)
{
J
Jeff Garzik 已提交
622
	struct ata_host *host = dev_get_drvdata(&pdev->dev);
623 624
	int rc;

625 626 627
	rc = ata_pci_device_do_resume(pdev);
	if (rc)
		return rc;
628 629

	if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
630
		rc = ahci_pci_reset_controller(host);
631 632 633
		if (rc)
			return rc;

634
		ahci_pci_init_controller(host);
635 636
	}

J
Jeff Garzik 已提交
637
	ata_host_resume(host);
638 639 640

	return 0;
}
641
#endif
642

643
static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac)
L
Linus Torvalds 已提交
644 645 646 647
{
	int rc;

	if (using_dac &&
648 649
	    !pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
		rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
L
Linus Torvalds 已提交
650
		if (rc) {
651
			rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
L
Linus Torvalds 已提交
652
			if (rc) {
653 654
				dev_printk(KERN_ERR, &pdev->dev,
					   "64-bit DMA enable failed\n");
L
Linus Torvalds 已提交
655 656 657 658
				return rc;
			}
		}
	} else {
659
		rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
L
Linus Torvalds 已提交
660
		if (rc) {
661 662
			dev_printk(KERN_ERR, &pdev->dev,
				   "32-bit DMA enable failed\n");
L
Linus Torvalds 已提交
663 664
			return rc;
		}
665
		rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
L
Linus Torvalds 已提交
666
		if (rc) {
667 668
			dev_printk(KERN_ERR, &pdev->dev,
				   "32-bit consistent DMA enable failed\n");
L
Linus Torvalds 已提交
669 670 671 672 673 674
			return rc;
		}
	}
	return 0;
}

675 676 677 678 679 680 681 682 683 684 685 686 687 688 689 690 691 692 693
static void ahci_pci_print_info(struct ata_host *host)
{
	struct pci_dev *pdev = to_pci_dev(host->dev);
	u16 cc;
	const char *scc_s;

	pci_read_config_word(pdev, 0x0a, &cc);
	if (cc == PCI_CLASS_STORAGE_IDE)
		scc_s = "IDE";
	else if (cc == PCI_CLASS_STORAGE_SATA)
		scc_s = "SATA";
	else if (cc == PCI_CLASS_STORAGE_RAID)
		scc_s = "RAID";
	else
		scc_s = "unknown";

	ahci_print_info(host, scc_s);
}

694 695 696 697 698 699 700 701 702 703 704 705 706 707 708 709 710 711 712 713 714 715 716 717 718 719 720 721 722 723 724 725 726 727 728 729 730 731 732 733 734 735 736 737 738
/* On ASUS P5W DH Deluxe, the second port of PCI device 00:1f.2 is
 * hardwired to on-board SIMG 4726.  The chipset is ICH8 and doesn't
 * support PMP and the 4726 either directly exports the device
 * attached to the first downstream port or acts as a hardware storage
 * controller and emulate a single ATA device (can be RAID 0/1 or some
 * other configuration).
 *
 * When there's no device attached to the first downstream port of the
 * 4726, "Config Disk" appears, which is a pseudo ATA device to
 * configure the 4726.  However, ATA emulation of the device is very
 * lame.  It doesn't send signature D2H Reg FIS after the initial
 * hardreset, pukes on SRST w/ PMP==0 and has bunch of other issues.
 *
 * The following function works around the problem by always using
 * hardreset on the port and not depending on receiving signature FIS
 * afterward.  If signature FIS isn't received soon, ATA class is
 * assumed without follow-up softreset.
 */
static void ahci_p5wdh_workaround(struct ata_host *host)
{
	static struct dmi_system_id sysids[] = {
		{
			.ident = "P5W DH Deluxe",
			.matches = {
				DMI_MATCH(DMI_SYS_VENDOR,
					  "ASUSTEK COMPUTER INC"),
				DMI_MATCH(DMI_PRODUCT_NAME, "P5W DH Deluxe"),
			},
		},
		{ }
	};
	struct pci_dev *pdev = to_pci_dev(host->dev);

	if (pdev->bus->number == 0 && pdev->devfn == PCI_DEVFN(0x1f, 2) &&
	    dmi_check_system(sysids)) {
		struct ata_port *ap = host->ports[1];

		dev_printk(KERN_INFO, &pdev->dev, "enabling ASUS P5W DH "
			   "Deluxe on-board SIMG4726 workaround\n");

		ap->ops = &ahci_p5wdh_ops;
		ap->link.flags |= ATA_LFLAG_NO_SRST | ATA_LFLAG_ASSUME_ATA;
	}
}

739 740
/* only some SB600 ahci controllers can do 64bit DMA */
static bool ahci_sb600_enable_64bit(struct pci_dev *pdev)
741 742
{
	static const struct dmi_system_id sysids[] = {
743 744 745
		/*
		 * The oldest version known to be broken is 0901 and
		 * working is 1501 which was released on 2007-10-26.
746 747
		 * Enable 64bit DMA on 1501 and anything newer.
		 *
748 749
		 * Please read bko#9412 for more info.
		 */
750 751 752 753 754 755 756
		{
			.ident = "ASUS M2A-VM",
			.matches = {
				DMI_MATCH(DMI_BOARD_VENDOR,
					  "ASUSTeK Computer INC."),
				DMI_MATCH(DMI_BOARD_NAME, "M2A-VM"),
			},
757
			.driver_data = "20071026",	/* yyyymmdd */
758
		},
759 760 761 762 763 764 765 766 767 768 769 770 771 772 773 774 775 776 777 778 779 780 781 782
		/*
		 * All BIOS versions for the MSI K9A2 Platinum (MS-7376)
		 * support 64bit DMA.
		 *
		 * BIOS versions earlier than 1.5 had the Manufacturer DMI
		 * fields as "MICRO-STAR INTERANTIONAL CO.,LTD".
		 * This spelling mistake was fixed in BIOS version 1.5, so
		 * 1.5 and later have the Manufacturer as
		 * "MICRO-STAR INTERNATIONAL CO.,LTD".
		 * So try to match on DMI_BOARD_VENDOR of "MICRO-STAR INTER".
		 *
		 * BIOS versions earlier than 1.9 had a Board Product Name
		 * DMI field of "MS-7376". This was changed to be
		 * "K9A2 Platinum (MS-7376)" in version 1.9, but we can still
		 * match on DMI_BOARD_NAME of "MS-7376".
		 */
		{
			.ident = "MSI K9A2 Platinum",
			.matches = {
				DMI_MATCH(DMI_BOARD_VENDOR,
					  "MICRO-STAR INTER"),
				DMI_MATCH(DMI_BOARD_NAME, "MS-7376"),
			},
		},
783 784
		{ }
	};
785
	const struct dmi_system_id *match;
786 787
	int year, month, date;
	char buf[9];
788

789
	match = dmi_first_match(sysids);
790
	if (pdev->bus->number != 0 || pdev->devfn != PCI_DEVFN(0x12, 0) ||
791
	    !match)
792 793
		return false;

794 795 796
	if (!match->driver_data)
		goto enable_64bit;

797 798
	dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
	snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
799

800 801 802
	if (strcmp(buf, match->driver_data) >= 0)
		goto enable_64bit;
	else {
803 804
		dev_printk(KERN_WARNING, &pdev->dev, "%s: BIOS too old, "
			   "forcing 32bit DMA, update BIOS\n", match->ident);
805 806
		return false;
	}
807 808 809 810 811

enable_64bit:
	dev_printk(KERN_WARNING, &pdev->dev, "%s: enabling 64bit DMA\n",
		   match->ident);
	return true;
812 813
}

814 815 816 817 818 819 820 821 822 823 824 825
static bool ahci_broken_system_poweroff(struct pci_dev *pdev)
{
	static const struct dmi_system_id broken_systems[] = {
		{
			.ident = "HP Compaq nx6310",
			.matches = {
				DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
				DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nx6310"),
			},
			/* PCI slot number of the controller */
			.driver_data = (void *)0x1FUL,
		},
826 827 828 829 830 831 832 833 834
		{
			.ident = "HP Compaq 6720s",
			.matches = {
				DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
				DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq 6720s"),
			},
			/* PCI slot number of the controller */
			.driver_data = (void *)0x1FUL,
		},
835 836 837 838 839 840 841 842 843 844 845 846 847 848

		{ }	/* terminate list */
	};
	const struct dmi_system_id *dmi = dmi_first_match(broken_systems);

	if (dmi) {
		unsigned long slot = (unsigned long)dmi->driver_data;
		/* apply the quirk only to on-board controllers */
		return slot == PCI_SLOT(pdev->devfn);
	}

	return false;
}

849 850 851 852 853 854 855
static bool ahci_broken_suspend(struct pci_dev *pdev)
{
	static const struct dmi_system_id sysids[] = {
		/*
		 * On HP dv[4-6] and HDX18 with earlier BIOSen, link
		 * to the harddisk doesn't become online after
		 * resuming from STR.  Warn and fail suspend.
856 857 858 859 860 861 862 863
		 *
		 * http://bugzilla.kernel.org/show_bug.cgi?id=12276
		 *
		 * Use dates instead of versions to match as HP is
		 * apparently recycling both product and version
		 * strings.
		 *
		 * http://bugzilla.kernel.org/show_bug.cgi?id=15462
864 865 866 867 868 869 870 871
		 */
		{
			.ident = "dv4",
			.matches = {
				DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
				DMI_MATCH(DMI_PRODUCT_NAME,
					  "HP Pavilion dv4 Notebook PC"),
			},
872
			.driver_data = "20090105",	/* F.30 */
873 874 875 876 877 878 879 880
		},
		{
			.ident = "dv5",
			.matches = {
				DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
				DMI_MATCH(DMI_PRODUCT_NAME,
					  "HP Pavilion dv5 Notebook PC"),
			},
881
			.driver_data = "20090506",	/* F.16 */
882 883 884 885 886 887 888 889
		},
		{
			.ident = "dv6",
			.matches = {
				DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
				DMI_MATCH(DMI_PRODUCT_NAME,
					  "HP Pavilion dv6 Notebook PC"),
			},
890
			.driver_data = "20090423",	/* F.21 */
891 892 893 894 895 896 897 898
		},
		{
			.ident = "HDX18",
			.matches = {
				DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
				DMI_MATCH(DMI_PRODUCT_NAME,
					  "HP HDX18 Notebook PC"),
			},
899
			.driver_data = "20090430",	/* F.23 */
900
		},
901 902 903 904 905 906
		/*
		 * Acer eMachines G725 has the same problem.  BIOS
		 * V1.03 is known to be broken.  V3.04 is known to
		 * work.  Inbetween, there are V1.06, V2.06 and V3.03
		 * that we don't have much idea about.  For now,
		 * blacklist anything older than V3.04.
907 908
		 *
		 * http://bugzilla.kernel.org/show_bug.cgi?id=15104
909 910 911 912 913 914 915
		 */
		{
			.ident = "G725",
			.matches = {
				DMI_MATCH(DMI_SYS_VENDOR, "eMachines"),
				DMI_MATCH(DMI_PRODUCT_NAME, "eMachines G725"),
			},
916
			.driver_data = "20091216",	/* V3.04 */
917
		},
918 919 920
		{ }	/* terminate list */
	};
	const struct dmi_system_id *dmi = dmi_first_match(sysids);
921 922
	int year, month, date;
	char buf[9];
923 924 925 926

	if (!dmi || pdev->bus->number || pdev->devfn != PCI_DEVFN(0x1f, 2))
		return false;

927 928
	dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
	snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
929

930
	return strcmp(buf, dmi->driver_data) < 0;
931 932
}

933 934 935 936 937 938 939 940 941 942 943 944 945 946 947 948 949 950 951 952 953 954 955 956 957 958 959 960 961 962 963 964 965 966 967 968 969 970 971 972 973 974 975 976 977 978 979 980 981 982
static bool ahci_broken_online(struct pci_dev *pdev)
{
#define ENCODE_BUSDEVFN(bus, slot, func)			\
	(void *)(unsigned long)(((bus) << 8) | PCI_DEVFN((slot), (func)))
	static const struct dmi_system_id sysids[] = {
		/*
		 * There are several gigabyte boards which use
		 * SIMG5723s configured as hardware RAID.  Certain
		 * 5723 firmware revisions shipped there keep the link
		 * online but fail to answer properly to SRST or
		 * IDENTIFY when no device is attached downstream
		 * causing libata to retry quite a few times leading
		 * to excessive detection delay.
		 *
		 * As these firmwares respond to the second reset try
		 * with invalid device signature, considering unknown
		 * sig as offline works around the problem acceptably.
		 */
		{
			.ident = "EP45-DQ6",
			.matches = {
				DMI_MATCH(DMI_BOARD_VENDOR,
					  "Gigabyte Technology Co., Ltd."),
				DMI_MATCH(DMI_BOARD_NAME, "EP45-DQ6"),
			},
			.driver_data = ENCODE_BUSDEVFN(0x0a, 0x00, 0),
		},
		{
			.ident = "EP45-DS5",
			.matches = {
				DMI_MATCH(DMI_BOARD_VENDOR,
					  "Gigabyte Technology Co., Ltd."),
				DMI_MATCH(DMI_BOARD_NAME, "EP45-DS5"),
			},
			.driver_data = ENCODE_BUSDEVFN(0x03, 0x00, 0),
		},
		{ }	/* terminate list */
	};
#undef ENCODE_BUSDEVFN
	const struct dmi_system_id *dmi = dmi_first_match(sysids);
	unsigned int val;

	if (!dmi)
		return false;

	val = (unsigned long)dmi->driver_data;

	return pdev->bus->number == (val >> 8) && pdev->devfn == (val & 0xff);
}

983
#ifdef CONFIG_ATA_ACPI
984 985 986 987 988 989 990 991 992 993 994 995 996 997 998 999 1000 1001 1002 1003 1004 1005 1006 1007 1008 1009 1010 1011 1012 1013 1014 1015 1016 1017 1018 1019 1020 1021 1022 1023 1024 1025 1026
static void ahci_gtf_filter_workaround(struct ata_host *host)
{
	static const struct dmi_system_id sysids[] = {
		/*
		 * Aspire 3810T issues a bunch of SATA enable commands
		 * via _GTF including an invalid one and one which is
		 * rejected by the device.  Among the successful ones
		 * is FPDMA non-zero offset enable which when enabled
		 * only on the drive side leads to NCQ command
		 * failures.  Filter it out.
		 */
		{
			.ident = "Aspire 3810T",
			.matches = {
				DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
				DMI_MATCH(DMI_PRODUCT_NAME, "Aspire 3810T"),
			},
			.driver_data = (void *)ATA_ACPI_FILTER_FPDMA_OFFSET,
		},
		{ }
	};
	const struct dmi_system_id *dmi = dmi_first_match(sysids);
	unsigned int filter;
	int i;

	if (!dmi)
		return;

	filter = (unsigned long)dmi->driver_data;
	dev_printk(KERN_INFO, host->dev,
		   "applying extra ACPI _GTF filter 0x%x for %s\n",
		   filter, dmi->ident);

	for (i = 0; i < host->n_ports; i++) {
		struct ata_port *ap = host->ports[i];
		struct ata_link *link;
		struct ata_device *dev;

		ata_for_each_link(link, ap, EDGE)
			ata_for_each_dev(dev, link, ALL)
				dev->gtf_filter |= filter;
	}
}
1027 1028 1029 1030
#else
static inline void ahci_gtf_filter_workaround(struct ata_host *host)
{}
#endif
1031

1032
static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
L
Linus Torvalds 已提交
1033 1034
{
	static int printed_version;
T
Tejun Heo 已提交
1035 1036
	unsigned int board_id = ent->driver_data;
	struct ata_port_info pi = ahci_port_info[board_id];
1037
	const struct ata_port_info *ppi[] = { &pi, NULL };
1038
	struct device *dev = &pdev->dev;
L
Linus Torvalds 已提交
1039
	struct ahci_host_priv *hpriv;
1040
	struct ata_host *host;
T
Tejun Heo 已提交
1041
	int n_ports, i, rc;
L
Linus Torvalds 已提交
1042 1043 1044

	VPRINTK("ENTER\n");

T
Tejun Heo 已提交
1045 1046
	WARN_ON(ATA_MAX_QUEUE > AHCI_MAX_CMDS);

L
Linus Torvalds 已提交
1047
	if (!printed_version++)
1048
		dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
L
Linus Torvalds 已提交
1049

1050 1051 1052 1053 1054 1055
	/* The AHCI driver can only drive the SATA ports, the PATA driver
	   can drive them all so if both drivers are selected make sure
	   AHCI stays out of the way */
	if (pdev->vendor == PCI_VENDOR_ID_MARVELL && !marvell_enable)
		return -ENODEV;

1056 1057 1058 1059 1060 1061 1062 1063 1064 1065
	/*
	 * For some reason, MCP89 on MacBook 7,1 doesn't work with
	 * ahci, use ata_generic instead.
	 */
	if (pdev->vendor == PCI_VENDOR_ID_NVIDIA &&
	    pdev->device == PCI_DEVICE_ID_NVIDIA_NFORCE_MCP89_SATA &&
	    pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE &&
	    pdev->subsystem_device == 0xcb89)
		return -ENODEV;

1066 1067 1068 1069 1070 1071 1072 1073
	/* Promise's PDC42819 is a SAS/SATA controller that has an AHCI mode.
	 * At the moment, we can only use the AHCI mode. Let the users know
	 * that for SAS drives they're out of luck.
	 */
	if (pdev->vendor == PCI_VENDOR_ID_PROMISE)
		dev_printk(KERN_INFO, &pdev->dev, "PDC42819 "
			   "can only drive SATA devices with this driver\n");

1074
	/* acquire resources */
1075
	rc = pcim_enable_device(pdev);
L
Linus Torvalds 已提交
1076 1077 1078
	if (rc)
		return rc;

T
Tejun Heo 已提交
1079 1080 1081 1082
	/* AHCI controllers often implement SFF compatible interface.
	 * Grab all PCI BARs just in case.
	 */
	rc = pcim_iomap_regions_request_all(pdev, 1 << AHCI_PCI_BAR, DRV_NAME);
T
Tejun Heo 已提交
1083
	if (rc == -EBUSY)
1084
		pcim_pin_device(pdev);
T
Tejun Heo 已提交
1085
	if (rc)
1086
		return rc;
L
Linus Torvalds 已提交
1087

1088 1089 1090 1091 1092 1093 1094 1095 1096 1097 1098 1099 1100 1101 1102 1103
	if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
	    (pdev->device == 0x2652 || pdev->device == 0x2653)) {
		u8 map;

		/* ICH6s share the same PCI ID for both piix and ahci
		 * modes.  Enabling ahci mode while MAP indicates
		 * combined mode is a bad idea.  Yield to ata_piix.
		 */
		pci_read_config_byte(pdev, ICH_MAP, &map);
		if (map & 0x3) {
			dev_printk(KERN_INFO, &pdev->dev, "controller is in "
				   "combined mode, can't enable AHCI mode\n");
			return -ENODEV;
		}
	}

1104 1105 1106
	hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
	if (!hpriv)
		return -ENOMEM;
1107 1108
	hpriv->flags |= (unsigned long)pi.private_data;

T
Tejun Heo 已提交
1109 1110 1111 1112 1113
	/* MCP65 revision A1 and A2 can't do MSI */
	if (board_id == board_ahci_mcp65 &&
	    (pdev->revision == 0xa1 || pdev->revision == 0xa2))
		hpriv->flags |= AHCI_HFLAG_NO_MSI;

1114 1115 1116 1117
	/* SB800 does NOT need the workaround to ignore SERR_INTERNAL */
	if (board_id == board_ahci_sb700 && pdev->revision >= 0x40)
		hpriv->flags &= ~AHCI_HFLAG_IGN_SERR_INTERNAL;

1118 1119 1120
	/* only some SB600s can do 64bit DMA */
	if (ahci_sb600_enable_64bit(pdev))
		hpriv->flags &= ~AHCI_HFLAG_32BIT_ONLY;
1121

T
Tejun Heo 已提交
1122 1123
	if ((hpriv->flags & AHCI_HFLAG_NO_MSI) || pci_enable_msi(pdev))
		pci_intx(pdev, 1);
L
Linus Torvalds 已提交
1124

1125 1126
	hpriv->mmio = pcim_iomap_table(pdev)[AHCI_PCI_BAR];

1127
	/* save initial config */
1128
	ahci_pci_save_initial_config(pdev, hpriv);
L
Linus Torvalds 已提交
1129

1130
	/* prepare host */
1131 1132
	if (hpriv->cap & HOST_CAP_NCQ) {
		pi.flags |= ATA_FLAG_NCQ;
1133 1134 1135 1136 1137 1138 1139
		/*
		 * Auto-activate optimization is supposed to be
		 * supported on all AHCI controllers indicating NCQ
		 * capability, but it seems to be broken on some
		 * chipsets including NVIDIAs.
		 */
		if (!(hpriv->flags & AHCI_HFLAG_NO_FPDMA_AA))
1140 1141
			pi.flags |= ATA_FLAG_FPDMA_AA;
	}
L
Linus Torvalds 已提交
1142

T
Tejun Heo 已提交
1143 1144 1145
	if (hpriv->cap & HOST_CAP_PMP)
		pi.flags |= ATA_FLAG_PMP;

1146
	ahci_set_em_messages(hpriv, &pi);
1147

1148 1149 1150 1151 1152 1153
	if (ahci_broken_system_poweroff(pdev)) {
		pi.flags |= ATA_FLAG_NO_POWEROFF_SPINDOWN;
		dev_info(&pdev->dev,
			"quirky BIOS, skipping spindown on poweroff\n");
	}

1154 1155 1156 1157 1158 1159
	if (ahci_broken_suspend(pdev)) {
		hpriv->flags |= AHCI_HFLAG_NO_SUSPEND;
		dev_printk(KERN_WARNING, &pdev->dev,
			   "BIOS update required for suspend/resume\n");
	}

1160 1161 1162 1163 1164 1165
	if (ahci_broken_online(pdev)) {
		hpriv->flags |= AHCI_HFLAG_SRST_TOUT_IS_OFFLINE;
		dev_info(&pdev->dev,
			 "online status unreliable, applying workaround\n");
	}

T
Tejun Heo 已提交
1166 1167 1168 1169 1170 1171 1172 1173
	/* CAP.NP sometimes indicate the index of the last enabled
	 * port, at other times, that of the last possible port, so
	 * determining the maximum port number requires looking at
	 * both CAP.NP and port_map.
	 */
	n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map));

	host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
1174 1175 1176 1177
	if (!host)
		return -ENOMEM;
	host->private_data = hpriv;

1178
	if (!(hpriv->cap & HOST_CAP_SSS) || ahci_ignore_sss)
1179
		host->flags |= ATA_HOST_PARALLEL_SCAN;
1180 1181
	else
		printk(KERN_INFO "ahci: SSS flag set, parallel bus scan disabled\n");
1182

1183 1184 1185
	if (pi.flags & ATA_FLAG_EM)
		ahci_reset_em(host);

1186
	for (i = 0; i < host->n_ports; i++) {
1187
		struct ata_port *ap = host->ports[i];
1188

1189 1190 1191 1192
		ata_port_pbar_desc(ap, AHCI_PCI_BAR, -1, "abar");
		ata_port_pbar_desc(ap, AHCI_PCI_BAR,
				   0x100 + ap->port_no * 0x80, "port");

1193 1194 1195
		/* set initial link pm policy */
		ap->pm_policy = NOT_AVAILABLE;

1196 1197
		/* set enclosure management message type */
		if (ap->flags & ATA_FLAG_EM)
H
Harry Zhang 已提交
1198
			ap->em_message_type = hpriv->em_msg_type;
1199 1200


1201
		/* disabled/not-implemented port */
1202
		if (!(hpriv->port_map & (1 << i)))
1203
			ap->ops = &ata_dummy_port_ops;
1204
	}
1205

1206 1207 1208
	/* apply workaround for ASUS P5W DH Deluxe mainboard */
	ahci_p5wdh_workaround(host);

1209 1210 1211
	/* apply gtf filter quirk */
	ahci_gtf_filter_workaround(host);

1212 1213
	/* initialize adapter */
	rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64);
L
Linus Torvalds 已提交
1214
	if (rc)
1215
		return rc;
L
Linus Torvalds 已提交
1216

1217
	rc = ahci_pci_reset_controller(host);
1218 1219
	if (rc)
		return rc;
L
Linus Torvalds 已提交
1220

1221
	ahci_pci_init_controller(host);
1222
	ahci_pci_print_info(host);
L
Linus Torvalds 已提交
1223

1224 1225 1226
	pci_set_master(pdev);
	return ata_host_activate(host, pdev->irq, ahci_interrupt, IRQF_SHARED,
				 &ahci_sht);
1227
}
L
Linus Torvalds 已提交
1228 1229 1230

static int __init ahci_init(void)
{
1231
	return pci_register_driver(&ahci_pci_driver);
L
Linus Torvalds 已提交
1232 1233 1234 1235 1236 1237 1238 1239 1240 1241 1242 1243
}

static void __exit ahci_exit(void)
{
	pci_unregister_driver(&ahci_pci_driver);
}


MODULE_AUTHOR("Jeff Garzik");
MODULE_DESCRIPTION("AHCI SATA low-level driver");
MODULE_LICENSE("GPL");
MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
1244
MODULE_VERSION(DRV_VERSION);
L
Linus Torvalds 已提交
1245 1246 1247

module_init(ahci_init);
module_exit(ahci_exit);