sun4i-a10.dtsi

/*
 * Copyright 2012 Stefan Roese
 * Stefan Roese <sr@denx.de>
 *
 * The code contained herein is licensed under the GNU General Public
 * License. You may obtain a copy of the GNU General Public License
 * Version 2 or later at the following locations:
 *
 * http://www.opensource.org/licenses/gpl-license.html
 * http://www.gnu.org/copyleft/gpl.html
 */

#include "skeleton.dtsi"

#include <dt-bindings/thermal/thermal.h>

#include <dt-bindings/dma/sun4i-a10.h>
#include <dt-bindings/pinctrl/sun4i-a10.h>

/ {
	interrupt-parent = <&intc>;

	aliases {
		ethernet0 = &emac;
		serial0 = &uart0;
		serial1 = &uart1;
		serial2 = &uart2;
		serial3 = &uart3;
		serial4 = &uart4;
		serial5 = &uart5;
		serial6 = &uart6;
		serial7 = &uart7;
	};

	chosen {
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		framebuffer@0 {
			compatible = "allwinner,simple-framebuffer", "simple-framebuffer";
			allwinner,pipeline = "de_be0-lcd0-hdmi";
			clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 43>,
				 <&ahb_gates 44>;
			status = "disabled";
		};

		framebuffer@1 {
			compatible = "allwinner,simple-framebuffer", "simple-framebuffer";
			allwinner,pipeline = "de_fe0-de_be0-lcd0-hdmi";
			clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 43>,
				 <&ahb_gates 44>, <&ahb_gates 46>;
			status = "disabled";
		};

		framebuffer@2 {
			compatible = "allwinner,simple-framebuffer",
				     "simple-framebuffer";
			allwinner,pipeline = "de_fe0-de_be0-lcd0";
			clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 44>,
				 <&ahb_gates 46>;
			status = "disabled";
		};

		framebuffer@3 {
			compatible = "allwinner,simple-framebuffer",
				     "simple-framebuffer";
			allwinner,pipeline = "de_fe0-de_be0-lcd0-tve0";
			clocks = <&pll5 1>, <&ahb_gates 34>, <&ahb_gates 36>,
				 <&ahb_gates 44>, <&ahb_gates 46>;
			status = "disabled";
		};
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;
		cpu0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a8";
			reg = <0x0>;
			clocks = <&cpu>;
			clock-latency = <244144>; /* 8 32k periods */
			operating-points = <
				/* kHz    uV */
				1056000 1500000
				1008000 1400000
				912000  1350000
				864000  1300000
				624000  1250000
				>;
			#cooling-cells = <2>;
			cooling-min-level = <0>;
			cooling-max-level = <4>;
		};
	};

	thermal-zones {
		cpu_thermal {
			/* milliseconds */
			polling-delay-passive = <250>;
			polling-delay = <1000>;
			thermal-sensors = <&rtp>;

			cooling-maps {
				map0 {
					trip = <&cpu_alert0>;
					cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
				};
			};

			trips {
				cpu_alert0: cpu_alert0 {
					/* milliCelsius */
					temperature = <850000>;
					hysteresis = <2000>;
					type = "passive";
				};

				cpu_crit: cpu_crit {
					/* milliCelsius */
					temperature = <100000>;
					hysteresis = <2000>;
					type = "critical";
				};
			};
		};
	};

	memory {
		reg = <0x40000000 0x80000000>;
	};

	clocks {
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		/*
		 * This is a dummy clock, to be used as placeholder on
		 * other mux clocks when a specific parent clock is not
		 * yet implemented. It should be dropped when the driver
		 * is complete.
		 */
		dummy: dummy {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <0>;
		};

		osc24M: clk@01c20050 {
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-a10-osc-clk";
			reg = <0x01c20050 0x4>;
			clock-frequency = <24000000>;
			clock-output-names = "osc24M";
		};

		osc32k: clk@0 {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <32768>;
			clock-output-names = "osc32k";
		};

		pll1: clk@01c20000 {
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-a10-pll1-clk";
			reg = <0x01c20000 0x4>;
			clocks = <&osc24M>;
			clock-output-names = "pll1";
		};

		pll4: clk@01c20018 {
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-a10-pll1-clk";
			reg = <0x01c20018 0x4>;
			clocks = <&osc24M>;
			clock-output-names = "pll4";
		};

		pll5: clk@01c20020 {
			#clock-cells = <1>;
			compatible = "allwinner,sun4i-a10-pll5-clk";
			reg = <0x01c20020 0x4>;
			clocks = <&osc24M>;
			clock-output-names = "pll5_ddr", "pll5_other";
		};

		pll6: clk@01c20028 {
			#clock-cells = <1>;
			compatible = "allwinner,sun4i-a10-pll6-clk";
			reg = <0x01c20028 0x4>;
			clocks = <&osc24M>;
			clock-output-names = "pll6_sata", "pll6_other", "pll6";
		};

		/* dummy is 200M */
		cpu: cpu@01c20054 {
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-a10-cpu-clk";
			reg = <0x01c20054 0x4>;
			clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>;
			clock-output-names = "cpu";
		};

		axi: axi@01c20054 {
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-a10-axi-clk";
			reg = <0x01c20054 0x4>;
			clocks = <&cpu>;
			clock-output-names = "axi";
		};

		axi_gates: clk@01c2005c {
			#clock-cells = <1>;
			compatible = "allwinner,sun4i-a10-axi-gates-clk";
			reg = <0x01c2005c 0x4>;
			clocks = <&axi>;
			clock-output-names = "axi_dram";
		};

		ahb: ahb@01c20054 {
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-a10-ahb-clk";
			reg = <0x01c20054 0x4>;
			clocks = <&axi>;
			clock-output-names = "ahb";
		};

		ahb_gates: clk@01c20060 {
			#clock-cells = <1>;
			compatible = "allwinner,sun4i-a10-ahb-gates-clk";
			reg = <0x01c20060 0x8>;
			clocks = <&ahb>;
			clock-output-names = "ahb_usb0", "ahb_ehci0",
				"ahb_ohci0", "ahb_ehci1", "ahb_ohci1", "ahb_ss",
				"ahb_dma", "ahb_bist", "ahb_mmc0", "ahb_mmc1",
				"ahb_mmc2", "ahb_mmc3", "ahb_ms", "ahb_nand",
				"ahb_sdram", "ahb_ace",	"ahb_emac", "ahb_ts",
				"ahb_spi0", "ahb_spi1", "ahb_spi2", "ahb_spi3",
				"ahb_pata", "ahb_sata", "ahb_gps", "ahb_ve",
				"ahb_tvd", "ahb_tve0", "ahb_tve1", "ahb_lcd0",
				"ahb_lcd1", "ahb_csi0", "ahb_csi1", "ahb_hdmi",
				"ahb_de_be0", "ahb_de_be1", "ahb_de_fe0",
				"ahb_de_fe1", "ahb_mp", "ahb_mali400";
		};

		apb0: apb0@01c20054 {
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-a10-apb0-clk";
			reg = <0x01c20054 0x4>;
			clocks = <&ahb>;
			clock-output-names = "apb0";
		};

		apb0_gates: clk@01c20068 {
			#clock-cells = <1>;
			compatible = "allwinner,sun4i-a10-apb0-gates-clk";
			reg = <0x01c20068 0x4>;
			clocks = <&apb0>;
			clock-output-names = "apb0_codec", "apb0_spdif",
				"apb0_ac97", "apb0_iis", "apb0_pio", "apb0_ir0",
				"apb0_ir1", "apb0_keypad";
		};

		apb1: clk@01c20058 {
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-a10-apb1-clk";
			reg = <0x01c20058 0x4>;
			clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
			clock-output-names = "apb1";
		};

		apb1_gates: clk@01c2006c {
			#clock-cells = <1>;
			compatible = "allwinner,sun4i-a10-apb1-gates-clk";
			reg = <0x01c2006c 0x4>;
			clocks = <&apb1>;
			clock-output-names = "apb1_i2c0", "apb1_i2c1",
				"apb1_i2c2", "apb1_can", "apb1_scr",
				"apb1_ps20", "apb1_ps21", "apb1_uart0",
				"apb1_uart1", "apb1_uart2", "apb1_uart3",
				"apb1_uart4", "apb1_uart5", "apb1_uart6",
				"apb1_uart7";
		};

		nand_clk: clk@01c20080 {
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-a10-mod0-clk";
			reg = <0x01c20080 0x4>;
			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
			clock-output-names = "nand";
		};

		ms_clk: clk@01c20084 {
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-a10-mod0-clk";
			reg = <0x01c20084 0x4>;
			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
			clock-output-names = "ms";
		};

		mmc0_clk: clk@01c20088 {
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-a10-mod0-clk";
			reg = <0x01c20088 0x4>;
			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
			clock-output-names = "mmc0";
		};

		mmc1_clk: clk@01c2008c {
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-a10-mod0-clk";
			reg = <0x01c2008c 0x4>;
			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
			clock-output-names = "mmc1";
		};

		mmc2_clk: clk@01c20090 {
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-a10-mod0-clk";
			reg = <0x01c20090 0x4>;
			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
			clock-output-names = "mmc2";
		};

		mmc3_clk: clk@01c20094 {
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-a10-mod0-clk";
			reg = <0x01c20094 0x4>;
			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
			clock-output-names = "mmc3";
		};

		ts_clk: clk@01c20098 {
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-a10-mod0-clk";
			reg = <0x01c20098 0x4>;
			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
			clock-output-names = "ts";
		};

		ss_clk: clk@01c2009c {
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-a10-mod0-clk";
			reg = <0x01c2009c 0x4>;
			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
			clock-output-names = "ss";
		};

		spi0_clk: clk@01c200a0 {
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-a10-mod0-clk";
			reg = <0x01c200a0 0x4>;
			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
			clock-output-names = "spi0";
		};

		spi1_clk: clk@01c200a4 {
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-a10-mod0-clk";
			reg = <0x01c200a4 0x4>;
			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
			clock-output-names = "spi1";
		};

		spi2_clk: clk@01c200a8 {
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-a10-mod0-clk";
			reg = <0x01c200a8 0x4>;
			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
			clock-output-names = "spi2";
		};

		pata_clk: clk@01c200ac {
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-a10-mod0-clk";
			reg = <0x01c200ac 0x4>;
			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
			clock-output-names = "pata";
		};

		ir0_clk: clk@01c200b0 {
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-a10-mod0-clk";
			reg = <0x01c200b0 0x4>;
			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
			clock-output-names = "ir0";
		};

		ir1_clk: clk@01c200b4 {
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-a10-mod0-clk";
			reg = <0x01c200b4 0x4>;
			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
			clock-output-names = "ir1";
		};

		usb_clk: clk@01c200cc {
			#clock-cells = <1>;
		        #reset-cells = <1>;
			compatible = "allwinner,sun4i-a10-usb-clk";
			reg = <0x01c200cc 0x4>;
			clocks = <&pll6 1>;
			clock-output-names = "usb_ohci0", "usb_ohci1", "usb_phy";
		};

		spi3_clk: clk@01c200d4 {
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-a10-mod0-clk";
			reg = <0x01c200d4 0x4>;
			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
			clock-output-names = "spi3";
		};
	};

	soc@01c00000 {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		dma: dma-controller@01c02000 {
			compatible = "allwinner,sun4i-a10-dma";
			reg = <0x01c02000 0x1000>;
			interrupts = <27>;
			clocks = <&ahb_gates 6>;
			#dma-cells = <2>;
		};

		spi0: spi@01c05000 {
			compatible = "allwinner,sun4i-a10-spi";
			reg = <0x01c05000 0x1000>;
			interrupts = <10>;
			clocks = <&ahb_gates 20>, <&spi0_clk>;
			clock-names = "ahb", "mod";
			dmas = <&dma SUN4I_DMA_DEDICATED 27>,
			       <&dma SUN4I_DMA_DEDICATED 26>;
			dma-names = "rx", "tx";
			status = "disabled";
			#address-cells = <1>;
			#size-cells = <0>;
		};

		spi1: spi@01c06000 {
			compatible = "allwinner,sun4i-a10-spi";
			reg = <0x01c06000 0x1000>;
			interrupts = <11>;
			clocks = <&ahb_gates 21>, <&spi1_clk>;
			clock-names = "ahb", "mod";
			dmas = <&dma SUN4I_DMA_DEDICATED 9>,
			       <&dma SUN4I_DMA_DEDICATED 8>;
			dma-names = "rx", "tx";
			status = "disabled";
			#address-cells = <1>;
			#size-cells = <0>;
		};

		emac: ethernet@01c0b000 {
			compatible = "allwinner,sun4i-a10-emac";
			reg = <0x01c0b000 0x1000>;
			interrupts = <55>;
			clocks = <&ahb_gates 17>;
			status = "disabled";
		};

		mdio@01c0b080 {
			compatible = "allwinner,sun4i-a10-mdio";
			reg = <0x01c0b080 0x14>;
			status = "disabled";
			#address-cells = <1>;
			#size-cells = <0>;
		};

		mmc0: mmc@01c0f000 {
			compatible = "allwinner,sun4i-a10-mmc";
			reg = <0x01c0f000 0x1000>;
			clocks = <&ahb_gates 8>, <&mmc0_clk>;
			clock-names = "ahb", "mmc";
			interrupts = <32>;
			status = "disabled";
		};

		mmc1: mmc@01c10000 {
			compatible = "allwinner,sun4i-a10-mmc";
			reg = <0x01c10000 0x1000>;
			clocks = <&ahb_gates 9>, <&mmc1_clk>;
			clock-names = "ahb", "mmc";
			interrupts = <33>;
			status = "disabled";
		};

		mmc2: mmc@01c11000 {
			compatible = "allwinner,sun4i-a10-mmc";
			reg = <0x01c11000 0x1000>;
			clocks = <&ahb_gates 10>, <&mmc2_clk>;
			clock-names = "ahb", "mmc";
			interrupts = <34>;
			status = "disabled";
		};

		mmc3: mmc@01c12000 {
			compatible = "allwinner,sun4i-a10-mmc";
			reg = <0x01c12000 0x1000>;
			clocks = <&ahb_gates 11>, <&mmc3_clk>;
			clock-names = "ahb", "mmc";
			interrupts = <35>;
			status = "disabled";
		};

		usbphy: phy@01c13400 {
			#phy-cells = <1>;
			compatible = "allwinner,sun4i-a10-usb-phy";
			reg = <0x01c13400 0x10 0x01c14800 0x4 0x01c1c800 0x4>;
			reg-names = "phy_ctrl", "pmu1", "pmu2";
			clocks = <&usb_clk 8>;
			clock-names = "usb_phy";
			resets = <&usb_clk 0>, <&usb_clk 1>, <&usb_clk 2>;
			reset-names = "usb0_reset", "usb1_reset", "usb2_reset";
			status = "disabled";
		};

		ehci0: usb@01c14000 {
			compatible = "allwinner,sun4i-a10-ehci", "generic-ehci";
			reg = <0x01c14000 0x100>;
			interrupts = <39>;
			clocks = <&ahb_gates 1>;
			phys = <&usbphy 1>;
			phy-names = "usb";
			status = "disabled";
		};

		ohci0: usb@01c14400 {
			compatible = "allwinner,sun4i-a10-ohci", "generic-ohci";
			reg = <0x01c14400 0x100>;
			interrupts = <64>;
			clocks = <&usb_clk 6>, <&ahb_gates 2>;
			phys = <&usbphy 1>;
			phy-names = "usb";
			status = "disabled";
		};

		spi2: spi@01c17000 {
			compatible = "allwinner,sun4i-a10-spi";
			reg = <0x01c17000 0x1000>;
			interrupts = <12>;
			clocks = <&ahb_gates 22>, <&spi2_clk>;
			clock-names = "ahb", "mod";
			dmas = <&dma SUN4I_DMA_DEDICATED 29>,
			       <&dma SUN4I_DMA_DEDICATED 28>;
			dma-names = "rx", "tx";
			status = "disabled";
			#address-cells = <1>;
			#size-cells = <0>;
		};

		ahci: sata@01c18000 {
			compatible = "allwinner,sun4i-a10-ahci";
			reg = <0x01c18000 0x1000>;
			interrupts = <56>;
			clocks = <&pll6 0>, <&ahb_gates 25>;
			status = "disabled";
		};

		ehci1: usb@01c1c000 {
			compatible = "allwinner,sun4i-a10-ehci", "generic-ehci";
			reg = <0x01c1c000 0x100>;
			interrupts = <40>;
			clocks = <&ahb_gates 3>;
			phys = <&usbphy 2>;
			phy-names = "usb";
			status = "disabled";
		};

		ohci1: usb@01c1c400 {
			compatible = "allwinner,sun4i-a10-ohci", "generic-ohci";
			reg = <0x01c1c400 0x100>;
			interrupts = <65>;
			clocks = <&usb_clk 7>, <&ahb_gates 4>;
			phys = <&usbphy 2>;
			phy-names = "usb";
			status = "disabled";
		};

		spi3: spi@01c1f000 {
			compatible = "allwinner,sun4i-a10-spi";
			reg = <0x01c1f000 0x1000>;
			interrupts = <50>;
			clocks = <&ahb_gates 23>, <&spi3_clk>;
			clock-names = "ahb", "mod";
			dmas = <&dma SUN4I_DMA_DEDICATED 31>,
			       <&dma SUN4I_DMA_DEDICATED 30>;
			dma-names = "rx", "tx";
			status = "disabled";
			#address-cells = <1>;
			#size-cells = <0>;
		};

		intc: interrupt-controller@01c20400 {
			compatible = "allwinner,sun4i-a10-ic";
			reg = <0x01c20400 0x400>;
			interrupt-controller;
			#interrupt-cells = <1>;
		};

		pio: pinctrl@01c20800 {
			compatible = "allwinner,sun4i-a10-pinctrl";
			reg = <0x01c20800 0x400>;
			interrupts = <28>;
			clocks = <&apb0_gates 5>;
			gpio-controller;
			interrupt-controller;
			#interrupt-cells = <2>;
			#size-cells = <0>;
			#gpio-cells = <3>;

			pwm0_pins_a: pwm0@0 {
				allwinner,pins = "PB2";
				allwinner,function = "pwm";
				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
			};

			pwm1_pins_a: pwm1@0 {
				allwinner,pins = "PI3";
				allwinner,function = "pwm";
				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
			};

			uart0_pins_a: uart0@0 {
				allwinner,pins = "PB22", "PB23";
				allwinner,function = "uart0";
				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
			};

			uart0_pins_b: uart0@1 {
				allwinner,pins = "PF2", "PF4";
				allwinner,function = "uart0";
				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
			};

			uart1_pins_a: uart1@0 {
				allwinner,pins = "PA10", "PA11";
				allwinner,function = "uart1";
				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
			};

			i2c0_pins_a: i2c0@0 {
				allwinner,pins = "PB0", "PB1";
				allwinner,function = "i2c0";
				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
			};

			i2c1_pins_a: i2c1@0 {
				allwinner,pins = "PB18", "PB19";
				allwinner,function = "i2c1";
				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
			};

			i2c2_pins_a: i2c2@0 {
				allwinner,pins = "PB20", "PB21";
				allwinner,function = "i2c2";
				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
			};

			emac_pins_a: emac0@0 {
				allwinner,pins = "PA0", "PA1", "PA2",
						"PA3", "PA4", "PA5", "PA6",
						"PA7", "PA8", "PA9", "PA10",
						"PA11", "PA12", "PA13", "PA14",
						"PA15", "PA16";
				allwinner,function = "emac";
				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
			};

			mmc0_pins_a: mmc0@0 {
				allwinner,pins = "PF0","PF1","PF2","PF3","PF4","PF5";
				allwinner,function = "mmc0";
				allwinner,drive = <SUN4I_PINCTRL_30_MA>;
				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
			};

			mmc0_cd_pin_reference_design: mmc0_cd_pin@0 {
				allwinner,pins = "PH1";
				allwinner,function = "gpio_in";
				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
				allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
			};

			ir0_pins_a: ir0@0 {
				allwinner,pins = "PB3","PB4";
				allwinner,function = "ir0";
				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
			};

			ir1_pins_a: ir1@0 {
				allwinner,pins = "PB22","PB23";
				allwinner,function = "ir1";
				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
			};

			spi0_pins_a: spi0@0 {
				allwinner,pins = "PI10", "PI11", "PI12", "PI13";
				allwinner,function = "spi0";
				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
			};

			spi1_pins_a: spi1@0 {
				allwinner,pins = "PI16", "PI17", "PI18", "PI19";
				allwinner,function = "spi1";
				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
			};

			spi2_pins_a: spi2@0 {
				allwinner,pins = "PB14", "PB15", "PB16", "PB17";
				allwinner,function = "spi2";
				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
			};

			spi2_pins_b: spi2@1 {
				allwinner,pins = "PC19", "PC20", "PC21", "PC22";
				allwinner,function = "spi2";
				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
			};
		};

		timer@01c20c00 {
			compatible = "allwinner,sun4i-a10-timer";
			reg = <0x01c20c00 0x90>;
			interrupts = <22>;
			clocks = <&osc24M>;
		};

		wdt: watchdog@01c20c90 {
			compatible = "allwinner,sun4i-a10-wdt";
			reg = <0x01c20c90 0x10>;
		};

		rtc: rtc@01c20d00 {
			compatible = "allwinner,sun4i-a10-rtc";
			reg = <0x01c20d00 0x20>;
			interrupts = <24>;
		};

		pwm: pwm@01c20e00 {
			compatible = "allwinner,sun4i-a10-pwm";
			reg = <0x01c20e00 0xc>;
			clocks = <&osc24M>;
			#pwm-cells = <3>;
			status = "disabled";
		};

		ir0: ir@01c21800 {
			compatible = "allwinner,sun4i-a10-ir";
			clocks = <&apb0_gates 6>, <&ir0_clk>;
			clock-names = "apb", "ir";
			interrupts = <5>;
			reg = <0x01c21800 0x40>;
			status = "disabled";
		};

		ir1: ir@01c21c00 {
			compatible = "allwinner,sun4i-a10-ir";
			clocks = <&apb0_gates 7>, <&ir1_clk>;
			clock-names = "apb", "ir";
			interrupts = <6>;
			reg = <0x01c21c00 0x40>;
			status = "disabled";
		};

		lradc: lradc@01c22800 {
			compatible = "allwinner,sun4i-a10-lradc-keys";
			reg = <0x01c22800 0x100>;
			interrupts = <31>;
			status = "disabled";
		};

		sid: eeprom@01c23800 {
			compatible = "allwinner,sun4i-a10-sid";
			reg = <0x01c23800 0x10>;
		};

		rtp: rtp@01c25000 {
			compatible = "allwinner,sun4i-a10-ts";
			reg = <0x01c25000 0x100>;
			interrupts = <29>;
			#thermal-sensor-cells = <0>;
		};

		uart0: serial@01c28000 {
			compatible = "snps,dw-apb-uart";
			reg = <0x01c28000 0x400>;
			interrupts = <1>;
			reg-shift = <2>;
			reg-io-width = <4>;
			clocks = <&apb1_gates 16>;
			status = "disabled";
		};

		uart1: serial@01c28400 {
			compatible = "snps,dw-apb-uart";
			reg = <0x01c28400 0x400>;
			interrupts = <2>;
			reg-shift = <2>;
			reg-io-width = <4>;
			clocks = <&apb1_gates 17>;
			status = "disabled";
		};

		uart2: serial@01c28800 {
			compatible = "snps,dw-apb-uart";
			reg = <0x01c28800 0x400>;
			interrupts = <3>;
			reg-shift = <2>;
			reg-io-width = <4>;
			clocks = <&apb1_gates 18>;
			status = "disabled";
		};

		uart3: serial@01c28c00 {
			compatible = "snps,dw-apb-uart";
			reg = <0x01c28c00 0x400>;
			interrupts = <4>;
			reg-shift = <2>;
			reg-io-width = <4>;
			clocks = <&apb1_gates 19>;
			status = "disabled";
		};

		uart4: serial@01c29000 {
			compatible = "snps,dw-apb-uart";
			reg = <0x01c29000 0x400>;
			interrupts = <17>;
			reg-shift = <2>;
			reg-io-width = <4>;
			clocks = <&apb1_gates 20>;
			status = "disabled";
		};

		uart5: serial@01c29400 {
			compatible = "snps,dw-apb-uart";
			reg = <0x01c29400 0x400>;
			interrupts = <18>;
			reg-shift = <2>;
			reg-io-width = <4>;
			clocks = <&apb1_gates 21>;
			status = "disabled";
		};

		uart6: serial@01c29800 {
			compatible = "snps,dw-apb-uart";
			reg = <0x01c29800 0x400>;
			interrupts = <19>;
			reg-shift = <2>;
			reg-io-width = <4>;
			clocks = <&apb1_gates 22>;
			status = "disabled";
		};

		uart7: serial@01c29c00 {
			compatible = "snps,dw-apb-uart";
			reg = <0x01c29c00 0x400>;
			interrupts = <20>;
			reg-shift = <2>;
			reg-io-width = <4>;
			clocks = <&apb1_gates 23>;
			status = "disabled";
		};

		i2c0: i2c@01c2ac00 {
			compatible = "allwinner,sun4i-a10-i2c";
			reg = <0x01c2ac00 0x400>;
			interrupts = <7>;
			clocks = <&apb1_gates 0>;
			status = "disabled";
			#address-cells = <1>;
			#size-cells = <0>;
		};

		i2c1: i2c@01c2b000 {
			compatible = "allwinner,sun4i-a10-i2c";
			reg = <0x01c2b000 0x400>;
			interrupts = <8>;
			clocks = <&apb1_gates 1>;
			status = "disabled";
			#address-cells = <1>;
			#size-cells = <0>;
		};

		i2c2: i2c@01c2b400 {
			compatible = "allwinner,sun4i-a10-i2c";
			reg = <0x01c2b400 0x400>;
			interrupts = <9>;
			clocks = <&apb1_gates 2>;
			status = "disabled";
			#address-cells = <1>;
			#size-cells = <0>;
		};
	};
};