common.c 16.8 KB
Newer Older
1
/*
2
 * arch/arm/mach-orion5x/common.c
3
 *
4
 * Core functions for Marvell Orion 5x SoCs
5 6 7
 *
 * Maintainer: Tzachi Perelstein <tzachi@marvell.com>
 *
L
Lennert Buytenhek 已提交
8 9
 * This file is licensed under the terms of the GNU General Public
 * License version 2.  This program is licensed "as is" without any
10 11 12 13 14
 * warranty of any kind, whether express or implied.
 */

#include <linux/kernel.h>
#include <linux/init.h>
15 16
#include <linux/platform_device.h>
#include <linux/serial_8250.h>
17
#include <linux/mbus.h>
18
#include <linux/mv643xx_eth.h>
19
#include <linux/mv643xx_i2c.h>
20
#include <linux/ata_platform.h>
21
#include <linux/spi/orion_spi.h>
22
#include <net/dsa.h>
23
#include <asm/page.h>
24
#include <asm/setup.h>
25
#include <asm/timex.h>
26
#include <asm/mach/arch.h>
27
#include <asm/mach/map.h>
28
#include <asm/mach/time.h>
29 30
#include <mach/hardware.h>
#include <mach/orion5x.h>
31
#include <plat/ehci-orion.h>
32
#include <plat/mv_xor.h>
33
#include <plat/orion_nand.h>
34
#include <plat/orion5x_wdt.h>
35
#include <plat/time.h>
36 37 38 39 40
#include "common.h"

/*****************************************************************************
 * I/O Address Mapping
 ****************************************************************************/
41
static struct map_desc orion5x_io_desc[] __initdata = {
42
	{
43 44 45
		.virtual	= ORION5X_REGS_VIRT_BASE,
		.pfn		= __phys_to_pfn(ORION5X_REGS_PHYS_BASE),
		.length		= ORION5X_REGS_SIZE,
46 47
		.type		= MT_DEVICE,
	}, {
48 49 50
		.virtual	= ORION5X_PCIE_IO_VIRT_BASE,
		.pfn		= __phys_to_pfn(ORION5X_PCIE_IO_PHYS_BASE),
		.length		= ORION5X_PCIE_IO_SIZE,
51 52
		.type		= MT_DEVICE,
	}, {
53 54 55
		.virtual	= ORION5X_PCI_IO_VIRT_BASE,
		.pfn		= __phys_to_pfn(ORION5X_PCI_IO_PHYS_BASE),
		.length		= ORION5X_PCI_IO_SIZE,
56 57
		.type		= MT_DEVICE,
	}, {
58 59 60
		.virtual	= ORION5X_PCIE_WA_VIRT_BASE,
		.pfn		= __phys_to_pfn(ORION5X_PCIE_WA_PHYS_BASE),
		.length		= ORION5X_PCIE_WA_SIZE,
61
		.type		= MT_DEVICE,
62 63 64
	},
};

65
void __init orion5x_map_io(void)
66
{
67
	iotable_init(orion5x_io_desc, ARRAY_SIZE(orion5x_io_desc));
68
}
69

70

71
/*****************************************************************************
72
 * EHCI
73
 ****************************************************************************/
74 75
static struct orion_ehci_data orion5x_ehci_data = {
	.dram		= &orion5x_mbus_dram_info,
76
	.phy_version	= EHCI_PHY_ORION,
77 78
};

79
static u64 ehci_dmamask = 0xffffffffUL;
80 81


82 83 84
/*****************************************************************************
 * EHCI0
 ****************************************************************************/
85
static struct resource orion5x_ehci0_resources[] = {
86
	{
87
		.start	= ORION5X_USB0_PHYS_BASE,
88
		.end	= ORION5X_USB0_PHYS_BASE + SZ_4K - 1,
89
		.flags	= IORESOURCE_MEM,
90
	}, {
91 92
		.start	= IRQ_ORION5X_USB0_CTRL,
		.end	= IRQ_ORION5X_USB0_CTRL,
93 94 95 96
		.flags	= IORESOURCE_IRQ,
	},
};

97
static struct platform_device orion5x_ehci0 = {
98 99 100 101 102
	.name		= "orion-ehci",
	.id		= 0,
	.dev		= {
		.dma_mask		= &ehci_dmamask,
		.coherent_dma_mask	= 0xffffffff,
103
		.platform_data		= &orion5x_ehci_data,
104
	},
105 106
	.resource	= orion5x_ehci0_resources,
	.num_resources	= ARRAY_SIZE(orion5x_ehci0_resources),
107 108
};

109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129
void __init orion5x_ehci0_init(void)
{
	platform_device_register(&orion5x_ehci0);
}


/*****************************************************************************
 * EHCI1
 ****************************************************************************/
static struct resource orion5x_ehci1_resources[] = {
	{
		.start	= ORION5X_USB1_PHYS_BASE,
		.end	= ORION5X_USB1_PHYS_BASE + SZ_4K - 1,
		.flags	= IORESOURCE_MEM,
	}, {
		.start	= IRQ_ORION5X_USB1_CTRL,
		.end	= IRQ_ORION5X_USB1_CTRL,
		.flags	= IORESOURCE_IRQ,
	},
};

130
static struct platform_device orion5x_ehci1 = {
131 132 133 134 135
	.name		= "orion-ehci",
	.id		= 1,
	.dev		= {
		.dma_mask		= &ehci_dmamask,
		.coherent_dma_mask	= 0xffffffff,
136
		.platform_data		= &orion5x_ehci_data,
137
	},
138 139
	.resource	= orion5x_ehci1_resources,
	.num_resources	= ARRAY_SIZE(orion5x_ehci1_resources),
140 141
};

142 143 144 145 146 147
void __init orion5x_ehci1_init(void)
{
	platform_device_register(&orion5x_ehci1);
}


148
/*****************************************************************************
149
 * GigE
150
 ****************************************************************************/
151 152 153 154
struct mv643xx_eth_shared_platform_data orion5x_eth_shared_data = {
	.dram		= &orion5x_mbus_dram_info,
};

155
static struct resource orion5x_eth_shared_resources[] = {
156
	{
157 158
		.start	= ORION5X_ETH_PHYS_BASE + 0x2000,
		.end	= ORION5X_ETH_PHYS_BASE + 0x3fff,
159
		.flags	= IORESOURCE_MEM,
160 161 162 163
	}, {
		.start	= IRQ_ORION5X_ETH_ERR,
		.end	= IRQ_ORION5X_ETH_ERR,
		.flags	= IORESOURCE_IRQ,
164 165 166
	},
};

167
static struct platform_device orion5x_eth_shared = {
168 169
	.name		= MV643XX_ETH_SHARED_NAME,
	.id		= 0,
170 171 172
	.dev		= {
		.platform_data	= &orion5x_eth_shared_data,
	},
173
	.num_resources	= ARRAY_SIZE(orion5x_eth_shared_resources),
174
	.resource	= orion5x_eth_shared_resources,
175 176
};

177
static struct resource orion5x_eth_resources[] = {
178 179
	{
		.name	= "eth irq",
180 181
		.start	= IRQ_ORION5X_ETH_SUM,
		.end	= IRQ_ORION5X_ETH_SUM,
182
		.flags	= IORESOURCE_IRQ,
183
	},
184 185
};

186
static struct platform_device orion5x_eth = {
187 188 189
	.name		= MV643XX_ETH_NAME,
	.id		= 0,
	.num_resources	= 1,
190
	.resource	= orion5x_eth_resources,
191 192
};

193
void __init orion5x_eth_init(struct mv643xx_eth_platform_data *eth_data)
194
{
195
	eth_data->shared = &orion5x_eth_shared;
196
	orion5x_eth.dev.platform_data = eth_data;
197

198 199
	platform_device_register(&orion5x_eth_shared);
	platform_device_register(&orion5x_eth);
200 201
}

202

203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222
/*****************************************************************************
 * Ethernet switch
 ****************************************************************************/
static struct resource orion5x_switch_resources[] = {
	{
		.start	= 0,
		.end	= 0,
		.flags	= IORESOURCE_IRQ,
	},
};

static struct platform_device orion5x_switch_device = {
	.name		= "dsa",
	.id		= 0,
	.num_resources	= 0,
	.resource	= orion5x_switch_resources,
};

void __init orion5x_eth_switch_init(struct dsa_platform_data *d, int irq)
{
223 224
	int i;

225 226 227 228 229 230 231
	if (irq != NO_IRQ) {
		orion5x_switch_resources[0].start = irq;
		orion5x_switch_resources[0].end = irq;
		orion5x_switch_device.num_resources = 1;
	}

	d->netdev = &orion5x_eth.dev;
232 233
	for (i = 0; i < d->nr_chips; i++)
		d->chip[i].mii_bus = &orion5x_eth_shared.dev;
234 235 236 237 238 239
	orion5x_switch_device.dev.platform_data = d;

	platform_device_register(&orion5x_switch_device);
}


240
/*****************************************************************************
241
 * I2C
242
 ****************************************************************************/
243
static struct mv64xxx_i2c_pdata orion5x_i2c_pdata = {
244 245 246 247 248
	.freq_m		= 8, /* assumes 166 MHz TCLK */
	.freq_n		= 3,
	.timeout	= 1000, /* Default timeout of 1 second */
};

249
static struct resource orion5x_i2c_resources[] = {
250
	{
251
		.start	= I2C_PHYS_BASE,
252
		.end	= I2C_PHYS_BASE + 0x1f,
253 254 255 256 257
		.flags	= IORESOURCE_MEM,
	}, {
		.start	= IRQ_ORION5X_I2C,
		.end	= IRQ_ORION5X_I2C,
		.flags	= IORESOURCE_IRQ,
258 259 260
	},
};

261
static struct platform_device orion5x_i2c = {
262 263
	.name		= MV64XXX_I2C_CTLR_NAME,
	.id		= 0,
264 265
	.num_resources	= ARRAY_SIZE(orion5x_i2c_resources),
	.resource	= orion5x_i2c_resources,
266
	.dev		= {
267
		.platform_data	= &orion5x_i2c_pdata,
268 269 270
	},
};

271 272 273 274 275 276
void __init orion5x_i2c_init(void)
{
	platform_device_register(&orion5x_i2c);
}


277
/*****************************************************************************
278
 * SATA
279
 ****************************************************************************/
280
static struct resource orion5x_sata_resources[] = {
281
	{
282 283 284 285 286 287 288 289 290 291
		.name	= "sata base",
		.start	= ORION5X_SATA_PHYS_BASE,
		.end	= ORION5X_SATA_PHYS_BASE + 0x5000 - 1,
		.flags	= IORESOURCE_MEM,
	}, {
		.name	= "sata irq",
		.start	= IRQ_ORION5X_SATA,
		.end	= IRQ_ORION5X_SATA,
		.flags	= IORESOURCE_IRQ,
	},
292 293
};

294
static struct platform_device orion5x_sata = {
295 296
	.name		= "sata_mv",
	.id		= 0,
297 298 299
	.dev		= {
		.coherent_dma_mask	= 0xffffffff,
	},
300 301
	.num_resources	= ARRAY_SIZE(orion5x_sata_resources),
	.resource	= orion5x_sata_resources,
302 303
};

304
void __init orion5x_sata_init(struct mv_sata_platform_data *sata_data)
305
{
306 307 308
	sata_data->dram = &orion5x_mbus_dram_info;
	orion5x_sata.dev.platform_data = sata_data;
	platform_device_register(&orion5x_sata);
309 310
}

311

312 313 314 315
/*****************************************************************************
 * SPI
 ****************************************************************************/
static struct orion_spi_info orion5x_spi_plat_data = {
316 317
	.tclk			= 0,
	.enable_clock_fix	= 1,
318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344
};

static struct resource orion5x_spi_resources[] = {
	{
		.name	= "spi base",
		.start	= SPI_PHYS_BASE,
		.end	= SPI_PHYS_BASE + 0x1f,
		.flags	= IORESOURCE_MEM,
	},
};

static struct platform_device orion5x_spi = {
	.name		= "orion_spi",
	.id		= 0,
	.dev		= {
		.platform_data	= &orion5x_spi_plat_data,
	},
	.num_resources	= ARRAY_SIZE(orion5x_spi_resources),
	.resource	= orion5x_spi_resources,
};

void __init orion5x_spi_init()
{
	platform_device_register(&orion5x_spi);
}


345
/*****************************************************************************
346 347 348 349 350 351 352 353 354 355
 * UART0
 ****************************************************************************/
static struct plat_serial8250_port orion5x_uart0_data[] = {
	{
		.mapbase	= UART0_PHYS_BASE,
		.membase	= (char *)UART0_VIRT_BASE,
		.irq		= IRQ_ORION5X_UART0,
		.flags		= UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
		.iotype		= UPIO_MEM,
		.regshift	= 2,
356
		.uartclk	= 0,
357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390
	}, {
	},
};

static struct resource orion5x_uart0_resources[] = {
	{
		.start		= UART0_PHYS_BASE,
		.end		= UART0_PHYS_BASE + 0xff,
		.flags		= IORESOURCE_MEM,
	}, {
		.start		= IRQ_ORION5X_UART0,
		.end		= IRQ_ORION5X_UART0,
		.flags		= IORESOURCE_IRQ,
	},
};

static struct platform_device orion5x_uart0 = {
	.name			= "serial8250",
	.id			= PLAT8250_DEV_PLATFORM,
	.dev			= {
		.platform_data	= orion5x_uart0_data,
	},
	.resource		= orion5x_uart0_resources,
	.num_resources		= ARRAY_SIZE(orion5x_uart0_resources),
};

void __init orion5x_uart0_init(void)
{
	platform_device_register(&orion5x_uart0);
}


/*****************************************************************************
 * UART1
391
 ****************************************************************************/
392 393 394 395 396 397 398 399
static struct plat_serial8250_port orion5x_uart1_data[] = {
	{
		.mapbase	= UART1_PHYS_BASE,
		.membase	= (char *)UART1_VIRT_BASE,
		.irq		= IRQ_ORION5X_UART1,
		.flags		= UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
		.iotype		= UPIO_MEM,
		.regshift	= 2,
400
		.uartclk	= 0,
401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 419 420 421 422 423 424 425 426 427 428 429 430
	}, {
	},
};

static struct resource orion5x_uart1_resources[] = {
	{
		.start		= UART1_PHYS_BASE,
		.end		= UART1_PHYS_BASE + 0xff,
		.flags		= IORESOURCE_MEM,
	}, {
		.start		= IRQ_ORION5X_UART1,
		.end		= IRQ_ORION5X_UART1,
		.flags		= IORESOURCE_IRQ,
	},
};

static struct platform_device orion5x_uart1 = {
	.name			= "serial8250",
	.id			= PLAT8250_DEV_PLATFORM1,
	.dev			= {
		.platform_data	= orion5x_uart1_data,
	},
	.resource		= orion5x_uart1_resources,
	.num_resources		= ARRAY_SIZE(orion5x_uart1_resources),
};

void __init orion5x_uart1_init(void)
{
	platform_device_register(&orion5x_uart1);
}
431

432

433 434 435
/*****************************************************************************
 * XOR engine
 ****************************************************************************/
436 437 438 439
struct mv_xor_platform_shared_data orion5x_xor_shared_data = {
	.dram		= &orion5x_mbus_dram_info,
};

440 441 442 443 444 445 446 447 448 449 450 451 452 453 454 455 456
static struct resource orion5x_xor_shared_resources[] = {
	{
		.name	= "xor low",
		.start	= ORION5X_XOR_PHYS_BASE,
		.end	= ORION5X_XOR_PHYS_BASE + 0xff,
		.flags	= IORESOURCE_MEM,
	}, {
		.name	= "xor high",
		.start	= ORION5X_XOR_PHYS_BASE + 0x200,
		.end	= ORION5X_XOR_PHYS_BASE + 0x2ff,
		.flags	= IORESOURCE_MEM,
	},
};

static struct platform_device orion5x_xor_shared = {
	.name		= MV_XOR_SHARED_NAME,
	.id		= 0,
457 458 459
	.dev		= {
		.platform_data	= &orion5x_xor_shared_data,
	},
460 461 462 463
	.num_resources	= ARRAY_SIZE(orion5x_xor_shared_resources),
	.resource	= orion5x_xor_shared_resources,
};

464
static u64 orion5x_xor_dmamask = DMA_BIT_MASK(32);
465 466 467 468 469 470 471 472 473 474 475 476 477 478 479 480 481 482 483 484 485 486

static struct resource orion5x_xor0_resources[] = {
	[0] = {
		.start	= IRQ_ORION5X_XOR0,
		.end	= IRQ_ORION5X_XOR0,
		.flags	= IORESOURCE_IRQ,
	},
};

static struct mv_xor_platform_data orion5x_xor0_data = {
	.shared		= &orion5x_xor_shared,
	.hw_id		= 0,
	.pool_size	= PAGE_SIZE,
};

static struct platform_device orion5x_xor0_channel = {
	.name		= MV_XOR_NAME,
	.id		= 0,
	.num_resources	= ARRAY_SIZE(orion5x_xor0_resources),
	.resource	= orion5x_xor0_resources,
	.dev		= {
		.dma_mask		= &orion5x_xor_dmamask,
487
		.coherent_dma_mask	= DMA_BIT_MASK(64),
488 489 490 491 492 493 494 495 496 497 498 499 500 501 502 503 504 505 506 507 508 509 510 511 512
		.platform_data		= (void *)&orion5x_xor0_data,
	},
};

static struct resource orion5x_xor1_resources[] = {
	[0] = {
		.start	= IRQ_ORION5X_XOR1,
		.end	= IRQ_ORION5X_XOR1,
		.flags	= IORESOURCE_IRQ,
	},
};

static struct mv_xor_platform_data orion5x_xor1_data = {
	.shared		= &orion5x_xor_shared,
	.hw_id		= 1,
	.pool_size	= PAGE_SIZE,
};

static struct platform_device orion5x_xor1_channel = {
	.name		= MV_XOR_NAME,
	.id		= 1,
	.num_resources	= ARRAY_SIZE(orion5x_xor1_resources),
	.resource	= orion5x_xor1_resources,
	.dev		= {
		.dma_mask		= &orion5x_xor_dmamask,
513
		.coherent_dma_mask	= DMA_BIT_MASK(64),
514 515 516 517 518 519 520 521 522 523 524 525 526 527 528 529 530 531 532 533 534 535 536
		.platform_data		= (void *)&orion5x_xor1_data,
	},
};

void __init orion5x_xor_init(void)
{
	platform_device_register(&orion5x_xor_shared);

	/*
	 * two engines can't do memset simultaneously, this limitation
	 * satisfied by removing memset support from one of the engines.
	 */
	dma_cap_set(DMA_MEMCPY, orion5x_xor0_data.cap_mask);
	dma_cap_set(DMA_XOR, orion5x_xor0_data.cap_mask);
	platform_device_register(&orion5x_xor0_channel);

	dma_cap_set(DMA_MEMCPY, orion5x_xor1_data.cap_mask);
	dma_cap_set(DMA_MEMSET, orion5x_xor1_data.cap_mask);
	dma_cap_set(DMA_XOR, orion5x_xor1_data.cap_mask);
	platform_device_register(&orion5x_xor1_channel);
}


537 538 539 540 541 542 543 544 545 546 547 548 549 550 551 552 553 554 555 556 557 558 559
/*****************************************************************************
 * Watchdog
 ****************************************************************************/
static struct orion5x_wdt_platform_data orion5x_wdt_data = {
	.tclk			= 0,
};

static struct platform_device orion5x_wdt_device = {
	.name		= "orion5x_wdt",
	.id		= -1,
	.dev		= {
		.platform_data	= &orion5x_wdt_data,
	},
	.num_resources	= 0,
};

void __init orion5x_wdt_init(void)
{
	orion5x_wdt_data.tclk = orion5x_tclk;
	platform_device_register(&orion5x_wdt_device);
}


560 561 562
/*****************************************************************************
 * Time handling
 ****************************************************************************/
563 564 565 566
int orion5x_tclk;

int __init orion5x_find_tclk(void)
{
567 568 569 570 571 572 573
	u32 dev, rev;

	orion5x_pcie_id(&dev, &rev);
	if (dev == MV88F6183_DEV_ID &&
	    (readl(MPP_RESET_SAMPLE) & 0x00000200) == 0)
		return 133333333;

574 575 576
	return 166666667;
}

577
static void orion5x_timer_init(void)
578
{
579 580
	orion5x_tclk = orion5x_find_tclk();
	orion_time_init(IRQ_ORION5X_BRIDGE, orion5x_tclk);
581 582
}

583
struct sys_timer orion5x_timer = {
584
	.init = orion5x_timer_init,
585 586
};

587

588 589 590 591
/*****************************************************************************
 * General
 ****************************************************************************/
/*
592
 * Identify device ID and rev from PCIe configuration header space '0'.
593
 */
594
static void __init orion5x_id(u32 *dev, u32 *rev, char **dev_name)
595
{
596
	orion5x_pcie_id(dev, rev);
597 598 599 600 601 602

	if (*dev == MV88F5281_DEV_ID) {
		if (*rev == MV88F5281_REV_D2) {
			*dev_name = "MV88F5281-D2";
		} else if (*rev == MV88F5281_REV_D1) {
			*dev_name = "MV88F5281-D1";
603 604
		} else if (*rev == MV88F5281_REV_D0) {
			*dev_name = "MV88F5281-D0";
605 606 607 608 609 610 611 612 613
		} else {
			*dev_name = "MV88F5281-Rev-Unsupported";
		}
	} else if (*dev == MV88F5182_DEV_ID) {
		if (*rev == MV88F5182_REV_A2) {
			*dev_name = "MV88F5182-A2";
		} else {
			*dev_name = "MV88F5182-Rev-Unsupported";
		}
614 615 616
	} else if (*dev == MV88F5181_DEV_ID) {
		if (*rev == MV88F5181_REV_B1) {
			*dev_name = "MV88F5181-Rev-B1";
617 618
		} else if (*rev == MV88F5181L_REV_A1) {
			*dev_name = "MV88F5181L-Rev-A1";
619
		} else {
620
			*dev_name = "MV88F5181(L)-Rev-Unsupported";
621
		}
622 623 624 625 626 627
	} else if (*dev == MV88F6183_DEV_ID) {
		if (*rev == MV88F6183_REV_B0) {
			*dev_name = "MV88F6183-Rev-B0";
		} else {
			*dev_name = "MV88F6183-Rev-Unsupported";
		}
628 629 630 631 632
	} else {
		*dev_name = "Device-Unknown";
	}
}

633
void __init orion5x_init(void)
634 635 636 637
{
	char *dev_name;
	u32 dev, rev;

638
	orion5x_id(&dev, &rev, &dev_name);
639 640 641
	printk(KERN_INFO "Orion ID: %s. TCLK=%d.\n", dev_name, orion5x_tclk);

	orion5x_eth_shared_data.t_clk = orion5x_tclk;
642
	orion5x_spi_plat_data.tclk = orion5x_tclk;
643 644
	orion5x_uart0_data[0].uartclk = orion5x_tclk;
	orion5x_uart1_data[0].uartclk = orion5x_tclk;
645 646 647 648

	/*
	 * Setup Orion address map
	 */
649
	orion5x_setup_cpu_mbus_bridge();
650 651 652 653 654 655 656 657 658

	/*
	 * Don't issue "Wait for Interrupt" instruction if we are
	 * running on D0 5281 silicon.
	 */
	if (dev == MV88F5281_DEV_ID && rev == MV88F5281_REV_D0) {
		printk(KERN_INFO "Orion: Applying 5281 D0 WFI workaround.\n");
		disable_hlt();
	}
659 660 661 662 663

	/*
	 * Register watchdog driver
	 */
	orion5x_wdt_init();
664
}
665 666 667 668 669 670 671 672 673 674 675 676 677 678 679 680 681 682

/*
 * Many orion-based systems have buggy bootloader implementations.
 * This is a common fixup for bogus memory tags.
 */
void __init tag_fixup_mem32(struct machine_desc *mdesc, struct tag *t,
			    char **from, struct meminfo *meminfo)
{
	for (; t->hdr.size; t = tag_next(t))
		if (t->hdr.tag == ATAG_MEM &&
		    (!t->u.mem.size || t->u.mem.size & ~PAGE_MASK ||
		     t->u.mem.start & ~PAGE_MASK)) {
			printk(KERN_WARNING
			       "Clearing invalid memory bank %dKB@0x%08x\n",
			       t->u.mem.size / 1024, t->u.mem.start);
			t->hdr.tag = 0;
		}
}