imx-sdma.c 49.1 KB
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/*
 * drivers/dma/imx-sdma.c
 *
 * This file contains a driver for the Freescale Smart DMA engine
 *
 * Copyright 2010 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
 *
 * Based on code from Freescale:
 *
 * Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved.
 *
 * The code contained herein is licensed under the GNU General Public
 * License. You may obtain a copy of the GNU General Public License
 * Version 2 or later at the following locations:
 *
 * http://www.opensource.org/licenses/gpl-license.html
 * http://www.gnu.org/copyleft/gpl.html
 */

#include <linux/init.h>
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#include <linux/iopoll.h>
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#include <linux/module.h>
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#include <linux/types.h>
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#include <linux/bitops.h>
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#include <linux/mm.h>
#include <linux/interrupt.h>
#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/sched.h>
#include <linux/semaphore.h>
#include <linux/spinlock.h>
#include <linux/device.h>
#include <linux/dma-mapping.h>
#include <linux/firmware.h>
#include <linux/slab.h>
#include <linux/platform_device.h>
#include <linux/dmaengine.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_device.h>
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#include <linux/of_dma.h>
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#include <asm/irq.h>
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#include <linux/platform_data/dma-imx-sdma.h>
#include <linux/platform_data/dma-imx.h>
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#include <linux/regmap.h>
#include <linux/mfd/syscon.h>
#include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
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#include "dmaengine.h"

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/* SDMA registers */
#define SDMA_H_C0PTR		0x000
#define SDMA_H_INTR		0x004
#define SDMA_H_STATSTOP		0x008
#define SDMA_H_START		0x00c
#define SDMA_H_EVTOVR		0x010
#define SDMA_H_DSPOVR		0x014
#define SDMA_H_HOSTOVR		0x018
#define SDMA_H_EVTPEND		0x01c
#define SDMA_H_DSPENBL		0x020
#define SDMA_H_RESET		0x024
#define SDMA_H_EVTERR		0x028
#define SDMA_H_INTRMSK		0x02c
#define SDMA_H_PSW		0x030
#define SDMA_H_EVTERRDBG	0x034
#define SDMA_H_CONFIG		0x038
#define SDMA_ONCE_ENB		0x040
#define SDMA_ONCE_DATA		0x044
#define SDMA_ONCE_INSTR		0x048
#define SDMA_ONCE_STAT		0x04c
#define SDMA_ONCE_CMD		0x050
#define SDMA_EVT_MIRROR		0x054
#define SDMA_ILLINSTADDR	0x058
#define SDMA_CHN0ADDR		0x05c
#define SDMA_ONCE_RTB		0x060
#define SDMA_XTRIG_CONF1	0x070
#define SDMA_XTRIG_CONF2	0x074
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#define SDMA_CHNENBL0_IMX35	0x200
#define SDMA_CHNENBL0_IMX31	0x080
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#define SDMA_CHNPRI_0		0x100

/*
 * Buffer descriptor status values.
 */
#define BD_DONE  0x01
#define BD_WRAP  0x02
#define BD_CONT  0x04
#define BD_INTR  0x08
#define BD_RROR  0x10
#define BD_LAST  0x20
#define BD_EXTD  0x80

/*
 * Data Node descriptor status values.
 */
#define DND_END_OF_FRAME  0x80
#define DND_END_OF_XFER   0x40
#define DND_DONE          0x20
#define DND_UNUSED        0x01

/*
 * IPCV2 descriptor status values.
 */
#define BD_IPCV2_END_OF_FRAME  0x40

#define IPCV2_MAX_NODES        50
/*
 * Error bit set in the CCB status field by the SDMA,
 * in setbd routine, in case of a transfer error
 */
#define DATA_ERROR  0x10000000

/*
 * Buffer descriptor commands.
 */
#define C0_ADDR             0x01
#define C0_LOAD             0x02
#define C0_DUMP             0x03
#define C0_SETCTX           0x07
#define C0_GETCTX           0x03
#define C0_SETDM            0x01
#define C0_SETPM            0x04
#define C0_GETDM            0x02
#define C0_GETPM            0x08
/*
 * Change endianness indicator in the BD command field
 */
#define CHANGE_ENDIANNESS   0x80

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/*
 *  p_2_p watermark_level description
 *	Bits		Name			Description
 *	0-7		Lower WML		Lower watermark level
 *	8		PS			1: Pad Swallowing
 *						0: No Pad Swallowing
 *	9		PA			1: Pad Adding
 *						0: No Pad Adding
 *	10		SPDIF			If this bit is set both source
 *						and destination are on SPBA
 *	11		Source Bit(SP)		1: Source on SPBA
 *						0: Source on AIPS
 *	12		Destination Bit(DP)	1: Destination on SPBA
 *						0: Destination on AIPS
 *	13-15		---------		MUST BE 0
 *	16-23		Higher WML		HWML
 *	24-27		N			Total number of samples after
 *						which Pad adding/Swallowing
 *						must be done. It must be odd.
 *	28		Lower WML Event(LWE)	SDMA events reg to check for
 *						LWML event mask
 *						0: LWE in EVENTS register
 *						1: LWE in EVENTS2 register
 *	29		Higher WML Event(HWE)	SDMA events reg to check for
 *						HWML event mask
 *						0: HWE in EVENTS register
 *						1: HWE in EVENTS2 register
 *	30		---------		MUST BE 0
 *	31		CONT			1: Amount of samples to be
 *						transferred is unknown and
 *						script will keep on
 *						transferring samples as long as
 *						both events are detected and
 *						script must be manually stopped
 *						by the application
 *						0: The amount of samples to be
 *						transferred is equal to the
 *						count field of mode word
 */
#define SDMA_WATERMARK_LEVEL_LWML	0xFF
#define SDMA_WATERMARK_LEVEL_PS		BIT(8)
#define SDMA_WATERMARK_LEVEL_PA		BIT(9)
#define SDMA_WATERMARK_LEVEL_SPDIF	BIT(10)
#define SDMA_WATERMARK_LEVEL_SP		BIT(11)
#define SDMA_WATERMARK_LEVEL_DP		BIT(12)
#define SDMA_WATERMARK_LEVEL_HWML	(0xFF << 16)
#define SDMA_WATERMARK_LEVEL_LWE	BIT(28)
#define SDMA_WATERMARK_LEVEL_HWE	BIT(29)
#define SDMA_WATERMARK_LEVEL_CONT	BIT(31)

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/*
 * Mode/Count of data node descriptors - IPCv2
 */
struct sdma_mode_count {
	u32 count   : 16; /* size of the buffer pointed by this BD */
	u32 status  :  8; /* E,R,I,C,W,D status bits stored here */
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	u32 command :  8; /* command mostly used for channel 0 */
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};

/*
 * Buffer descriptor
 */
struct sdma_buffer_descriptor {
	struct sdma_mode_count  mode;
	u32 buffer_addr;	/* address of the buffer described */
	u32 ext_buffer_addr;	/* extended buffer address */
} __attribute__ ((packed));

/**
 * struct sdma_channel_control - Channel control Block
 *
 * @current_bd_ptr	current buffer descriptor processed
 * @base_bd_ptr		first element of buffer descriptor array
 * @unused		padding. The SDMA engine expects an array of 128 byte
 *			control blocks
 */
struct sdma_channel_control {
	u32 current_bd_ptr;
	u32 base_bd_ptr;
	u32 unused[2];
} __attribute__ ((packed));

/**
 * struct sdma_state_registers - SDMA context for a channel
 *
 * @pc:		program counter
 * @t:		test bit: status of arithmetic & test instruction
 * @rpc:	return program counter
 * @sf:		source fault while loading data
 * @spc:	loop start program counter
 * @df:		destination fault while storing data
 * @epc:	loop end program counter
 * @lm:		loop mode
 */
struct sdma_state_registers {
	u32 pc     :14;
	u32 unused1: 1;
	u32 t      : 1;
	u32 rpc    :14;
	u32 unused0: 1;
	u32 sf     : 1;
	u32 spc    :14;
	u32 unused2: 1;
	u32 df     : 1;
	u32 epc    :14;
	u32 lm     : 2;
} __attribute__ ((packed));

/**
 * struct sdma_context_data - sdma context specific to a channel
 *
 * @channel_state:	channel state bits
 * @gReg:		general registers
 * @mda:		burst dma destination address register
 * @msa:		burst dma source address register
 * @ms:			burst dma status register
 * @md:			burst dma data register
 * @pda:		peripheral dma destination address register
 * @psa:		peripheral dma source address register
 * @ps:			peripheral dma status register
 * @pd:			peripheral dma data register
 * @ca:			CRC polynomial register
 * @cs:			CRC accumulator register
 * @dda:		dedicated core destination address register
 * @dsa:		dedicated core source address register
 * @ds:			dedicated core status register
 * @dd:			dedicated core data register
 */
struct sdma_context_data {
	struct sdma_state_registers  channel_state;
	u32  gReg[8];
	u32  mda;
	u32  msa;
	u32  ms;
	u32  md;
	u32  pda;
	u32  psa;
	u32  ps;
	u32  pd;
	u32  ca;
	u32  cs;
	u32  dda;
	u32  dsa;
	u32  ds;
	u32  dd;
	u32  scratch0;
	u32  scratch1;
	u32  scratch2;
	u32  scratch3;
	u32  scratch4;
	u32  scratch5;
	u32  scratch6;
	u32  scratch7;
} __attribute__ ((packed));

#define NUM_BD (int)(PAGE_SIZE / sizeof(struct sdma_buffer_descriptor))

struct sdma_engine;

/**
 * struct sdma_channel - housekeeping for a SDMA channel
 *
 * @sdma		pointer to the SDMA engine for this channel
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 * @channel		the channel number, matches dmaengine chan_id + 1
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 * @direction		transfer type. Needed for setting SDMA script
 * @peripheral_type	Peripheral type. Needed for setting SDMA script
 * @event_id0		aka dma request line
 * @event_id1		for channels that use 2 events
 * @word_size		peripheral access size
 * @buf_tail		ID of the buffer that was processed
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 * @buf_ptail		ID of the previous buffer that was processed
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 * @num_bd		max NUM_BD. number of descriptors currently handling
 */
struct sdma_channel {
	struct sdma_engine		*sdma;
	unsigned int			channel;
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	enum dma_transfer_direction		direction;
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	enum sdma_peripheral_type	peripheral_type;
	unsigned int			event_id0;
	unsigned int			event_id1;
	enum dma_slave_buswidth		word_size;
	unsigned int			buf_tail;
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	unsigned int			buf_ptail;
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	unsigned int			num_bd;
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	unsigned int			period_len;
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	struct sdma_buffer_descriptor	*bd;
	dma_addr_t			bd_phys;
	unsigned int			pc_from_device, pc_to_device;
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	unsigned int			device_to_device;
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	unsigned long			flags;
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	dma_addr_t			per_address, per_address2;
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	unsigned long			event_mask[2];
	unsigned long			watermark_level;
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	u32				shp_addr, per_addr;
	struct dma_chan			chan;
	spinlock_t			lock;
	struct dma_async_tx_descriptor	desc;
	enum dma_status			status;
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	unsigned int			chn_count;
	unsigned int			chn_real_count;
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	struct tasklet_struct		tasklet;
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	struct imx_dma_data		data;
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};

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#define IMX_DMA_SG_LOOP		BIT(0)
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#define MAX_DMA_CHANNELS 32
#define MXC_SDMA_DEFAULT_PRIORITY 1
#define MXC_SDMA_MIN_PRIORITY 1
#define MXC_SDMA_MAX_PRIORITY 7

#define SDMA_FIRMWARE_MAGIC 0x414d4453

/**
 * struct sdma_firmware_header - Layout of the firmware image
 *
 * @magic		"SDMA"
 * @version_major	increased whenever layout of struct sdma_script_start_addrs
 *			changes.
 * @version_minor	firmware minor version (for binary compatible changes)
 * @script_addrs_start	offset of struct sdma_script_start_addrs in this image
 * @num_script_addrs	Number of script addresses in this image
 * @ram_code_start	offset of SDMA ram image in this firmware image
 * @ram_code_size	size of SDMA ram image
 * @script_addrs	Stores the start address of the SDMA scripts
 *			(in SDMA memory space)
 */
struct sdma_firmware_header {
	u32	magic;
	u32	version_major;
	u32	version_minor;
	u32	script_addrs_start;
	u32	num_script_addrs;
	u32	ram_code_start;
	u32	ram_code_size;
};

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struct sdma_driver_data {
	int chnenbl0;
	int num_events;
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	struct sdma_script_start_addrs	*script_addrs;
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};

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struct sdma_engine {
	struct device			*dev;
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	struct device_dma_parameters	dma_parms;
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	struct sdma_channel		channel[MAX_DMA_CHANNELS];
	struct sdma_channel_control	*channel_control;
	void __iomem			*regs;
	struct sdma_context_data	*context;
	dma_addr_t			context_phys;
	struct dma_device		dma_device;
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	struct clk			*clk_ipg;
	struct clk			*clk_ahb;
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	spinlock_t			channel_0_lock;
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	u32				script_number;
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	struct sdma_script_start_addrs	*script_addrs;
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	const struct sdma_driver_data	*drvdata;
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	u32				spba_start_addr;
	u32				spba_end_addr;
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	unsigned int			irq;
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};

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static struct sdma_driver_data sdma_imx31 = {
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	.chnenbl0 = SDMA_CHNENBL0_IMX31,
	.num_events = 32,
};

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static struct sdma_script_start_addrs sdma_script_imx25 = {
	.ap_2_ap_addr = 729,
	.uart_2_mcu_addr = 904,
	.per_2_app_addr = 1255,
	.mcu_2_app_addr = 834,
	.uartsh_2_mcu_addr = 1120,
	.per_2_shp_addr = 1329,
	.mcu_2_shp_addr = 1048,
	.ata_2_mcu_addr = 1560,
	.mcu_2_ata_addr = 1479,
	.app_2_per_addr = 1189,
	.app_2_mcu_addr = 770,
	.shp_2_per_addr = 1407,
	.shp_2_mcu_addr = 979,
};

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static struct sdma_driver_data sdma_imx25 = {
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	.chnenbl0 = SDMA_CHNENBL0_IMX35,
	.num_events = 48,
	.script_addrs = &sdma_script_imx25,
};

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static struct sdma_driver_data sdma_imx35 = {
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	.chnenbl0 = SDMA_CHNENBL0_IMX35,
	.num_events = 48,
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};

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static struct sdma_script_start_addrs sdma_script_imx51 = {
	.ap_2_ap_addr = 642,
	.uart_2_mcu_addr = 817,
	.mcu_2_app_addr = 747,
	.mcu_2_shp_addr = 961,
	.ata_2_mcu_addr = 1473,
	.mcu_2_ata_addr = 1392,
	.app_2_per_addr = 1033,
	.app_2_mcu_addr = 683,
	.shp_2_per_addr = 1251,
	.shp_2_mcu_addr = 892,
};

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static struct sdma_driver_data sdma_imx51 = {
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	.chnenbl0 = SDMA_CHNENBL0_IMX35,
	.num_events = 48,
	.script_addrs = &sdma_script_imx51,
};

static struct sdma_script_start_addrs sdma_script_imx53 = {
	.ap_2_ap_addr = 642,
	.app_2_mcu_addr = 683,
	.mcu_2_app_addr = 747,
	.uart_2_mcu_addr = 817,
	.shp_2_mcu_addr = 891,
	.mcu_2_shp_addr = 960,
	.uartsh_2_mcu_addr = 1032,
	.spdif_2_mcu_addr = 1100,
	.mcu_2_spdif_addr = 1134,
	.firi_2_mcu_addr = 1193,
	.mcu_2_firi_addr = 1290,
};

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static struct sdma_driver_data sdma_imx53 = {
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	.chnenbl0 = SDMA_CHNENBL0_IMX35,
	.num_events = 48,
	.script_addrs = &sdma_script_imx53,
};

static struct sdma_script_start_addrs sdma_script_imx6q = {
	.ap_2_ap_addr = 642,
	.uart_2_mcu_addr = 817,
	.mcu_2_app_addr = 747,
	.per_2_per_addr = 6331,
	.uartsh_2_mcu_addr = 1032,
	.mcu_2_shp_addr = 960,
	.app_2_mcu_addr = 683,
	.shp_2_mcu_addr = 891,
	.spdif_2_mcu_addr = 1100,
	.mcu_2_spdif_addr = 1134,
};

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static struct sdma_driver_data sdma_imx6q = {
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	.chnenbl0 = SDMA_CHNENBL0_IMX35,
	.num_events = 48,
	.script_addrs = &sdma_script_imx6q,
};

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static struct sdma_script_start_addrs sdma_script_imx7d = {
	.ap_2_ap_addr = 644,
	.uart_2_mcu_addr = 819,
	.mcu_2_app_addr = 749,
	.uartsh_2_mcu_addr = 1034,
	.mcu_2_shp_addr = 962,
	.app_2_mcu_addr = 685,
	.shp_2_mcu_addr = 893,
	.spdif_2_mcu_addr = 1102,
	.mcu_2_spdif_addr = 1136,
};

static struct sdma_driver_data sdma_imx7d = {
	.chnenbl0 = SDMA_CHNENBL0_IMX35,
	.num_events = 48,
	.script_addrs = &sdma_script_imx7d,
};

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static const struct platform_device_id sdma_devtypes[] = {
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	{
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		.name = "imx25-sdma",
		.driver_data = (unsigned long)&sdma_imx25,
	}, {
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		.name = "imx31-sdma",
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		.driver_data = (unsigned long)&sdma_imx31,
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	}, {
		.name = "imx35-sdma",
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		.driver_data = (unsigned long)&sdma_imx35,
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	}, {
		.name = "imx51-sdma",
		.driver_data = (unsigned long)&sdma_imx51,
	}, {
		.name = "imx53-sdma",
		.driver_data = (unsigned long)&sdma_imx53,
	}, {
		.name = "imx6q-sdma",
		.driver_data = (unsigned long)&sdma_imx6q,
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	}, {
		.name = "imx7d-sdma",
		.driver_data = (unsigned long)&sdma_imx7d,
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	}, {
		/* sentinel */
	}
};
MODULE_DEVICE_TABLE(platform, sdma_devtypes);

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static const struct of_device_id sdma_dt_ids[] = {
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	{ .compatible = "fsl,imx6q-sdma", .data = &sdma_imx6q, },
	{ .compatible = "fsl,imx53-sdma", .data = &sdma_imx53, },
	{ .compatible = "fsl,imx51-sdma", .data = &sdma_imx51, },
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	{ .compatible = "fsl,imx35-sdma", .data = &sdma_imx35, },
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	{ .compatible = "fsl,imx31-sdma", .data = &sdma_imx31, },
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	{ .compatible = "fsl,imx25-sdma", .data = &sdma_imx25, },
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	{ .compatible = "fsl,imx7d-sdma", .data = &sdma_imx7d, },
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	{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, sdma_dt_ids);

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#define SDMA_H_CONFIG_DSPDMA	BIT(12) /* indicates if the DSPDMA is used */
#define SDMA_H_CONFIG_RTD_PINS	BIT(11) /* indicates if Real-Time Debug pins are enabled */
#define SDMA_H_CONFIG_ACR	BIT(4)  /* indicates if AHB freq /core freq = 2 or 1 */
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#define SDMA_H_CONFIG_CSM	(3)       /* indicates which context switch mode is selected*/

static inline u32 chnenbl_ofs(struct sdma_engine *sdma, unsigned int event)
{
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	u32 chnenbl0 = sdma->drvdata->chnenbl0;
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	return chnenbl0 + event * 4;
}

static int sdma_config_ownership(struct sdma_channel *sdmac,
		bool event_override, bool mcu_override, bool dsp_override)
{
	struct sdma_engine *sdma = sdmac->sdma;
	int channel = sdmac->channel;
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	unsigned long evt, mcu, dsp;
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	if (event_override && mcu_override && dsp_override)
		return -EINVAL;

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	evt = readl_relaxed(sdma->regs + SDMA_H_EVTOVR);
	mcu = readl_relaxed(sdma->regs + SDMA_H_HOSTOVR);
	dsp = readl_relaxed(sdma->regs + SDMA_H_DSPOVR);
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	if (dsp_override)
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		__clear_bit(channel, &dsp);
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	else
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		__set_bit(channel, &dsp);
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	if (event_override)
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		__clear_bit(channel, &evt);
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	else
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		__set_bit(channel, &evt);
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	if (mcu_override)
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		__clear_bit(channel, &mcu);
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	else
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		__set_bit(channel, &mcu);
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	writel_relaxed(evt, sdma->regs + SDMA_H_EVTOVR);
	writel_relaxed(mcu, sdma->regs + SDMA_H_HOSTOVR);
	writel_relaxed(dsp, sdma->regs + SDMA_H_DSPOVR);
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	return 0;
}

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static void sdma_enable_channel(struct sdma_engine *sdma, int channel)
{
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	writel(BIT(channel), sdma->regs + SDMA_H_START);
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}

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/*
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 * sdma_run_channel0 - run a channel and wait till it's done
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 */
597
static int sdma_run_channel0(struct sdma_engine *sdma)
598 599
{
	int ret;
600
	u32 reg;
601

602
	sdma_enable_channel(sdma, 0);
603

604 605 606
	ret = readl_relaxed_poll_timeout_atomic(sdma->regs + SDMA_H_STATSTOP,
						reg, !(reg & 1), 1, 500);
	if (ret)
607
		dev_err(sdma->dev, "Timeout waiting for CH0 ready\n");
608

609 610 611 612
	/* Set bits of CONFIG register with dynamic context switching */
	if (readl(sdma->regs + SDMA_H_CONFIG) == 0)
		writel_relaxed(SDMA_H_CONFIG_CSM, sdma->regs + SDMA_H_CONFIG);

613
	return ret;
614 615 616 617 618 619 620 621 622
}

static int sdma_load_script(struct sdma_engine *sdma, void *buf, int size,
		u32 address)
{
	struct sdma_buffer_descriptor *bd0 = sdma->channel[0].bd;
	void *buf_virt;
	dma_addr_t buf_phys;
	int ret;
623
	unsigned long flags;
624

625 626 627
	buf_virt = dma_alloc_coherent(NULL,
			size,
			&buf_phys, GFP_KERNEL);
628
	if (!buf_virt) {
629
		return -ENOMEM;
630
	}
631

632 633
	spin_lock_irqsave(&sdma->channel_0_lock, flags);

634 635 636 637 638 639 640 641
	bd0->mode.command = C0_SETPM;
	bd0->mode.status = BD_DONE | BD_INTR | BD_WRAP | BD_EXTD;
	bd0->mode.count = size / 2;
	bd0->buffer_addr = buf_phys;
	bd0->ext_buffer_addr = address;

	memcpy(buf_virt, buf, size);

642
	ret = sdma_run_channel0(sdma);
643

644
	spin_unlock_irqrestore(&sdma->channel_0_lock, flags);
645

646
	dma_free_coherent(NULL, size, buf_virt, buf_phys);
647

648 649 650 651 652 653 654
	return ret;
}

static void sdma_event_enable(struct sdma_channel *sdmac, unsigned int event)
{
	struct sdma_engine *sdma = sdmac->sdma;
	int channel = sdmac->channel;
655
	unsigned long val;
656 657
	u32 chnenbl = chnenbl_ofs(sdma, event);

658
	val = readl_relaxed(sdma->regs + chnenbl);
659
	__set_bit(channel, &val);
660
	writel_relaxed(val, sdma->regs + chnenbl);
661 662 663 664 665 666 667
}

static void sdma_event_disable(struct sdma_channel *sdmac, unsigned int event)
{
	struct sdma_engine *sdma = sdmac->sdma;
	int channel = sdmac->channel;
	u32 chnenbl = chnenbl_ofs(sdma, event);
668
	unsigned long val;
669

670
	val = readl_relaxed(sdma->regs + chnenbl);
671
	__clear_bit(channel, &val);
672
	writel_relaxed(val, sdma->regs + chnenbl);
673 674
}

675
static void sdma_update_channel_loop(struct sdma_channel *sdmac)
676 677
{
	struct sdma_buffer_descriptor *bd;
678 679
	int error = 0;
	enum dma_status	old_status = sdmac->status;
680 681 682 683 684 685 686 687 688 689 690

	/*
	 * loop mode. Iterate over descriptors, re-setup them and
	 * call callback function.
	 */
	while (1) {
		bd = &sdmac->bd[sdmac->buf_tail];

		if (bd->mode.status & BD_DONE)
			break;

691 692
		if (bd->mode.status & BD_RROR) {
			bd->mode.status &= ~BD_RROR;
693
			sdmac->status = DMA_ERROR;
694 695
			error = -EIO;
		}
696

697 698 699 700 701 702
	       /*
		* We use bd->mode.count to calculate the residue, since contains
		* the number of bytes present in the current buffer descriptor.
		*/

		sdmac->chn_real_count = bd->mode.count;
703
		bd->mode.status |= BD_DONE;
704
		bd->mode.count = sdmac->period_len;
705 706
		sdmac->buf_ptail = sdmac->buf_tail;
		sdmac->buf_tail = (sdmac->buf_tail + 1) % sdmac->num_bd;
707 708 709 710 711 712 713 714

		/*
		 * The callback is called from the interrupt context in order
		 * to reduce latency and to avoid the risk of altering the
		 * SDMA transaction status by the time the client tasklet is
		 * executed.
		 */

715
		dmaengine_desc_get_callback_invoke(&sdmac->desc, NULL);
716

717 718
		if (error)
			sdmac->status = old_status;
719 720 721
	}
}

722
static void mxc_sdma_handle_channel_normal(unsigned long data)
723
{
724
	struct sdma_channel *sdmac = (struct sdma_channel *) data;
725 726 727
	struct sdma_buffer_descriptor *bd;
	int i, error = 0;

728
	sdmac->chn_real_count = 0;
729 730 731 732 733 734 735 736 737
	/*
	 * non loop mode. Iterate over all descriptors, collect
	 * errors and call callback function
	 */
	for (i = 0; i < sdmac->num_bd; i++) {
		bd = &sdmac->bd[i];

		 if (bd->mode.status & (BD_DONE | BD_RROR))
			error = -EIO;
738
		 sdmac->chn_real_count += bd->mode.count;
739 740 741 742 743
	}

	if (error)
		sdmac->status = DMA_ERROR;
	else
744
		sdmac->status = DMA_COMPLETE;
745

746
	dma_cookie_complete(&sdmac->desc);
747 748

	dmaengine_desc_get_callback_invoke(&sdmac->desc, NULL);
749 750 751 752 753
}

static irqreturn_t sdma_int_handler(int irq, void *dev_id)
{
	struct sdma_engine *sdma = dev_id;
754
	unsigned long stat;
755

756 757
	stat = readl_relaxed(sdma->regs + SDMA_H_INTR);
	writel_relaxed(stat, sdma->regs + SDMA_H_INTR);
758 759
	/* channel 0 is special and not handled here, see run_channel0() */
	stat &= ~1;
760 761 762 763 764

	while (stat) {
		int channel = fls(stat) - 1;
		struct sdma_channel *sdmac = &sdma->channel[channel];

765 766
		if (sdmac->flags & IMX_DMA_SG_LOOP)
			sdma_update_channel_loop(sdmac);
767 768
		else
			tasklet_schedule(&sdmac->tasklet);
769

770
		__clear_bit(channel, &stat);
771 772 773 774 775 776 777 778 779 780 781 782 783 784 785 786 787
	}

	return IRQ_HANDLED;
}

/*
 * sets the pc of SDMA script according to the peripheral type
 */
static void sdma_get_pc(struct sdma_channel *sdmac,
		enum sdma_peripheral_type peripheral_type)
{
	struct sdma_engine *sdma = sdmac->sdma;
	int per_2_emi = 0, emi_2_per = 0;
	/*
	 * These are needed once we start to support transfers between
	 * two peripherals or memory-to-memory transfers
	 */
788
	int per_2_per = 0;
789 790 791

	sdmac->pc_from_device = 0;
	sdmac->pc_to_device = 0;
792
	sdmac->device_to_device = 0;
793 794 795 796 797 798 799 800 801 802 803 804 805 806 807 808 809 810 811 812 813 814 815 816 817 818 819

	switch (peripheral_type) {
	case IMX_DMATYPE_MEMORY:
		break;
	case IMX_DMATYPE_DSP:
		emi_2_per = sdma->script_addrs->bp_2_ap_addr;
		per_2_emi = sdma->script_addrs->ap_2_bp_addr;
		break;
	case IMX_DMATYPE_FIRI:
		per_2_emi = sdma->script_addrs->firi_2_mcu_addr;
		emi_2_per = sdma->script_addrs->mcu_2_firi_addr;
		break;
	case IMX_DMATYPE_UART:
		per_2_emi = sdma->script_addrs->uart_2_mcu_addr;
		emi_2_per = sdma->script_addrs->mcu_2_app_addr;
		break;
	case IMX_DMATYPE_UART_SP:
		per_2_emi = sdma->script_addrs->uartsh_2_mcu_addr;
		emi_2_per = sdma->script_addrs->mcu_2_shp_addr;
		break;
	case IMX_DMATYPE_ATA:
		per_2_emi = sdma->script_addrs->ata_2_mcu_addr;
		emi_2_per = sdma->script_addrs->mcu_2_ata_addr;
		break;
	case IMX_DMATYPE_CSPI:
	case IMX_DMATYPE_EXT:
	case IMX_DMATYPE_SSI:
820
	case IMX_DMATYPE_SAI:
821 822 823
		per_2_emi = sdma->script_addrs->app_2_mcu_addr;
		emi_2_per = sdma->script_addrs->mcu_2_app_addr;
		break;
824 825 826 827
	case IMX_DMATYPE_SSI_DUAL:
		per_2_emi = sdma->script_addrs->ssish_2_mcu_addr;
		emi_2_per = sdma->script_addrs->mcu_2_ssish_addr;
		break;
828 829 830 831 832 833 834 835 836 837 838 839 840 841
	case IMX_DMATYPE_SSI_SP:
	case IMX_DMATYPE_MMC:
	case IMX_DMATYPE_SDHC:
	case IMX_DMATYPE_CSPI_SP:
	case IMX_DMATYPE_ESAI:
	case IMX_DMATYPE_MSHC_SP:
		per_2_emi = sdma->script_addrs->shp_2_mcu_addr;
		emi_2_per = sdma->script_addrs->mcu_2_shp_addr;
		break;
	case IMX_DMATYPE_ASRC:
		per_2_emi = sdma->script_addrs->asrc_2_mcu_addr;
		emi_2_per = sdma->script_addrs->asrc_2_mcu_addr;
		per_2_per = sdma->script_addrs->per_2_per_addr;
		break;
842 843 844 845 846
	case IMX_DMATYPE_ASRC_SP:
		per_2_emi = sdma->script_addrs->shp_2_mcu_addr;
		emi_2_per = sdma->script_addrs->mcu_2_shp_addr;
		per_2_per = sdma->script_addrs->per_2_per_addr;
		break;
847 848 849 850 851 852 853 854 855 856 857 858 859 860 861 862 863 864 865 866
	case IMX_DMATYPE_MSHC:
		per_2_emi = sdma->script_addrs->mshc_2_mcu_addr;
		emi_2_per = sdma->script_addrs->mcu_2_mshc_addr;
		break;
	case IMX_DMATYPE_CCM:
		per_2_emi = sdma->script_addrs->dptc_dvfs_addr;
		break;
	case IMX_DMATYPE_SPDIF:
		per_2_emi = sdma->script_addrs->spdif_2_mcu_addr;
		emi_2_per = sdma->script_addrs->mcu_2_spdif_addr;
		break;
	case IMX_DMATYPE_IPU_MEMORY:
		emi_2_per = sdma->script_addrs->ext_mem_2_ipu_addr;
		break;
	default:
		break;
	}

	sdmac->pc_from_device = per_2_emi;
	sdmac->pc_to_device = emi_2_per;
867
	sdmac->device_to_device = per_2_per;
868 869 870 871 872 873 874 875 876 877
}

static int sdma_load_context(struct sdma_channel *sdmac)
{
	struct sdma_engine *sdma = sdmac->sdma;
	int channel = sdmac->channel;
	int load_address;
	struct sdma_context_data *context = sdma->context;
	struct sdma_buffer_descriptor *bd0 = sdma->channel[0].bd;
	int ret;
878
	unsigned long flags;
879

880
	if (sdmac->direction == DMA_DEV_TO_MEM)
881
		load_address = sdmac->pc_from_device;
882 883 884
	else if (sdmac->direction == DMA_DEV_TO_DEV)
		load_address = sdmac->device_to_device;
	else
885 886 887 888 889 890
		load_address = sdmac->pc_to_device;

	if (load_address < 0)
		return load_address;

	dev_dbg(sdma->dev, "load_address = %d\n", load_address);
891
	dev_dbg(sdma->dev, "wml = 0x%08x\n", (u32)sdmac->watermark_level);
892 893
	dev_dbg(sdma->dev, "shp_addr = 0x%08x\n", sdmac->shp_addr);
	dev_dbg(sdma->dev, "per_addr = 0x%08x\n", sdmac->per_addr);
894 895
	dev_dbg(sdma->dev, "event_mask0 = 0x%08x\n", (u32)sdmac->event_mask[0]);
	dev_dbg(sdma->dev, "event_mask1 = 0x%08x\n", (u32)sdmac->event_mask[1]);
896

897
	spin_lock_irqsave(&sdma->channel_0_lock, flags);
898

899 900 901 902 903 904
	memset(context, 0, sizeof(*context));
	context->channel_state.pc = load_address;

	/* Send by context the event mask,base address for peripheral
	 * and watermark level
	 */
905 906
	context->gReg[0] = sdmac->event_mask[1];
	context->gReg[1] = sdmac->event_mask[0];
907 908 909 910 911 912 913 914 915
	context->gReg[2] = sdmac->per_addr;
	context->gReg[6] = sdmac->shp_addr;
	context->gReg[7] = sdmac->watermark_level;

	bd0->mode.command = C0_SETDM;
	bd0->mode.status = BD_DONE | BD_INTR | BD_WRAP | BD_EXTD;
	bd0->mode.count = sizeof(*context) / 4;
	bd0->buffer_addr = sdma->context_phys;
	bd0->ext_buffer_addr = 2048 + (sizeof(*context) / 4) * channel;
916
	ret = sdma_run_channel0(sdma);
917

918
	spin_unlock_irqrestore(&sdma->channel_0_lock, flags);
919

920 921 922
	return ret;
}

923 924 925 926 927 928
static struct sdma_channel *to_sdma_chan(struct dma_chan *chan)
{
	return container_of(chan, struct sdma_channel, chan);
}

static int sdma_disable_channel(struct dma_chan *chan)
929
{
930
	struct sdma_channel *sdmac = to_sdma_chan(chan);
931 932 933
	struct sdma_engine *sdma = sdmac->sdma;
	int channel = sdmac->channel;

934
	writel_relaxed(BIT(channel), sdma->regs + SDMA_H_STATSTOP);
935
	sdmac->status = DMA_ERROR;
936 937

	return 0;
938 939
}

940 941 942 943 944 945 946 947 948 949 950 951 952 953 954 955 956 957 958 959 960 961 962 963 964 965 966 967 968 969 970 971 972 973 974 975 976 977 978 979
static void sdma_set_watermarklevel_for_p2p(struct sdma_channel *sdmac)
{
	struct sdma_engine *sdma = sdmac->sdma;

	int lwml = sdmac->watermark_level & SDMA_WATERMARK_LEVEL_LWML;
	int hwml = (sdmac->watermark_level & SDMA_WATERMARK_LEVEL_HWML) >> 16;

	set_bit(sdmac->event_id0 % 32, &sdmac->event_mask[1]);
	set_bit(sdmac->event_id1 % 32, &sdmac->event_mask[0]);

	if (sdmac->event_id0 > 31)
		sdmac->watermark_level |= SDMA_WATERMARK_LEVEL_LWE;

	if (sdmac->event_id1 > 31)
		sdmac->watermark_level |= SDMA_WATERMARK_LEVEL_HWE;

	/*
	 * If LWML(src_maxburst) > HWML(dst_maxburst), we need
	 * swap LWML and HWML of INFO(A.3.2.5.1), also need swap
	 * r0(event_mask[1]) and r1(event_mask[0]).
	 */
	if (lwml > hwml) {
		sdmac->watermark_level &= ~(SDMA_WATERMARK_LEVEL_LWML |
						SDMA_WATERMARK_LEVEL_HWML);
		sdmac->watermark_level |= hwml;
		sdmac->watermark_level |= lwml << 16;
		swap(sdmac->event_mask[0], sdmac->event_mask[1]);
	}

	if (sdmac->per_address2 >= sdma->spba_start_addr &&
			sdmac->per_address2 <= sdma->spba_end_addr)
		sdmac->watermark_level |= SDMA_WATERMARK_LEVEL_SP;

	if (sdmac->per_address >= sdma->spba_start_addr &&
			sdmac->per_address <= sdma->spba_end_addr)
		sdmac->watermark_level |= SDMA_WATERMARK_LEVEL_DP;

	sdmac->watermark_level |= SDMA_WATERMARK_LEVEL_CONT;
}

980
static int sdma_config_channel(struct dma_chan *chan)
981
{
982
	struct sdma_channel *sdmac = to_sdma_chan(chan);
983 984
	int ret;

985
	sdma_disable_channel(chan);
986

987 988
	sdmac->event_mask[0] = 0;
	sdmac->event_mask[1] = 0;
989 990 991 992
	sdmac->shp_addr = 0;
	sdmac->per_addr = 0;

	if (sdmac->event_id0) {
993
		if (sdmac->event_id0 >= sdmac->sdma->drvdata->num_events)
994 995 996 997
			return -EINVAL;
		sdma_event_enable(sdmac, sdmac->event_id0);
	}

998 999 1000 1001 1002 1003
	if (sdmac->event_id1) {
		if (sdmac->event_id1 >= sdmac->sdma->drvdata->num_events)
			return -EINVAL;
		sdma_event_enable(sdmac, sdmac->event_id1);
	}

1004 1005 1006 1007 1008 1009 1010 1011 1012 1013 1014 1015 1016 1017 1018 1019 1020 1021
	switch (sdmac->peripheral_type) {
	case IMX_DMATYPE_DSP:
		sdma_config_ownership(sdmac, false, true, true);
		break;
	case IMX_DMATYPE_MEMORY:
		sdma_config_ownership(sdmac, false, true, false);
		break;
	default:
		sdma_config_ownership(sdmac, true, true, false);
		break;
	}

	sdma_get_pc(sdmac, sdmac->peripheral_type);

	if ((sdmac->peripheral_type != IMX_DMATYPE_MEMORY) &&
			(sdmac->peripheral_type != IMX_DMATYPE_DSP)) {
		/* Handle multiple event channels differently */
		if (sdmac->event_id1) {
1022 1023 1024 1025
			if (sdmac->peripheral_type == IMX_DMATYPE_ASRC_SP ||
			    sdmac->peripheral_type == IMX_DMATYPE_ASRC)
				sdma_set_watermarklevel_for_p2p(sdmac);
		} else
1026
			__set_bit(sdmac->event_id0, sdmac->event_mask);
1027

1028 1029
		/* Address */
		sdmac->shp_addr = sdmac->per_address;
1030
		sdmac->per_addr = sdmac->per_address2;
1031 1032 1033 1034 1035 1036 1037 1038 1039 1040 1041 1042 1043 1044 1045 1046 1047 1048 1049 1050
	} else {
		sdmac->watermark_level = 0; /* FIXME: M3_BASE_ADDRESS */
	}

	ret = sdma_load_context(sdmac);

	return ret;
}

static int sdma_set_channel_priority(struct sdma_channel *sdmac,
		unsigned int priority)
{
	struct sdma_engine *sdma = sdmac->sdma;
	int channel = sdmac->channel;

	if (priority < MXC_SDMA_MIN_PRIORITY
	    || priority > MXC_SDMA_MAX_PRIORITY) {
		return -EINVAL;
	}

1051
	writel_relaxed(priority, sdma->regs + SDMA_CHNPRI_0 + 4 * channel);
1052 1053 1054 1055 1056 1057 1058 1059 1060 1061

	return 0;
}

static int sdma_request_channel(struct sdma_channel *sdmac)
{
	struct sdma_engine *sdma = sdmac->sdma;
	int channel = sdmac->channel;
	int ret = -EBUSY;

J
Joe Perches 已提交
1062 1063
	sdmac->bd = dma_zalloc_coherent(NULL, PAGE_SIZE, &sdmac->bd_phys,
					GFP_KERNEL);
1064 1065 1066 1067 1068 1069 1070 1071 1072 1073 1074 1075 1076 1077 1078 1079 1080
	if (!sdmac->bd) {
		ret = -ENOMEM;
		goto out;
	}

	sdma->channel_control[channel].base_bd_ptr = sdmac->bd_phys;
	sdma->channel_control[channel].current_bd_ptr = sdmac->bd_phys;

	sdma_set_channel_priority(sdmac, MXC_SDMA_DEFAULT_PRIORITY);
	return 0;
out:

	return ret;
}

static dma_cookie_t sdma_tx_submit(struct dma_async_tx_descriptor *tx)
{
1081
	unsigned long flags;
1082 1083 1084
	struct sdma_channel *sdmac = to_sdma_chan(tx->chan);
	dma_cookie_t cookie;

1085
	spin_lock_irqsave(&sdmac->lock, flags);
1086

1087
	cookie = dma_cookie_assign(tx);
1088

1089
	spin_unlock_irqrestore(&sdmac->lock, flags);
1090 1091 1092 1093 1094 1095 1096 1097 1098 1099 1100 1101 1102 1103 1104 1105 1106 1107 1108 1109 1110 1111 1112 1113 1114 1115 1116 1117

	return cookie;
}

static int sdma_alloc_chan_resources(struct dma_chan *chan)
{
	struct sdma_channel *sdmac = to_sdma_chan(chan);
	struct imx_dma_data *data = chan->private;
	int prio, ret;

	if (!data)
		return -EINVAL;

	switch (data->priority) {
	case DMA_PRIO_HIGH:
		prio = 3;
		break;
	case DMA_PRIO_MEDIUM:
		prio = 2;
		break;
	case DMA_PRIO_LOW:
	default:
		prio = 1;
		break;
	}

	sdmac->peripheral_type = data->peripheral_type;
	sdmac->event_id0 = data->dma_request;
1118
	sdmac->event_id1 = data->dma_request2;
1119

1120 1121 1122 1123 1124 1125
	ret = clk_enable(sdmac->sdma->clk_ipg);
	if (ret)
		return ret;
	ret = clk_enable(sdmac->sdma->clk_ahb);
	if (ret)
		goto disable_clk_ipg;
1126

1127
	ret = sdma_request_channel(sdmac);
1128
	if (ret)
1129
		goto disable_clk_ahb;
1130

1131
	ret = sdma_set_channel_priority(sdmac, prio);
1132
	if (ret)
1133
		goto disable_clk_ahb;
1134 1135 1136 1137 1138 1139 1140

	dma_async_tx_descriptor_init(&sdmac->desc, chan);
	sdmac->desc.tx_submit = sdma_tx_submit;
	/* txd.flags will be overwritten in prep funcs */
	sdmac->desc.flags = DMA_CTRL_ACK;

	return 0;
1141 1142 1143 1144 1145 1146

disable_clk_ahb:
	clk_disable(sdmac->sdma->clk_ahb);
disable_clk_ipg:
	clk_disable(sdmac->sdma->clk_ipg);
	return ret;
1147 1148 1149 1150 1151 1152 1153
}

static void sdma_free_chan_resources(struct dma_chan *chan)
{
	struct sdma_channel *sdmac = to_sdma_chan(chan);
	struct sdma_engine *sdma = sdmac->sdma;

1154
	sdma_disable_channel(chan);
1155 1156 1157 1158 1159 1160 1161 1162 1163 1164 1165 1166 1167

	if (sdmac->event_id0)
		sdma_event_disable(sdmac, sdmac->event_id0);
	if (sdmac->event_id1)
		sdma_event_disable(sdmac, sdmac->event_id1);

	sdmac->event_id0 = 0;
	sdmac->event_id1 = 0;

	sdma_set_channel_priority(sdmac, 0);

	dma_free_coherent(NULL, PAGE_SIZE, sdmac->bd, sdmac->bd_phys);

1168 1169
	clk_disable(sdma->clk_ipg);
	clk_disable(sdma->clk_ahb);
1170 1171 1172 1173
}

static struct dma_async_tx_descriptor *sdma_prep_slave_sg(
		struct dma_chan *chan, struct scatterlist *sgl,
1174
		unsigned int sg_len, enum dma_transfer_direction direction,
1175
		unsigned long flags, void *context)
1176 1177 1178 1179
{
	struct sdma_channel *sdmac = to_sdma_chan(chan);
	struct sdma_engine *sdma = sdmac->sdma;
	int ret, i, count;
1180
	int channel = sdmac->channel;
1181 1182 1183 1184 1185 1186 1187 1188
	struct scatterlist *sg;

	if (sdmac->status == DMA_IN_PROGRESS)
		return NULL;
	sdmac->status = DMA_IN_PROGRESS;

	sdmac->flags = 0;

1189
	sdmac->buf_tail = 0;
1190 1191
	sdmac->buf_ptail = 0;
	sdmac->chn_real_count = 0;
1192

1193 1194 1195 1196 1197 1198 1199 1200 1201 1202 1203 1204 1205 1206 1207
	dev_dbg(sdma->dev, "setting up %d entries for channel %d.\n",
			sg_len, channel);

	sdmac->direction = direction;
	ret = sdma_load_context(sdmac);
	if (ret)
		goto err_out;

	if (sg_len > NUM_BD) {
		dev_err(sdma->dev, "SDMA channel %d: maximum number of sg exceeded: %d > %d\n",
				channel, sg_len, NUM_BD);
		ret = -EINVAL;
		goto err_out;
	}

1208
	sdmac->chn_count = 0;
1209 1210 1211 1212
	for_each_sg(sgl, sg, sg_len, i) {
		struct sdma_buffer_descriptor *bd = &sdmac->bd[i];
		int param;

1213
		bd->buffer_addr = sg->dma_address;
1214

1215
		count = sg_dma_len(sg);
1216 1217 1218 1219 1220 1221 1222 1223 1224

		if (count > 0xffff) {
			dev_err(sdma->dev, "SDMA channel %d: maximum bytes for sg entry exceeded: %d > %d\n",
					channel, count, 0xffff);
			ret = -EINVAL;
			goto err_out;
		}

		bd->mode.count = count;
1225
		sdmac->chn_count += count;
1226 1227 1228 1229 1230

		if (sdmac->word_size > DMA_SLAVE_BUSWIDTH_4_BYTES) {
			ret =  -EINVAL;
			goto err_out;
		}
1231 1232 1233

		switch (sdmac->word_size) {
		case DMA_SLAVE_BUSWIDTH_4_BYTES:
1234
			bd->mode.command = 0;
1235 1236 1237 1238 1239 1240 1241 1242 1243 1244 1245 1246 1247 1248
			if (count & 3 || sg->dma_address & 3)
				return NULL;
			break;
		case DMA_SLAVE_BUSWIDTH_2_BYTES:
			bd->mode.command = 2;
			if (count & 1 || sg->dma_address & 1)
				return NULL;
			break;
		case DMA_SLAVE_BUSWIDTH_1_BYTE:
			bd->mode.command = 1;
			break;
		default:
			return NULL;
		}
1249 1250 1251

		param = BD_DONE | BD_EXTD | BD_CONT;

1252
		if (i + 1 == sg_len) {
1253
			param |= BD_INTR;
1254 1255
			param |= BD_LAST;
			param &= ~BD_CONT;
1256 1257
		}

1258 1259
		dev_dbg(sdma->dev, "entry %d: count: %d dma: %#llx %s%s\n",
				i, count, (u64)sg->dma_address,
1260 1261 1262 1263 1264 1265 1266 1267 1268 1269 1270
				param & BD_WRAP ? "wrap" : "",
				param & BD_INTR ? " intr" : "");

		bd->mode.status = param;
	}

	sdmac->num_bd = sg_len;
	sdma->channel_control[channel].current_bd_ptr = sdmac->bd_phys;

	return &sdmac->desc;
err_out:
1271
	sdmac->status = DMA_ERROR;
1272 1273 1274 1275 1276
	return NULL;
}

static struct dma_async_tx_descriptor *sdma_prep_dma_cyclic(
		struct dma_chan *chan, dma_addr_t dma_addr, size_t buf_len,
1277
		size_t period_len, enum dma_transfer_direction direction,
1278
		unsigned long flags)
1279 1280 1281 1282
{
	struct sdma_channel *sdmac = to_sdma_chan(chan);
	struct sdma_engine *sdma = sdmac->sdma;
	int num_periods = buf_len / period_len;
1283
	int channel = sdmac->channel;
1284 1285 1286 1287 1288 1289 1290 1291 1292
	int ret, i = 0, buf = 0;

	dev_dbg(sdma->dev, "%s channel: %d\n", __func__, channel);

	if (sdmac->status == DMA_IN_PROGRESS)
		return NULL;

	sdmac->status = DMA_IN_PROGRESS;

1293
	sdmac->buf_tail = 0;
1294 1295
	sdmac->buf_ptail = 0;
	sdmac->chn_real_count = 0;
1296
	sdmac->period_len = period_len;
1297

1298 1299 1300 1301 1302 1303 1304 1305 1306 1307 1308 1309 1310 1311 1312 1313 1314 1315 1316 1317 1318 1319 1320 1321 1322 1323 1324 1325 1326 1327 1328 1329 1330 1331 1332 1333 1334
	sdmac->flags |= IMX_DMA_SG_LOOP;
	sdmac->direction = direction;
	ret = sdma_load_context(sdmac);
	if (ret)
		goto err_out;

	if (num_periods > NUM_BD) {
		dev_err(sdma->dev, "SDMA channel %d: maximum number of sg exceeded: %d > %d\n",
				channel, num_periods, NUM_BD);
		goto err_out;
	}

	if (period_len > 0xffff) {
		dev_err(sdma->dev, "SDMA channel %d: maximum period size exceeded: %d > %d\n",
				channel, period_len, 0xffff);
		goto err_out;
	}

	while (buf < buf_len) {
		struct sdma_buffer_descriptor *bd = &sdmac->bd[i];
		int param;

		bd->buffer_addr = dma_addr;

		bd->mode.count = period_len;

		if (sdmac->word_size > DMA_SLAVE_BUSWIDTH_4_BYTES)
			goto err_out;
		if (sdmac->word_size == DMA_SLAVE_BUSWIDTH_4_BYTES)
			bd->mode.command = 0;
		else
			bd->mode.command = sdmac->word_size;

		param = BD_DONE | BD_EXTD | BD_CONT | BD_INTR;
		if (i + 1 == num_periods)
			param |= BD_WRAP;

1335 1336
		dev_dbg(sdma->dev, "entry %d: count: %d dma: %#llx %s%s\n",
				i, period_len, (u64)dma_addr,
1337 1338 1339 1340 1341 1342 1343 1344 1345 1346 1347 1348 1349 1350 1351 1352 1353 1354 1355 1356
				param & BD_WRAP ? "wrap" : "",
				param & BD_INTR ? " intr" : "");

		bd->mode.status = param;

		dma_addr += period_len;
		buf += period_len;

		i++;
	}

	sdmac->num_bd = num_periods;
	sdma->channel_control[channel].current_bd_ptr = sdmac->bd_phys;

	return &sdmac->desc;
err_out:
	sdmac->status = DMA_ERROR;
	return NULL;
}

1357 1358
static int sdma_config(struct dma_chan *chan,
		       struct dma_slave_config *dmaengine_cfg)
1359 1360 1361
{
	struct sdma_channel *sdmac = to_sdma_chan(chan);

1362 1363 1364 1365 1366
	if (dmaengine_cfg->direction == DMA_DEV_TO_MEM) {
		sdmac->per_address = dmaengine_cfg->src_addr;
		sdmac->watermark_level = dmaengine_cfg->src_maxburst *
			dmaengine_cfg->src_addr_width;
		sdmac->word_size = dmaengine_cfg->src_addr_width;
1367 1368 1369 1370 1371 1372 1373 1374
	} else if (dmaengine_cfg->direction == DMA_DEV_TO_DEV) {
		sdmac->per_address2 = dmaengine_cfg->src_addr;
		sdmac->per_address = dmaengine_cfg->dst_addr;
		sdmac->watermark_level = dmaengine_cfg->src_maxburst &
			SDMA_WATERMARK_LEVEL_LWML;
		sdmac->watermark_level |= (dmaengine_cfg->dst_maxburst << 16) &
			SDMA_WATERMARK_LEVEL_HWML;
		sdmac->word_size = dmaengine_cfg->dst_addr_width;
1375 1376 1377 1378 1379 1380 1381 1382
	} else {
		sdmac->per_address = dmaengine_cfg->dst_addr;
		sdmac->watermark_level = dmaengine_cfg->dst_maxburst *
			dmaengine_cfg->dst_addr_width;
		sdmac->word_size = dmaengine_cfg->dst_addr_width;
	}
	sdmac->direction = dmaengine_cfg->direction;
	return sdma_config_channel(chan);
1383 1384 1385
}

static enum dma_status sdma_tx_status(struct dma_chan *chan,
1386 1387
				      dma_cookie_t cookie,
				      struct dma_tx_state *txstate)
1388 1389
{
	struct sdma_channel *sdmac = to_sdma_chan(chan);
1390 1391 1392
	u32 residue;

	if (sdmac->flags & IMX_DMA_SG_LOOP)
1393
		residue = (sdmac->num_bd - sdmac->buf_ptail) *
1394
			   sdmac->period_len - sdmac->chn_real_count;
1395 1396
	else
		residue = sdmac->chn_count - sdmac->chn_real_count;
1397

1398
	dma_set_tx_state(txstate, chan->completed_cookie, chan->cookie,
1399
			 residue);
1400

1401
	return sdmac->status;
1402 1403 1404 1405
}

static void sdma_issue_pending(struct dma_chan *chan)
{
1406 1407 1408 1409 1410
	struct sdma_channel *sdmac = to_sdma_chan(chan);
	struct sdma_engine *sdma = sdmac->sdma;

	if (sdmac->status == DMA_IN_PROGRESS)
		sdma_enable_channel(sdma, sdmac->channel);
1411 1412
}

1413
#define SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1	34
1414
#define SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V2	38
1415
#define SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V3	41
1416
#define SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V4	42
1417 1418 1419 1420 1421 1422 1423 1424

static void sdma_add_scripts(struct sdma_engine *sdma,
		const struct sdma_script_start_addrs *addr)
{
	s32 *addr_arr = (u32 *)addr;
	s32 *saddr_arr = (u32 *)sdma->script_addrs;
	int i;

1425 1426 1427 1428
	/* use the default firmware in ROM if missing external firmware */
	if (!sdma->script_number)
		sdma->script_number = SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1;

1429
	for (i = 0; i < sdma->script_number; i++)
1430 1431 1432 1433
		if (addr_arr[i] > 0)
			saddr_arr[i] = addr_arr[i];
}

1434
static void sdma_load_firmware(const struct firmware *fw, void *context)
1435
{
1436
	struct sdma_engine *sdma = context;
1437 1438 1439 1440
	const struct sdma_firmware_header *header;
	const struct sdma_script_start_addrs *addr;
	unsigned short *ram_code;

1441
	if (!fw) {
1442 1443
		dev_info(sdma->dev, "external firmware not found, using ROM firmware\n");
		/* In this case we just use the ROM firmware. */
1444 1445
		return;
	}
1446 1447 1448 1449 1450 1451 1452 1453 1454 1455

	if (fw->size < sizeof(*header))
		goto err_firmware;

	header = (struct sdma_firmware_header *)fw->data;

	if (header->magic != SDMA_FIRMWARE_MAGIC)
		goto err_firmware;
	if (header->ram_code_start + header->ram_code_size > fw->size)
		goto err_firmware;
1456
	switch (header->version_major) {
A
Asaf Vertz 已提交
1457 1458 1459 1460 1461 1462
	case 1:
		sdma->script_number = SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1;
		break;
	case 2:
		sdma->script_number = SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V2;
		break;
1463 1464 1465
	case 3:
		sdma->script_number = SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V3;
		break;
1466 1467 1468
	case 4:
		sdma->script_number = SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V4;
		break;
A
Asaf Vertz 已提交
1469 1470 1471
	default:
		dev_err(sdma->dev, "unknown firmware version\n");
		goto err_firmware;
1472
	}
1473 1474 1475 1476

	addr = (void *)header + header->script_addrs_start;
	ram_code = (void *)header + header->ram_code_start;

1477 1478
	clk_enable(sdma->clk_ipg);
	clk_enable(sdma->clk_ahb);
1479 1480 1481
	/* download the RAM image for SDMA */
	sdma_load_script(sdma, ram_code,
			header->ram_code_size,
1482
			addr->ram_code_start_addr);
1483 1484
	clk_disable(sdma->clk_ipg);
	clk_disable(sdma->clk_ahb);
1485 1486 1487 1488 1489 1490 1491 1492 1493

	sdma_add_scripts(sdma, addr);

	dev_info(sdma->dev, "loaded firmware %d.%d\n",
			header->version_major,
			header->version_minor);

err_firmware:
	release_firmware(fw);
1494 1495
}

1496 1497
#define EVENT_REMAP_CELLS 3

1498
static int sdma_event_remap(struct sdma_engine *sdma)
1499 1500 1501 1502 1503 1504 1505 1506 1507 1508 1509 1510 1511 1512 1513
{
	struct device_node *np = sdma->dev->of_node;
	struct device_node *gpr_np = of_parse_phandle(np, "gpr", 0);
	struct property *event_remap;
	struct regmap *gpr;
	char propname[] = "fsl,sdma-event-remap";
	u32 reg, val, shift, num_map, i;
	int ret = 0;

	if (IS_ERR(np) || IS_ERR(gpr_np))
		goto out;

	event_remap = of_find_property(np, propname, NULL);
	num_map = event_remap ? (event_remap->length / sizeof(u32)) : 0;
	if (!num_map) {
1514
		dev_dbg(sdma->dev, "no event needs to be remapped\n");
1515 1516 1517 1518 1519 1520 1521 1522 1523 1524 1525 1526 1527 1528 1529 1530 1531 1532 1533 1534 1535 1536 1537 1538 1539 1540 1541 1542 1543 1544 1545 1546 1547 1548 1549 1550 1551 1552 1553 1554 1555 1556 1557 1558 1559 1560 1561
		goto out;
	} else if (num_map % EVENT_REMAP_CELLS) {
		dev_err(sdma->dev, "the property %s must modulo %d\n",
				propname, EVENT_REMAP_CELLS);
		ret = -EINVAL;
		goto out;
	}

	gpr = syscon_node_to_regmap(gpr_np);
	if (IS_ERR(gpr)) {
		dev_err(sdma->dev, "failed to get gpr regmap\n");
		ret = PTR_ERR(gpr);
		goto out;
	}

	for (i = 0; i < num_map; i += EVENT_REMAP_CELLS) {
		ret = of_property_read_u32_index(np, propname, i, &reg);
		if (ret) {
			dev_err(sdma->dev, "failed to read property %s index %d\n",
					propname, i);
			goto out;
		}

		ret = of_property_read_u32_index(np, propname, i + 1, &shift);
		if (ret) {
			dev_err(sdma->dev, "failed to read property %s index %d\n",
					propname, i + 1);
			goto out;
		}

		ret = of_property_read_u32_index(np, propname, i + 2, &val);
		if (ret) {
			dev_err(sdma->dev, "failed to read property %s index %d\n",
					propname, i + 2);
			goto out;
		}

		regmap_update_bits(gpr, reg, BIT(shift), val << shift);
	}

out:
	if (!IS_ERR(gpr_np))
		of_node_put(gpr_np);

	return ret;
}

1562
static int sdma_get_firmware(struct sdma_engine *sdma,
1563 1564 1565 1566 1567 1568 1569
		const char *fw_name)
{
	int ret;

	ret = request_firmware_nowait(THIS_MODULE,
			FW_ACTION_HOTPLUG, fw_name, sdma->dev,
			GFP_KERNEL, sdma, sdma_load_firmware);
1570 1571 1572 1573

	return ret;
}

1574
static int sdma_init(struct sdma_engine *sdma)
1575 1576 1577 1578
{
	int i, ret;
	dma_addr_t ccb_phys;

1579 1580 1581 1582 1583 1584
	ret = clk_enable(sdma->clk_ipg);
	if (ret)
		return ret;
	ret = clk_enable(sdma->clk_ahb);
	if (ret)
		goto disable_clk_ipg;
1585 1586

	/* Be sure SDMA has not started yet */
1587
	writel_relaxed(0, sdma->regs + SDMA_H_C0PTR);
1588 1589 1590 1591 1592 1593 1594 1595 1596 1597 1598 1599 1600 1601 1602 1603 1604 1605 1606 1607 1608

	sdma->channel_control = dma_alloc_coherent(NULL,
			MAX_DMA_CHANNELS * sizeof (struct sdma_channel_control) +
			sizeof(struct sdma_context_data),
			&ccb_phys, GFP_KERNEL);

	if (!sdma->channel_control) {
		ret = -ENOMEM;
		goto err_dma_alloc;
	}

	sdma->context = (void *)sdma->channel_control +
		MAX_DMA_CHANNELS * sizeof (struct sdma_channel_control);
	sdma->context_phys = ccb_phys +
		MAX_DMA_CHANNELS * sizeof (struct sdma_channel_control);

	/* Zero-out the CCB structures array just allocated */
	memset(sdma->channel_control, 0,
			MAX_DMA_CHANNELS * sizeof (struct sdma_channel_control));

	/* disable all channels */
1609
	for (i = 0; i < sdma->drvdata->num_events; i++)
1610
		writel_relaxed(0, sdma->regs + chnenbl_ofs(sdma, i));
1611 1612 1613

	/* All channels have priority 0 */
	for (i = 0; i < MAX_DMA_CHANNELS; i++)
1614
		writel_relaxed(0, sdma->regs + SDMA_CHNPRI_0 + i * 4);
1615 1616 1617 1618 1619 1620 1621 1622

	ret = sdma_request_channel(&sdma->channel[0]);
	if (ret)
		goto err_dma_alloc;

	sdma_config_ownership(&sdma->channel[0], false, true, false);

	/* Set Command Channel (Channel Zero) */
1623
	writel_relaxed(0x4050, sdma->regs + SDMA_CHN0ADDR);
1624 1625 1626

	/* Set bits of CONFIG register but with static context switching */
	/* FIXME: Check whether to set ACR bit depending on clock ratios */
1627
	writel_relaxed(0, sdma->regs + SDMA_H_CONFIG);
1628

1629
	writel_relaxed(ccb_phys, sdma->regs + SDMA_H_C0PTR);
1630 1631 1632 1633

	/* Initializes channel's priorities */
	sdma_set_channel_priority(&sdma->channel[0], 7);

1634 1635
	clk_disable(sdma->clk_ipg);
	clk_disable(sdma->clk_ahb);
1636 1637 1638 1639

	return 0;

err_dma_alloc:
1640
	clk_disable(sdma->clk_ahb);
1641 1642
disable_clk_ipg:
	clk_disable(sdma->clk_ipg);
1643 1644 1645 1646
	dev_err(sdma->dev, "initialisation failed with %d\n", ret);
	return ret;
}

1647 1648
static bool sdma_filter_fn(struct dma_chan *chan, void *fn_param)
{
1649
	struct sdma_channel *sdmac = to_sdma_chan(chan);
1650 1651 1652 1653 1654
	struct imx_dma_data *data = fn_param;

	if (!imx_dma_is_general_purpose(chan))
		return false;

1655 1656
	sdmac->data = *data;
	chan->private = &sdmac->data;
1657 1658 1659 1660 1661 1662 1663 1664 1665 1666 1667 1668 1669 1670 1671 1672 1673

	return true;
}

static struct dma_chan *sdma_xlate(struct of_phandle_args *dma_spec,
				   struct of_dma *ofdma)
{
	struct sdma_engine *sdma = ofdma->of_dma_data;
	dma_cap_mask_t mask = sdma->dma_device.cap_mask;
	struct imx_dma_data data;

	if (dma_spec->args_count != 3)
		return NULL;

	data.dma_request = dma_spec->args[0];
	data.peripheral_type = dma_spec->args[1];
	data.priority = dma_spec->args[2];
1674 1675 1676 1677 1678 1679 1680 1681
	/*
	 * init dma_request2 to zero, which is not used by the dts.
	 * For P2P, dma_request2 is init from dma_request_channel(),
	 * chan->private will point to the imx_dma_data, and in
	 * device_alloc_chan_resources(), imx_dma_data.dma_request2 will
	 * be set to sdmac->event_id1.
	 */
	data.dma_request2 = 0;
1682 1683 1684 1685

	return dma_request_channel(mask, sdma_filter_fn, &data);
}

1686
static int sdma_probe(struct platform_device *pdev)
1687
{
1688 1689 1690
	const struct of_device_id *of_id =
			of_match_device(sdma_dt_ids, &pdev->dev);
	struct device_node *np = pdev->dev.of_node;
1691
	struct device_node *spba_bus;
1692
	const char *fw_name;
1693 1694 1695
	int ret;
	int irq;
	struct resource *iores;
1696
	struct resource spba_res;
J
Jingoo Han 已提交
1697
	struct sdma_platform_data *pdata = dev_get_platdata(&pdev->dev);
1698 1699
	int i;
	struct sdma_engine *sdma;
1700
	s32 *saddr_arr;
1701 1702 1703 1704 1705 1706 1707 1708 1709 1710 1711
	const struct sdma_driver_data *drvdata = NULL;

	if (of_id)
		drvdata = of_id->data;
	else if (pdev->id_entry)
		drvdata = (void *)pdev->id_entry->driver_data;

	if (!drvdata) {
		dev_err(&pdev->dev, "unable to find driver data\n");
		return -EINVAL;
	}
1712

1713 1714 1715 1716
	ret = dma_coerce_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
	if (ret)
		return ret;

1717
	sdma = devm_kzalloc(&pdev->dev, sizeof(*sdma), GFP_KERNEL);
1718 1719 1720
	if (!sdma)
		return -ENOMEM;

1721
	spin_lock_init(&sdma->channel_0_lock);
1722

1723
	sdma->dev = &pdev->dev;
1724
	sdma->drvdata = drvdata;
1725 1726

	irq = platform_get_irq(pdev, 0);
1727
	if (irq < 0)
1728
		return irq;
1729

1730 1731 1732 1733
	iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	sdma->regs = devm_ioremap_resource(&pdev->dev, iores);
	if (IS_ERR(sdma->regs))
		return PTR_ERR(sdma->regs);
1734

1735
	sdma->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
1736 1737
	if (IS_ERR(sdma->clk_ipg))
		return PTR_ERR(sdma->clk_ipg);
1738

1739
	sdma->clk_ahb = devm_clk_get(&pdev->dev, "ahb");
1740 1741
	if (IS_ERR(sdma->clk_ahb))
		return PTR_ERR(sdma->clk_ahb);
1742 1743 1744 1745

	clk_prepare(sdma->clk_ipg);
	clk_prepare(sdma->clk_ahb);

1746 1747
	ret = devm_request_irq(&pdev->dev, irq, sdma_int_handler, 0, "sdma",
			       sdma);
1748
	if (ret)
1749
		return ret;
1750

1751 1752
	sdma->irq = irq;

1753
	sdma->script_addrs = kzalloc(sizeof(*sdma->script_addrs), GFP_KERNEL);
1754 1755
	if (!sdma->script_addrs)
		return -ENOMEM;
1756

1757 1758 1759 1760 1761
	/* initially no scripts available */
	saddr_arr = (s32 *)sdma->script_addrs;
	for (i = 0; i < SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1; i++)
		saddr_arr[i] = -EINVAL;

1762 1763 1764
	dma_cap_set(DMA_SLAVE, sdma->dma_device.cap_mask);
	dma_cap_set(DMA_CYCLIC, sdma->dma_device.cap_mask);

1765 1766 1767 1768 1769 1770 1771 1772 1773
	INIT_LIST_HEAD(&sdma->dma_device.channels);
	/* Initialize channel parameters */
	for (i = 0; i < MAX_DMA_CHANNELS; i++) {
		struct sdma_channel *sdmac = &sdma->channel[i];

		sdmac->sdma = sdma;
		spin_lock_init(&sdmac->lock);

		sdmac->chan.device = &sdma->dma_device;
1774
		dma_cookie_init(&sdmac->chan);
1775 1776
		sdmac->channel = i;

1777
		tasklet_init(&sdmac->tasklet, mxc_sdma_handle_channel_normal,
1778
			     (unsigned long) sdmac);
1779 1780 1781 1782 1783 1784 1785 1786
		/*
		 * Add the channel to the DMAC list. Do not add channel 0 though
		 * because we need it internally in the SDMA driver. This also means
		 * that channel 0 in dmaengine counting matches sdma channel 1.
		 */
		if (i)
			list_add_tail(&sdmac->chan.device_node,
					&sdma->dma_device.channels);
1787 1788
	}

1789
	ret = sdma_init(sdma);
1790 1791 1792
	if (ret)
		goto err_init;

1793 1794 1795 1796
	ret = sdma_event_remap(sdma);
	if (ret)
		goto err_init;

1797 1798
	if (sdma->drvdata->script_addrs)
		sdma_add_scripts(sdma, sdma->drvdata->script_addrs);
1799
	if (pdata && pdata->script_addrs)
1800 1801
		sdma_add_scripts(sdma, pdata->script_addrs);

1802
	if (pdata) {
1803 1804
		ret = sdma_get_firmware(sdma, pdata->fw_name);
		if (ret)
1805
			dev_warn(&pdev->dev, "failed to get firmware from platform data\n");
1806 1807 1808 1809 1810 1811 1812 1813
	} else {
		/*
		 * Because that device tree does not encode ROM script address,
		 * the RAM script in firmware is mandatory for device tree
		 * probe, otherwise it fails.
		 */
		ret = of_property_read_string(np, "fsl,sdma-ram-script-name",
					      &fw_name);
1814
		if (ret)
1815
			dev_warn(&pdev->dev, "failed to get firmware name\n");
1816 1817 1818
		else {
			ret = sdma_get_firmware(sdma, fw_name);
			if (ret)
1819
				dev_warn(&pdev->dev, "failed to get firmware from device tree\n");
1820 1821
		}
	}
1822

1823 1824 1825 1826 1827 1828 1829
	sdma->dma_device.dev = &pdev->dev;

	sdma->dma_device.device_alloc_chan_resources = sdma_alloc_chan_resources;
	sdma->dma_device.device_free_chan_resources = sdma_free_chan_resources;
	sdma->dma_device.device_tx_status = sdma_tx_status;
	sdma->dma_device.device_prep_slave_sg = sdma_prep_slave_sg;
	sdma->dma_device.device_prep_dma_cyclic = sdma_prep_dma_cyclic;
1830 1831
	sdma->dma_device.device_config = sdma_config;
	sdma->dma_device.device_terminate_all = sdma_disable_channel;
1832 1833 1834 1835
	sdma->dma_device.src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_4_BYTES);
	sdma->dma_device.dst_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_4_BYTES);
	sdma->dma_device.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV);
	sdma->dma_device.residue_granularity = DMA_RESIDUE_GRANULARITY_BURST;
1836
	sdma->dma_device.device_issue_pending = sdma_issue_pending;
1837 1838
	sdma->dma_device.dev->dma_parms = &sdma->dma_parms;
	dma_set_max_seg_size(sdma->dma_device.dev, 65535);
1839

1840 1841
	platform_set_drvdata(pdev, sdma);

1842 1843 1844 1845 1846 1847
	ret = dma_async_device_register(&sdma->dma_device);
	if (ret) {
		dev_err(&pdev->dev, "unable to register\n");
		goto err_init;
	}

1848 1849 1850 1851 1852 1853
	if (np) {
		ret = of_dma_controller_register(np, sdma_xlate, sdma);
		if (ret) {
			dev_err(&pdev->dev, "failed to register controller\n");
			goto err_register;
		}
1854 1855 1856 1857 1858 1859 1860 1861

		spba_bus = of_find_compatible_node(NULL, NULL, "fsl,spba-bus");
		ret = of_address_to_resource(spba_bus, 0, &spba_res);
		if (!ret) {
			sdma->spba_start_addr = spba_res.start;
			sdma->spba_end_addr = spba_res.end;
		}
		of_node_put(spba_bus);
1862 1863
	}

1864 1865
	return 0;

1866 1867
err_register:
	dma_async_device_unregister(&sdma->dma_device);
1868 1869
err_init:
	kfree(sdma->script_addrs);
1870
	return ret;
1871 1872
}

1873
static int sdma_remove(struct platform_device *pdev)
1874
{
1875
	struct sdma_engine *sdma = platform_get_drvdata(pdev);
1876
	int i;
1877

1878
	devm_free_irq(&pdev->dev, sdma->irq, sdma);
1879 1880
	dma_async_device_unregister(&sdma->dma_device);
	kfree(sdma->script_addrs);
1881 1882 1883 1884 1885 1886
	/* Kill the tasklet */
	for (i = 0; i < MAX_DMA_CHANNELS; i++) {
		struct sdma_channel *sdmac = &sdma->channel[i];

		tasklet_kill(&sdmac->tasklet);
	}
1887 1888 1889

	platform_set_drvdata(pdev, NULL);
	return 0;
1890 1891 1892 1893 1894
}

static struct platform_driver sdma_driver = {
	.driver		= {
		.name	= "imx-sdma",
1895
		.of_match_table = sdma_dt_ids,
1896
	},
1897
	.id_table	= sdma_devtypes,
1898
	.remove		= sdma_remove,
1899
	.probe		= sdma_probe,
1900 1901
};

1902
module_platform_driver(sdma_driver);
1903 1904 1905 1906

MODULE_AUTHOR("Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>");
MODULE_DESCRIPTION("i.MX SDMA driver");
MODULE_LICENSE("GPL");