ahci.c 74.1 KB
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/*
 *  ahci.c - AHCI SATA support
 *
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 *  Maintained by:  Jeff Garzik <jgarzik@pobox.com>
 *    		    Please ALWAYS copy linux-ide@vger.kernel.org
 *		    on emails.
 *
 *  Copyright 2004-2005 Red Hat, Inc.
 *
 *
 *  This program is free software; you can redistribute it and/or modify
 *  it under the terms of the GNU General Public License as published by
 *  the Free Software Foundation; either version 2, or (at your option)
 *  any later version.
 *
 *  This program is distributed in the hope that it will be useful,
 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *  GNU General Public License for more details.
 *
 *  You should have received a copy of the GNU General Public License
 *  along with this program; see the file COPYING.  If not, write to
 *  the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
 *
 *
 * libata documentation is available via 'make {ps|pdf}docs',
 * as Documentation/DocBook/libata.*
 *
 * AHCI hardware documentation:
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 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
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 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
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 *
 */

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/blkdev.h>
#include <linux/delay.h>
#include <linux/interrupt.h>
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#include <linux/dma-mapping.h>
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#include <linux/device.h>
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#include <linux/dmi.h>
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#include <scsi/scsi_host.h>
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#include <scsi/scsi_cmnd.h>
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#include <linux/libata.h>

#define DRV_NAME	"ahci"
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#define DRV_VERSION	"3.0"
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static int ahci_skip_host_reset;
module_param_named(skip_host_reset, ahci_skip_host_reset, int, 0444);
MODULE_PARM_DESC(skip_host_reset, "skip global host reset (0=don't skip, 1=skip)");

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static int ahci_enable_alpm(struct ata_port *ap,
		enum link_pm policy);
static void ahci_disable_alpm(struct ata_port *ap);
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static ssize_t ahci_led_show(struct ata_port *ap, char *buf);
static ssize_t ahci_led_store(struct ata_port *ap, const char *buf,
			      size_t size);
static ssize_t ahci_transmit_led_message(struct ata_port *ap, u32 state,
					ssize_t size);
#define MAX_SLOTS 8
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enum {
	AHCI_PCI_BAR		= 5,
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	AHCI_MAX_PORTS		= 32,
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	AHCI_MAX_SG		= 168, /* hardware max is 64K */
	AHCI_DMA_BOUNDARY	= 0xffffffff,
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	AHCI_MAX_CMDS		= 32,
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	AHCI_CMD_SZ		= 32,
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	AHCI_CMD_SLOT_SZ	= AHCI_MAX_CMDS * AHCI_CMD_SZ,
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	AHCI_RX_FIS_SZ		= 256,
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	AHCI_CMD_TBL_CDB	= 0x40,
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	AHCI_CMD_TBL_HDR_SZ	= 0x80,
	AHCI_CMD_TBL_SZ		= AHCI_CMD_TBL_HDR_SZ + (AHCI_MAX_SG * 16),
	AHCI_CMD_TBL_AR_SZ	= AHCI_CMD_TBL_SZ * AHCI_MAX_CMDS,
	AHCI_PORT_PRIV_DMA_SZ	= AHCI_CMD_SLOT_SZ + AHCI_CMD_TBL_AR_SZ +
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				  AHCI_RX_FIS_SZ,
	AHCI_IRQ_ON_SG		= (1 << 31),
	AHCI_CMD_ATAPI		= (1 << 5),
	AHCI_CMD_WRITE		= (1 << 6),
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	AHCI_CMD_PREFETCH	= (1 << 7),
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	AHCI_CMD_RESET		= (1 << 8),
	AHCI_CMD_CLR_BUSY	= (1 << 10),
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	RX_FIS_D2H_REG		= 0x40,	/* offset of D2H Register FIS data */
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	RX_FIS_SDB		= 0x58, /* offset of SDB FIS data */
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	RX_FIS_UNK		= 0x60, /* offset of Unknown FIS data */
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	board_ahci		= 0,
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	board_ahci_vt8251	= 1,
	board_ahci_ign_iferr	= 2,
	board_ahci_sb600	= 3,
	board_ahci_mv		= 4,
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	board_ahci_sb700	= 5,
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	board_ahci_mcp65	= 6,
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	board_ahci_nopmp	= 7,
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	/* global controller registers */
	HOST_CAP		= 0x00, /* host capabilities */
	HOST_CTL		= 0x04, /* global host control */
	HOST_IRQ_STAT		= 0x08, /* interrupt status */
	HOST_PORTS_IMPL		= 0x0c, /* bitmap of implemented ports */
	HOST_VERSION		= 0x10, /* AHCI spec. version compliancy */
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	HOST_EM_LOC		= 0x1c, /* Enclosure Management location */
	HOST_EM_CTL		= 0x20, /* Enclosure Management Control */
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	/* HOST_CTL bits */
	HOST_RESET		= (1 << 0),  /* reset controller; self-clear */
	HOST_IRQ_EN		= (1 << 1),  /* global IRQ enable */
	HOST_AHCI_EN		= (1 << 31), /* AHCI enabled */

	/* HOST_CAP bits */
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	HOST_CAP_EMS		= (1 << 6),  /* Enclosure Management support */
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	HOST_CAP_SSC		= (1 << 14), /* Slumber capable */
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	HOST_CAP_PMP		= (1 << 17), /* Port Multiplier support */
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	HOST_CAP_CLO		= (1 << 24), /* Command List Override support */
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	HOST_CAP_ALPM		= (1 << 26), /* Aggressive Link PM support */
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	HOST_CAP_SSS		= (1 << 27), /* Staggered Spin-up */
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	HOST_CAP_SNTF		= (1 << 29), /* SNotification register */
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	HOST_CAP_NCQ		= (1 << 30), /* Native Command Queueing */
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	HOST_CAP_64		= (1 << 31), /* PCI DAC (64-bit DMA) support */
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	/* registers for each SATA port */
	PORT_LST_ADDR		= 0x00, /* command list DMA addr */
	PORT_LST_ADDR_HI	= 0x04, /* command list DMA addr hi */
	PORT_FIS_ADDR		= 0x08, /* FIS rx buf addr */
	PORT_FIS_ADDR_HI	= 0x0c, /* FIS rx buf addr hi */
	PORT_IRQ_STAT		= 0x10, /* interrupt status */
	PORT_IRQ_MASK		= 0x14, /* interrupt enable/disable mask */
	PORT_CMD		= 0x18, /* port command */
	PORT_TFDATA		= 0x20,	/* taskfile data */
	PORT_SIG		= 0x24,	/* device TF signature */
	PORT_CMD_ISSUE		= 0x38, /* command issue */
	PORT_SCR_STAT		= 0x28, /* SATA phy register: SStatus */
	PORT_SCR_CTL		= 0x2c, /* SATA phy register: SControl */
	PORT_SCR_ERR		= 0x30, /* SATA phy register: SError */
	PORT_SCR_ACT		= 0x34, /* SATA phy register: SActive */
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	PORT_SCR_NTF		= 0x3c, /* SATA phy register: SNotification */
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	/* PORT_IRQ_{STAT,MASK} bits */
	PORT_IRQ_COLD_PRES	= (1 << 31), /* cold presence detect */
	PORT_IRQ_TF_ERR		= (1 << 30), /* task file error */
	PORT_IRQ_HBUS_ERR	= (1 << 29), /* host bus fatal error */
	PORT_IRQ_HBUS_DATA_ERR	= (1 << 28), /* host bus data error */
	PORT_IRQ_IF_ERR		= (1 << 27), /* interface fatal error */
	PORT_IRQ_IF_NONFATAL	= (1 << 26), /* interface non-fatal error */
	PORT_IRQ_OVERFLOW	= (1 << 24), /* xfer exhausted available S/G */
	PORT_IRQ_BAD_PMP	= (1 << 23), /* incorrect port multiplier */

	PORT_IRQ_PHYRDY		= (1 << 22), /* PhyRdy changed */
	PORT_IRQ_DEV_ILCK	= (1 << 7), /* device interlock */
	PORT_IRQ_CONNECT	= (1 << 6), /* port connect change status */
	PORT_IRQ_SG_DONE	= (1 << 5), /* descriptor processed */
	PORT_IRQ_UNK_FIS	= (1 << 4), /* unknown FIS rx'd */
	PORT_IRQ_SDB_FIS	= (1 << 3), /* Set Device Bits FIS rx'd */
	PORT_IRQ_DMAS_FIS	= (1 << 2), /* DMA Setup FIS rx'd */
	PORT_IRQ_PIOS_FIS	= (1 << 1), /* PIO Setup FIS rx'd */
	PORT_IRQ_D2H_REG_FIS	= (1 << 0), /* D2H Register FIS rx'd */

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	PORT_IRQ_FREEZE		= PORT_IRQ_HBUS_ERR |
				  PORT_IRQ_IF_ERR |
				  PORT_IRQ_CONNECT |
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				  PORT_IRQ_PHYRDY |
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				  PORT_IRQ_UNK_FIS |
				  PORT_IRQ_BAD_PMP,
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	PORT_IRQ_ERROR		= PORT_IRQ_FREEZE |
				  PORT_IRQ_TF_ERR |
				  PORT_IRQ_HBUS_DATA_ERR,
	DEF_PORT_IRQ		= PORT_IRQ_ERROR | PORT_IRQ_SG_DONE |
				  PORT_IRQ_SDB_FIS | PORT_IRQ_DMAS_FIS |
				  PORT_IRQ_PIOS_FIS | PORT_IRQ_D2H_REG_FIS,
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	/* PORT_CMD bits */
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	PORT_CMD_ASP		= (1 << 27), /* Aggressive Slumber/Partial */
	PORT_CMD_ALPE		= (1 << 26), /* Aggressive Link PM enable */
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	PORT_CMD_ATAPI		= (1 << 24), /* Device is ATAPI */
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	PORT_CMD_PMP		= (1 << 17), /* PMP attached */
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	PORT_CMD_LIST_ON	= (1 << 15), /* cmd list DMA engine running */
	PORT_CMD_FIS_ON		= (1 << 14), /* FIS DMA engine running */
	PORT_CMD_FIS_RX		= (1 << 4), /* Enable FIS receive DMA engine */
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	PORT_CMD_CLO		= (1 << 3), /* Command list override */
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	PORT_CMD_POWER_ON	= (1 << 2), /* Power up device */
	PORT_CMD_SPIN_UP	= (1 << 1), /* Spin up device */
	PORT_CMD_START		= (1 << 0), /* Enable port DMA engine */

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	PORT_CMD_ICC_MASK	= (0xf << 28), /* i/f ICC state mask */
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	PORT_CMD_ICC_ACTIVE	= (0x1 << 28), /* Put i/f in active state */
	PORT_CMD_ICC_PARTIAL	= (0x2 << 28), /* Put i/f in partial state */
	PORT_CMD_ICC_SLUMBER	= (0x6 << 28), /* Put i/f in slumber state */
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	/* hpriv->flags bits */
	AHCI_HFLAG_NO_NCQ		= (1 << 0),
	AHCI_HFLAG_IGN_IRQ_IF_ERR	= (1 << 1), /* ignore IRQ_IF_ERR */
	AHCI_HFLAG_IGN_SERR_INTERNAL	= (1 << 2), /* ignore SERR_INTERNAL */
	AHCI_HFLAG_32BIT_ONLY		= (1 << 3), /* force 32bit */
	AHCI_HFLAG_MV_PATA		= (1 << 4), /* PATA port */
	AHCI_HFLAG_NO_MSI		= (1 << 5), /* no PCI MSI */
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	AHCI_HFLAG_NO_PMP		= (1 << 6), /* no PMP */
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	AHCI_HFLAG_NO_HOTPLUG		= (1 << 7), /* ignore PxSERR.DIAG.N */
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	AHCI_HFLAG_SECT255		= (1 << 8), /* max 255 sectors */
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	AHCI_HFLAG_YES_NCQ		= (1 << 9), /* force NCQ cap on */
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	/* ap->flags bits */
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	AHCI_FLAG_COMMON		= ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
					  ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA |
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					  ATA_FLAG_ACPI_SATA | ATA_FLAG_AN |
					  ATA_FLAG_IPM,
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	ICH_MAP				= 0x90, /* ICH MAP register */
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	/* em_ctl bits */
	EM_CTL_RST			= (1 << 9), /* Reset */
	EM_CTL_TM			= (1 << 8), /* Transmit Message */
	EM_CTL_ALHD			= (1 << 26), /* Activity LED */
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};

struct ahci_cmd_hdr {
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	__le32			opts;
	__le32			status;
	__le32			tbl_addr;
	__le32			tbl_addr_hi;
	__le32			reserved[4];
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};

struct ahci_sg {
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	__le32			addr;
	__le32			addr_hi;
	__le32			reserved;
	__le32			flags_size;
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};

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struct ahci_em_priv {
	enum sw_activity blink_policy;
	struct timer_list timer;
	unsigned long saved_activity;
	unsigned long activity;
	unsigned long led_state;
};

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struct ahci_host_priv {
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	unsigned int		flags;		/* AHCI_HFLAG_* */
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	u32			cap;		/* cap to use */
	u32			port_map;	/* port map to use */
	u32			saved_cap;	/* saved initial cap */
	u32			saved_port_map;	/* saved initial port_map */
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	u32 			em_loc; /* enclosure management location */
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};

struct ahci_port_priv {
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	struct ata_link		*active_link;
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	struct ahci_cmd_hdr	*cmd_slot;
	dma_addr_t		cmd_slot_dma;
	void			*cmd_tbl;
	dma_addr_t		cmd_tbl_dma;
	void			*rx_fis;
	dma_addr_t		rx_fis_dma;
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	/* for NCQ spurious interrupt analysis */
	unsigned int		ncq_saw_d2h:1;
	unsigned int		ncq_saw_dmas:1;
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	unsigned int		ncq_saw_sdb:1;
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	u32 			intr_mask;	/* interrupts to enable */
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	struct ahci_em_priv	em_priv[MAX_SLOTS];/* enclosure management info
					 	 * per PM slot */
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};

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static int ahci_scr_read(struct ata_port *ap, unsigned int sc_reg, u32 *val);
static int ahci_scr_write(struct ata_port *ap, unsigned int sc_reg, u32 val);
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static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
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static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc);
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static bool ahci_qc_fill_rtf(struct ata_queued_cmd *qc);
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static int ahci_port_start(struct ata_port *ap);
static void ahci_port_stop(struct ata_port *ap);
static void ahci_qc_prep(struct ata_queued_cmd *qc);
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static void ahci_freeze(struct ata_port *ap);
static void ahci_thaw(struct ata_port *ap);
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static void ahci_pmp_attach(struct ata_port *ap);
static void ahci_pmp_detach(struct ata_port *ap);
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static int ahci_softreset(struct ata_link *link, unsigned int *class,
			  unsigned long deadline);
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static int ahci_sb600_softreset(struct ata_link *link, unsigned int *class,
			  unsigned long deadline);
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static int ahci_hardreset(struct ata_link *link, unsigned int *class,
			  unsigned long deadline);
static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
				 unsigned long deadline);
static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
				unsigned long deadline);
static void ahci_postreset(struct ata_link *link, unsigned int *class);
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static void ahci_error_handler(struct ata_port *ap);
static void ahci_post_internal_cmd(struct ata_queued_cmd *qc);
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static int ahci_port_resume(struct ata_port *ap);
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static void ahci_dev_config(struct ata_device *dev);
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static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl);
static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,
			       u32 opts);
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#ifdef CONFIG_PM
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static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg);
static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
static int ahci_pci_device_resume(struct pci_dev *pdev);
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#endif
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static ssize_t ahci_activity_show(struct ata_device *dev, char *buf);
static ssize_t ahci_activity_store(struct ata_device *dev,
				   enum sw_activity val);
static void ahci_init_sw_activity(struct ata_link *link);
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static struct device_attribute *ahci_shost_attrs[] = {
	&dev_attr_link_power_management_policy,
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	&dev_attr_em_message_type,
	&dev_attr_em_message,
	NULL
};

static struct device_attribute *ahci_sdev_attrs[] = {
	&dev_attr_sw_activity,
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	NULL
};

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static struct scsi_host_template ahci_sht = {
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	ATA_NCQ_SHT(DRV_NAME),
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	.can_queue		= AHCI_MAX_CMDS - 1,
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	.sg_tablesize		= AHCI_MAX_SG,
	.dma_boundary		= AHCI_DMA_BOUNDARY,
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	.shost_attrs		= ahci_shost_attrs,
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	.sdev_attrs		= ahci_sdev_attrs,
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};

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static struct ata_port_operations ahci_ops = {
	.inherits		= &sata_pmp_port_ops,

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	.qc_defer		= sata_pmp_qc_defer_cmd_switch,
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	.qc_prep		= ahci_qc_prep,
	.qc_issue		= ahci_qc_issue,
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	.qc_fill_rtf		= ahci_qc_fill_rtf,
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	.freeze			= ahci_freeze,
	.thaw			= ahci_thaw,
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	.softreset		= ahci_softreset,
	.hardreset		= ahci_hardreset,
	.postreset		= ahci_postreset,
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	.pmp_softreset		= ahci_softreset,
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	.error_handler		= ahci_error_handler,
	.post_internal_cmd	= ahci_post_internal_cmd,
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	.dev_config		= ahci_dev_config,

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	.scr_read		= ahci_scr_read,
	.scr_write		= ahci_scr_write,
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	.pmp_attach		= ahci_pmp_attach,
	.pmp_detach		= ahci_pmp_detach,

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	.enable_pm		= ahci_enable_alpm,
	.disable_pm		= ahci_disable_alpm,
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	.em_show		= ahci_led_show,
	.em_store		= ahci_led_store,
	.sw_activity_show	= ahci_activity_show,
	.sw_activity_store	= ahci_activity_store,
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#ifdef CONFIG_PM
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	.port_suspend		= ahci_port_suspend,
	.port_resume		= ahci_port_resume,
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#endif
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	.port_start		= ahci_port_start,
	.port_stop		= ahci_port_stop,
};

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static struct ata_port_operations ahci_vt8251_ops = {
	.inherits		= &ahci_ops,
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	.hardreset		= ahci_vt8251_hardreset,
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};
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static struct ata_port_operations ahci_p5wdh_ops = {
	.inherits		= &ahci_ops,
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	.hardreset		= ahci_p5wdh_hardreset,
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};

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static struct ata_port_operations ahci_sb600_ops = {
	.inherits		= &ahci_ops,
	.softreset		= ahci_sb600_softreset,
	.pmp_softreset		= ahci_sb600_softreset,
};

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#define AHCI_HFLAGS(flags)	.private_data	= (void *)(flags)

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static const struct ata_port_info ahci_port_info[] = {
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	/* board_ahci */
	{
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		.flags		= AHCI_FLAG_COMMON,
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		.pio_mask	= 0x1f, /* pio0-4 */
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		.udma_mask	= ATA_UDMA6,
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		.port_ops	= &ahci_ops,
	},
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	/* board_ahci_vt8251 */
	{
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		AHCI_HFLAGS	(AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_PMP),
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		.flags		= AHCI_FLAG_COMMON,
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		.pio_mask	= 0x1f, /* pio0-4 */
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		.udma_mask	= ATA_UDMA6,
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		.port_ops	= &ahci_vt8251_ops,
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	},
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	/* board_ahci_ign_iferr */
	{
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		AHCI_HFLAGS	(AHCI_HFLAG_IGN_IRQ_IF_ERR),
		.flags		= AHCI_FLAG_COMMON,
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		.pio_mask	= 0x1f, /* pio0-4 */
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		.udma_mask	= ATA_UDMA6,
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		.port_ops	= &ahci_ops,
	},
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	/* board_ahci_sb600 */
	{
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		AHCI_HFLAGS	(AHCI_HFLAG_IGN_SERR_INTERNAL |
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				 AHCI_HFLAG_32BIT_ONLY | AHCI_HFLAG_NO_MSI |
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				 AHCI_HFLAG_SECT255),
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		.flags		= AHCI_FLAG_COMMON,
416
		.pio_mask	= 0x1f, /* pio0-4 */
417
		.udma_mask	= ATA_UDMA6,
418
		.port_ops	= &ahci_sb600_ops,
419
	},
420 421
	/* board_ahci_mv */
	{
422
		AHCI_HFLAGS	(AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI |
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				 AHCI_HFLAG_MV_PATA | AHCI_HFLAG_NO_PMP),
424
		.flags		= ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
425
				  ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA,
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		.pio_mask	= 0x1f, /* pio0-4 */
		.udma_mask	= ATA_UDMA6,
		.port_ops	= &ahci_ops,
	},
430 431
	/* board_ahci_sb700 */
	{
432
		AHCI_HFLAGS	(AHCI_HFLAG_IGN_SERR_INTERNAL),
433 434 435
		.flags		= AHCI_FLAG_COMMON,
		.pio_mask	= 0x1f, /* pio0-4 */
		.udma_mask	= ATA_UDMA6,
436
		.port_ops	= &ahci_sb600_ops,
437
	},
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	/* board_ahci_mcp65 */
	{
		AHCI_HFLAGS	(AHCI_HFLAG_YES_NCQ),
		.flags		= AHCI_FLAG_COMMON,
		.pio_mask	= 0x1f, /* pio0-4 */
		.udma_mask	= ATA_UDMA6,
		.port_ops	= &ahci_ops,
	},
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	/* board_ahci_nopmp */
	{
		AHCI_HFLAGS	(AHCI_HFLAG_NO_PMP),
		.flags		= AHCI_FLAG_COMMON,
		.pio_mask	= 0x1f, /* pio0-4 */
		.udma_mask	= ATA_UDMA6,
		.port_ops	= &ahci_ops,
	},
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};

456
static const struct pci_device_id ahci_pci_tbl[] = {
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	/* Intel */
458 459 460 461 462
	{ PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */
	{ PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */
	{ PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */
	{ PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */
	{ PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */
463
	{ PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */
464 465 466 467
	{ PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */
	{ PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */
	{ PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */
	{ PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */
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	{ PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */
	{ PCI_VDEVICE(INTEL, 0x2822), board_ahci }, /* ICH8 */
	{ PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */
	{ PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */
	{ PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */
	{ PCI_VDEVICE(INTEL, 0x2922), board_ahci }, /* ICH9 */
	{ PCI_VDEVICE(INTEL, 0x2923), board_ahci }, /* ICH9 */
	{ PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */
	{ PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */
	{ PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */
	{ PCI_VDEVICE(INTEL, 0x2929), board_ahci }, /* ICH9M */
	{ PCI_VDEVICE(INTEL, 0x292a), board_ahci }, /* ICH9M */
	{ PCI_VDEVICE(INTEL, 0x292b), board_ahci }, /* ICH9M */
	{ PCI_VDEVICE(INTEL, 0x292c), board_ahci }, /* ICH9M */
	{ PCI_VDEVICE(INTEL, 0x292f), board_ahci }, /* ICH9M */
	{ PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */
	{ PCI_VDEVICE(INTEL, 0x294e), board_ahci }, /* ICH9M */
485 486
	{ PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */
	{ PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */
487 488
	{ PCI_VDEVICE(INTEL, 0x3a05), board_ahci }, /* ICH10 */
	{ PCI_VDEVICE(INTEL, 0x3a25), board_ahci }, /* ICH10 */
489
	{ PCI_VDEVICE(INTEL, 0x3b24), board_ahci }, /* PCH RAID */
490
	{ PCI_VDEVICE(INTEL, 0x3b25), board_ahci }, /* PCH RAID */
491
	{ PCI_VDEVICE(INTEL, 0x3b2b), board_ahci }, /* PCH RAID */
492
	{ PCI_VDEVICE(INTEL, 0x3b2c), board_ahci }, /* PCH RAID */
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494 495 496
	/* JMicron 360/1/3/5/6, match class to avoid IDE function */
	{ PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
	  PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr },
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	/* ATI */
499
	{ PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */
500 501 502 503 504 505
	{ PCI_VDEVICE(ATI, 0x4390), board_ahci_sb700 }, /* ATI SB700/800 */
	{ PCI_VDEVICE(ATI, 0x4391), board_ahci_sb700 }, /* ATI SB700/800 */
	{ PCI_VDEVICE(ATI, 0x4392), board_ahci_sb700 }, /* ATI SB700/800 */
	{ PCI_VDEVICE(ATI, 0x4393), board_ahci_sb700 }, /* ATI SB700/800 */
	{ PCI_VDEVICE(ATI, 0x4394), board_ahci_sb700 }, /* ATI SB700/800 */
	{ PCI_VDEVICE(ATI, 0x4395), board_ahci_sb700 }, /* ATI SB700/800 */
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	/* VIA */
508
	{ PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */
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	{ PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */
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	/* NVIDIA */
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	{ PCI_VDEVICE(NVIDIA, 0x044c), board_ahci_mcp65 },	/* MCP65 */
	{ PCI_VDEVICE(NVIDIA, 0x044d), board_ahci_mcp65 },	/* MCP65 */
	{ PCI_VDEVICE(NVIDIA, 0x044e), board_ahci_mcp65 },	/* MCP65 */
	{ PCI_VDEVICE(NVIDIA, 0x044f), board_ahci_mcp65 },	/* MCP65 */
	{ PCI_VDEVICE(NVIDIA, 0x045c), board_ahci_mcp65 },	/* MCP65 */
	{ PCI_VDEVICE(NVIDIA, 0x045d), board_ahci_mcp65 },	/* MCP65 */
	{ PCI_VDEVICE(NVIDIA, 0x045e), board_ahci_mcp65 },	/* MCP65 */
	{ PCI_VDEVICE(NVIDIA, 0x045f), board_ahci_mcp65 },	/* MCP65 */
520 521 522 523
	{ PCI_VDEVICE(NVIDIA, 0x0550), board_ahci },		/* MCP67 */
	{ PCI_VDEVICE(NVIDIA, 0x0551), board_ahci },		/* MCP67 */
	{ PCI_VDEVICE(NVIDIA, 0x0552), board_ahci },		/* MCP67 */
	{ PCI_VDEVICE(NVIDIA, 0x0553), board_ahci },		/* MCP67 */
524 525 526 527 528 529 530 531
	{ PCI_VDEVICE(NVIDIA, 0x0554), board_ahci },		/* MCP67 */
	{ PCI_VDEVICE(NVIDIA, 0x0555), board_ahci },		/* MCP67 */
	{ PCI_VDEVICE(NVIDIA, 0x0556), board_ahci },		/* MCP67 */
	{ PCI_VDEVICE(NVIDIA, 0x0557), board_ahci },		/* MCP67 */
	{ PCI_VDEVICE(NVIDIA, 0x0558), board_ahci },		/* MCP67 */
	{ PCI_VDEVICE(NVIDIA, 0x0559), board_ahci },		/* MCP67 */
	{ PCI_VDEVICE(NVIDIA, 0x055a), board_ahci },		/* MCP67 */
	{ PCI_VDEVICE(NVIDIA, 0x055b), board_ahci },		/* MCP67 */
532 533 534 535 536 537 538 539 540 541 542 543 544 545 546 547 548 549 550 551 552 553 554 555
	{ PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci },		/* MCP73 */
	{ PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci },		/* MCP73 */
	{ PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci },		/* MCP73 */
	{ PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci },		/* MCP73 */
	{ PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci },		/* MCP73 */
	{ PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci },		/* MCP73 */
	{ PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci },		/* MCP73 */
	{ PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci },		/* MCP73 */
	{ PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci },		/* MCP73 */
	{ PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci },		/* MCP73 */
	{ PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci },		/* MCP73 */
	{ PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci },		/* MCP73 */
	{ PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci },		/* MCP77 */
	{ PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci },		/* MCP77 */
	{ PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci },		/* MCP77 */
	{ PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci },		/* MCP77 */
	{ PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci },		/* MCP77 */
	{ PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci },		/* MCP77 */
	{ PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci },		/* MCP77 */
	{ PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci },		/* MCP77 */
	{ PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci },		/* MCP77 */
	{ PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci },		/* MCP77 */
	{ PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci },		/* MCP77 */
	{ PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci },		/* MCP77 */
556 557 558 559
	{ PCI_VDEVICE(NVIDIA, 0x0ab4), board_ahci },		/* MCP79 */
	{ PCI_VDEVICE(NVIDIA, 0x0ab5), board_ahci },		/* MCP79 */
	{ PCI_VDEVICE(NVIDIA, 0x0ab6), board_ahci },		/* MCP79 */
	{ PCI_VDEVICE(NVIDIA, 0x0ab7), board_ahci },		/* MCP79 */
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	{ PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci },		/* MCP79 */
	{ PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci },		/* MCP79 */
	{ PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci },		/* MCP79 */
	{ PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci },		/* MCP79 */
	{ PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci },		/* MCP79 */
	{ PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci },		/* MCP79 */
	{ PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci },		/* MCP79 */
	{ PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci },		/* MCP79 */
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	{ PCI_VDEVICE(NVIDIA, 0x0bc8), board_ahci },		/* MCP7B */
	{ PCI_VDEVICE(NVIDIA, 0x0bc9), board_ahci },		/* MCP7B */
	{ PCI_VDEVICE(NVIDIA, 0x0bca), board_ahci },		/* MCP7B */
	{ PCI_VDEVICE(NVIDIA, 0x0bcb), board_ahci },		/* MCP7B */
	{ PCI_VDEVICE(NVIDIA, 0x0bcc), board_ahci },		/* MCP7B */
	{ PCI_VDEVICE(NVIDIA, 0x0bcd), board_ahci },		/* MCP7B */
	{ PCI_VDEVICE(NVIDIA, 0x0bce), board_ahci },		/* MCP7B */
	{ PCI_VDEVICE(NVIDIA, 0x0bcf), board_ahci },		/* MCP7B */
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	{ PCI_VDEVICE(NVIDIA, 0x0bc4), board_ahci },		/* MCP7B */
	{ PCI_VDEVICE(NVIDIA, 0x0bc5), board_ahci },		/* MCP7B */
	{ PCI_VDEVICE(NVIDIA, 0x0bc6), board_ahci },		/* MCP7B */
	{ PCI_VDEVICE(NVIDIA, 0x0bc7), board_ahci },		/* MCP7B */
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	/* SiS */
582 583 584
	{ PCI_VDEVICE(SI, 0x1184), board_ahci },		/* SiS 966 */
	{ PCI_VDEVICE(SI, 0x1185), board_ahci },		/* SiS 968 */
	{ PCI_VDEVICE(SI, 0x0186), board_ahci },		/* SiS 968 */
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586 587
	/* Marvell */
	{ PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv },	/* 6145 */
588
	{ PCI_VDEVICE(MARVELL, 0x6121), board_ahci_mv },	/* 6121 */
589

590 591
	/* Generic, PCI class code for AHCI */
	{ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
592
	  PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci },
593

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	{ }	/* terminate list */
};


static struct pci_driver ahci_pci_driver = {
	.name			= DRV_NAME,
	.id_table		= ahci_pci_tbl,
	.probe			= ahci_init_one,
602
	.remove			= ata_pci_remove_one,
603
#ifdef CONFIG_PM
604 605
	.suspend		= ahci_pci_device_suspend,
	.resume			= ahci_pci_device_resume,
606
#endif
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};

609 610 611 612 613
static int ahci_em_messages = 1;
module_param(ahci_em_messages, int, 0444);
/* add other LED protocol types when they become supported */
MODULE_PARM_DESC(ahci_em_messages,
	"Set AHCI Enclosure Management Message type (0 = disabled, 1 = LED");
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615 616 617 618 619 620 621 622 623
#if defined(CONFIG_PATA_MARVELL) || defined(CONFIG_PATA_MARVELL_MODULE)
static int marvell_enable;
#else
static int marvell_enable = 1;
#endif
module_param(marvell_enable, int, 0644);
MODULE_PARM_DESC(marvell_enable, "Marvell SATA via AHCI (1 = enabled)");


624 625 626 627 628
static inline int ahci_nr_ports(u32 cap)
{
	return (cap & 0x1f) + 1;
}

629 630
static inline void __iomem *__ahci_port_base(struct ata_host *host,
					     unsigned int port_no)
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{
632
	void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
633

634 635 636 637 638 639
	return mmio + 0x100 + (port_no * 0x80);
}

static inline void __iomem *ahci_port_base(struct ata_port *ap)
{
	return __ahci_port_base(ap->host, ap->port_no);
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}

642 643
static void ahci_enable_ahci(void __iomem *mmio)
{
644
	int i;
645 646 647 648
	u32 tmp;

	/* turn on AHCI_EN */
	tmp = readl(mmio + HOST_CTL);
649 650 651 652 653 654 655
	if (tmp & HOST_AHCI_EN)
		return;

	/* Some controllers need AHCI_EN to be written multiple times.
	 * Try a few times before giving up.
	 */
	for (i = 0; i < 5; i++) {
656 657 658
		tmp |= HOST_AHCI_EN;
		writel(tmp, mmio + HOST_CTL);
		tmp = readl(mmio + HOST_CTL);	/* flush && sanity check */
659 660 661
		if (tmp & HOST_AHCI_EN)
			return;
		msleep(10);
662
	}
663 664

	WARN_ON(1);
665 666
}

667 668
/**
 *	ahci_save_initial_config - Save and fixup initial config values
669 670
 *	@pdev: target PCI device
 *	@hpriv: host private area to store config values
671 672 673 674 675 676 677 678 679 680 681
 *
 *	Some registers containing configuration info might be setup by
 *	BIOS and might be cleared on reset.  This function saves the
 *	initial values of those registers into @hpriv such that they
 *	can be restored after controller reset.
 *
 *	If inconsistent, config values are fixed up by this function.
 *
 *	LOCKING:
 *	None.
 */
682 683
static void ahci_save_initial_config(struct pci_dev *pdev,
				     struct ahci_host_priv *hpriv)
684
{
685
	void __iomem *mmio = pcim_iomap_table(pdev)[AHCI_PCI_BAR];
686
	u32 cap, port_map;
687
	int i;
688
	int mv;
689

690 691 692
	/* make sure AHCI mode is enabled before accessing CAP */
	ahci_enable_ahci(mmio);

693 694 695 696 697 698
	/* Values prefixed with saved_ are written back to host after
	 * reset.  Values without are used for driver operation.
	 */
	hpriv->saved_cap = cap = readl(mmio + HOST_CAP);
	hpriv->saved_port_map = port_map = readl(mmio + HOST_PORTS_IMPL);

699
	/* some chips have errata preventing 64bit use */
700
	if ((cap & HOST_CAP_64) && (hpriv->flags & AHCI_HFLAG_32BIT_ONLY)) {
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		dev_printk(KERN_INFO, &pdev->dev,
			   "controller can't do 64bit DMA, forcing 32bit\n");
		cap &= ~HOST_CAP_64;
	}

706
	if ((cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_NO_NCQ)) {
707 708 709 710 711
		dev_printk(KERN_INFO, &pdev->dev,
			   "controller can't do NCQ, turning off CAP_NCQ\n");
		cap &= ~HOST_CAP_NCQ;
	}

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	if (!(cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_YES_NCQ)) {
		dev_printk(KERN_INFO, &pdev->dev,
			   "controller can do NCQ, turning on CAP_NCQ\n");
		cap |= HOST_CAP_NCQ;
	}

718
	if ((cap & HOST_CAP_PMP) && (hpriv->flags & AHCI_HFLAG_NO_PMP)) {
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		dev_printk(KERN_INFO, &pdev->dev,
			   "controller can't do PMP, turning off CAP_PMP\n");
		cap &= ~HOST_CAP_PMP;
	}

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	if (pdev->vendor == PCI_VENDOR_ID_JMICRON && pdev->device == 0x2361 &&
	    port_map != 1) {
		dev_printk(KERN_INFO, &pdev->dev,
			   "JMB361 has only one port, port_map 0x%x -> 0x%x\n",
			   port_map, 1);
		port_map = 1;
	}

732 733 734 735 736
	/*
	 * Temporary Marvell 6145 hack: PATA port presence
	 * is asserted through the standard AHCI port
	 * presence register, as bit 4 (counting from 0)
	 */
737
	if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
738 739 740 741
		if (pdev->device == 0x6121)
			mv = 0x3;
		else
			mv = 0xf;
742 743
		dev_printk(KERN_ERR, &pdev->dev,
			   "MV_AHCI HACK: port_map %x -> %x\n",
744 745
			   port_map,
			   port_map & mv);
746 747
		dev_printk(KERN_ERR, &pdev->dev,
			  "Disabling your PATA port. Use the boot option 'ahci.marvell_enable=0' to avoid this.\n");
748

749
		port_map &= mv;
750 751
	}

752
	/* cross check port_map and cap.n_ports */
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	if (port_map) {
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		int map_ports = 0;
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		for (i = 0; i < AHCI_MAX_PORTS; i++)
			if (port_map & (1 << i))
				map_ports++;
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		/* If PI has more ports than n_ports, whine, clear
		 * port_map and let it be generated from n_ports.
762
		 */
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		if (map_ports > ahci_nr_ports(cap)) {
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			dev_printk(KERN_WARNING, &pdev->dev,
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				   "implemented port map (0x%x) contains more "
				   "ports than nr_ports (%u), using nr_ports\n",
				   port_map, ahci_nr_ports(cap));
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			port_map = 0;
		}
	}

	/* fabricate port_map from cap.nr_ports */
	if (!port_map) {
774
		port_map = (1 << ahci_nr_ports(cap)) - 1;
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		dev_printk(KERN_WARNING, &pdev->dev,
			   "forcing PORTS_IMPL to 0x%x\n", port_map);

		/* write the fixed up value to the PI register */
		hpriv->saved_port_map = port_map;
780 781
	}

782 783 784 785 786 787 788
	/* record values to use during operation */
	hpriv->cap = cap;
	hpriv->port_map = port_map;
}

/**
 *	ahci_restore_initial_config - Restore initial config
789
 *	@host: target ATA host
790 791 792 793 794 795
 *
 *	Restore initial config stored by ahci_save_initial_config().
 *
 *	LOCKING:
 *	None.
 */
796
static void ahci_restore_initial_config(struct ata_host *host)
797
{
798 799 800
	struct ahci_host_priv *hpriv = host->private_data;
	void __iomem *mmio = host->iomap[AHCI_PCI_BAR];

801 802 803 804 805
	writel(hpriv->saved_cap, mmio + HOST_CAP);
	writel(hpriv->saved_port_map, mmio + HOST_PORTS_IMPL);
	(void) readl(mmio + HOST_PORTS_IMPL);	/* flush */
}

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static unsigned ahci_scr_offset(struct ata_port *ap, unsigned int sc_reg)
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{
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	static const int offset[] = {
		[SCR_STATUS]		= PORT_SCR_STAT,
		[SCR_CONTROL]		= PORT_SCR_CTL,
		[SCR_ERROR]		= PORT_SCR_ERR,
		[SCR_ACTIVE]		= PORT_SCR_ACT,
		[SCR_NOTIFICATION]	= PORT_SCR_NTF,
	};
	struct ahci_host_priv *hpriv = ap->host->private_data;
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	if (sc_reg < ARRAY_SIZE(offset) &&
	    (sc_reg != SCR_NOTIFICATION || (hpriv->cap & HOST_CAP_SNTF)))
		return offset[sc_reg];
820
	return 0;
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}

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static int ahci_scr_read(struct ata_port *ap, unsigned int sc_reg, u32 *val)
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{
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	void __iomem *port_mmio = ahci_port_base(ap);
	int offset = ahci_scr_offset(ap, sc_reg);

	if (offset) {
		*val = readl(port_mmio + offset);
		return 0;
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	}
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	return -EINVAL;
}
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static int ahci_scr_write(struct ata_port *ap, unsigned int sc_reg, u32 val)
{
	void __iomem *port_mmio = ahci_port_base(ap);
	int offset = ahci_scr_offset(ap, sc_reg);

	if (offset) {
		writel(val, port_mmio + offset);
		return 0;
	}
	return -EINVAL;
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}

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static void ahci_start_engine(struct ata_port *ap)
848
{
849
	void __iomem *port_mmio = ahci_port_base(ap);
850 851
	u32 tmp;

852
	/* start DMA */
853
	tmp = readl(port_mmio + PORT_CMD);
854 855 856 857 858
	tmp |= PORT_CMD_START;
	writel(tmp, port_mmio + PORT_CMD);
	readl(port_mmio + PORT_CMD); /* flush */
}

859
static int ahci_stop_engine(struct ata_port *ap)
860
{
861
	void __iomem *port_mmio = ahci_port_base(ap);
862 863 864 865
	u32 tmp;

	tmp = readl(port_mmio + PORT_CMD);

866
	/* check if the HBA is idle */
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	if ((tmp & (PORT_CMD_START | PORT_CMD_LIST_ON)) == 0)
		return 0;

870
	/* setting HBA to idle */
871 872 873
	tmp &= ~PORT_CMD_START;
	writel(tmp, port_mmio + PORT_CMD);

874
	/* wait for engine to stop. This could be as long as 500 msec */
875
	tmp = ata_wait_register(port_mmio + PORT_CMD,
876
				PORT_CMD_LIST_ON, PORT_CMD_LIST_ON, 1, 500);
877
	if (tmp & PORT_CMD_LIST_ON)
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		return -EIO;

	return 0;
}

883
static void ahci_start_fis_rx(struct ata_port *ap)
884
{
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	void __iomem *port_mmio = ahci_port_base(ap);
	struct ahci_host_priv *hpriv = ap->host->private_data;
	struct ahci_port_priv *pp = ap->private_data;
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	u32 tmp;

	/* set FIS registers */
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	if (hpriv->cap & HOST_CAP_64)
		writel((pp->cmd_slot_dma >> 16) >> 16,
		       port_mmio + PORT_LST_ADDR_HI);
	writel(pp->cmd_slot_dma & 0xffffffff, port_mmio + PORT_LST_ADDR);
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	if (hpriv->cap & HOST_CAP_64)
		writel((pp->rx_fis_dma >> 16) >> 16,
		       port_mmio + PORT_FIS_ADDR_HI);
	writel(pp->rx_fis_dma & 0xffffffff, port_mmio + PORT_FIS_ADDR);
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	/* enable FIS reception */
	tmp = readl(port_mmio + PORT_CMD);
	tmp |= PORT_CMD_FIS_RX;
	writel(tmp, port_mmio + PORT_CMD);

	/* flush */
	readl(port_mmio + PORT_CMD);
}

910
static int ahci_stop_fis_rx(struct ata_port *ap)
911
{
912
	void __iomem *port_mmio = ahci_port_base(ap);
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	u32 tmp;

	/* disable FIS reception */
	tmp = readl(port_mmio + PORT_CMD);
	tmp &= ~PORT_CMD_FIS_RX;
	writel(tmp, port_mmio + PORT_CMD);

	/* wait for completion, spec says 500ms, give it 1000 */
	tmp = ata_wait_register(port_mmio + PORT_CMD, PORT_CMD_FIS_ON,
				PORT_CMD_FIS_ON, 10, 1000);
	if (tmp & PORT_CMD_FIS_ON)
		return -EBUSY;

	return 0;
}

929
static void ahci_power_up(struct ata_port *ap)
930
{
931 932
	struct ahci_host_priv *hpriv = ap->host->private_data;
	void __iomem *port_mmio = ahci_port_base(ap);
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	u32 cmd;

	cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;

	/* spin up device */
938
	if (hpriv->cap & HOST_CAP_SSS) {
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		cmd |= PORT_CMD_SPIN_UP;
		writel(cmd, port_mmio + PORT_CMD);
	}

	/* wake up link */
	writel(cmd | PORT_CMD_ICC_ACTIVE, port_mmio + PORT_CMD);
}

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static void ahci_disable_alpm(struct ata_port *ap)
{
	struct ahci_host_priv *hpriv = ap->host->private_data;
	void __iomem *port_mmio = ahci_port_base(ap);
	u32 cmd;
	struct ahci_port_priv *pp = ap->private_data;

	/* IPM bits should be disabled by libata-core */
	/* get the existing command bits */
	cmd = readl(port_mmio + PORT_CMD);

	/* disable ALPM and ASP */
	cmd &= ~PORT_CMD_ASP;
	cmd &= ~PORT_CMD_ALPE;

	/* force the interface back to active */
	cmd |= PORT_CMD_ICC_ACTIVE;

	/* write out new cmd value */
	writel(cmd, port_mmio + PORT_CMD);
	cmd = readl(port_mmio + PORT_CMD);

	/* wait 10ms to be sure we've come out of any low power state */
	msleep(10);

	/* clear out any PhyRdy stuff from interrupt status */
	writel(PORT_IRQ_PHYRDY, port_mmio + PORT_IRQ_STAT);

	/* go ahead and clean out PhyRdy Change from Serror too */
	ahci_scr_write(ap, SCR_ERROR, ((1 << 16) | (1 << 18)));

	/*
 	 * Clear flag to indicate that we should ignore all PhyRdy
 	 * state changes
 	 */
	hpriv->flags &= ~AHCI_HFLAG_NO_HOTPLUG;

	/*
 	 * Enable interrupts on Phy Ready.
 	 */
	pp->intr_mask |= PORT_IRQ_PHYRDY;
	writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);

	/*
 	 * don't change the link pm policy - we can be called
 	 * just to turn of link pm temporarily
 	 */
}

static int ahci_enable_alpm(struct ata_port *ap,
	enum link_pm policy)
{
	struct ahci_host_priv *hpriv = ap->host->private_data;
	void __iomem *port_mmio = ahci_port_base(ap);
	u32 cmd;
	struct ahci_port_priv *pp = ap->private_data;
	u32 asp;

	/* Make sure the host is capable of link power management */
	if (!(hpriv->cap & HOST_CAP_ALPM))
		return -EINVAL;

	switch (policy) {
	case MAX_PERFORMANCE:
	case NOT_AVAILABLE:
		/*
 		 * if we came here with NOT_AVAILABLE,
 		 * it just means this is the first time we
 		 * have tried to enable - default to max performance,
 		 * and let the user go to lower power modes on request.
 		 */
		ahci_disable_alpm(ap);
		return 0;
	case MIN_POWER:
		/* configure HBA to enter SLUMBER */
		asp = PORT_CMD_ASP;
		break;
	case MEDIUM_POWER:
		/* configure HBA to enter PARTIAL */
		asp = 0;
		break;
	default:
		return -EINVAL;
	}

	/*
 	 * Disable interrupts on Phy Ready. This keeps us from
 	 * getting woken up due to spurious phy ready interrupts
	 * TBD - Hot plug should be done via polling now, is
	 * that even supported?
 	 */
	pp->intr_mask &= ~PORT_IRQ_PHYRDY;
	writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);

	/*
 	 * Set a flag to indicate that we should ignore all PhyRdy
 	 * state changes since these can happen now whenever we
 	 * change link state
 	 */
	hpriv->flags |= AHCI_HFLAG_NO_HOTPLUG;

	/* get the existing command bits */
	cmd = readl(port_mmio + PORT_CMD);

	/*
 	 * Set ASP based on Policy
 	 */
	cmd |= asp;

	/*
 	 * Setting this bit will instruct the HBA to aggressively
 	 * enter a lower power link state when it's appropriate and
 	 * based on the value set above for ASP
 	 */
	cmd |= PORT_CMD_ALPE;

	/* write out new cmd value */
	writel(cmd, port_mmio + PORT_CMD);
	cmd = readl(port_mmio + PORT_CMD);

	/* IPM bits should be set by libata-core */
	return 0;
}

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#ifdef CONFIG_PM
1072
static void ahci_power_down(struct ata_port *ap)
1073
{
1074 1075
	struct ahci_host_priv *hpriv = ap->host->private_data;
	void __iomem *port_mmio = ahci_port_base(ap);
1076 1077
	u32 cmd, scontrol;

1078
	if (!(hpriv->cap & HOST_CAP_SSS))
1079
		return;
1080

1081 1082 1083 1084
	/* put device into listen mode, first set PxSCTL.DET to 0 */
	scontrol = readl(port_mmio + PORT_SCR_CTL);
	scontrol &= ~0xf;
	writel(scontrol, port_mmio + PORT_SCR_CTL);
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1086 1087 1088 1089
	/* then set PxCMD.SUD to 0 */
	cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
	cmd &= ~PORT_CMD_SPIN_UP;
	writel(cmd, port_mmio + PORT_CMD);
1090
}
1091
#endif
1092

1093
static void ahci_start_port(struct ata_port *ap)
1094
{
1095 1096 1097 1098
	struct ahci_port_priv *pp = ap->private_data;
	struct ata_link *link;
	struct ahci_em_priv *emp;

1099
	/* enable FIS reception */
1100
	ahci_start_fis_rx(ap);
1101 1102

	/* enable DMA */
1103
	ahci_start_engine(ap);
1104 1105 1106 1107 1108 1109 1110 1111 1112 1113 1114 1115 1116

	/* turn on LEDs */
	if (ap->flags & ATA_FLAG_EM) {
		ata_port_for_each_link(link, ap) {
			emp = &pp->em_priv[link->pmp];
			ahci_transmit_led_message(ap, emp->led_state, 4);
		}
	}

	if (ap->flags & ATA_FLAG_SW_ACTIVITY)
		ata_port_for_each_link(link, ap)
			ahci_init_sw_activity(link);

1117 1118
}

1119
static int ahci_deinit_port(struct ata_port *ap, const char **emsg)
1120 1121 1122 1123
{
	int rc;

	/* disable DMA */
1124
	rc = ahci_stop_engine(ap);
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	if (rc) {
		*emsg = "failed to stop engine";
		return rc;
	}

	/* disable FIS reception */
1131
	rc = ahci_stop_fis_rx(ap);
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	if (rc) {
		*emsg = "failed stop FIS RX";
		return rc;
	}

	return 0;
}

1140
static int ahci_reset_controller(struct ata_host *host)
1141
{
1142
	struct pci_dev *pdev = to_pci_dev(host->dev);
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	struct ahci_host_priv *hpriv = host->private_data;
1144
	void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
1145
	u32 tmp;
1146

1147 1148 1149
	/* we must be in AHCI mode, before using anything
	 * AHCI-specific, such as HOST_RESET.
	 */
1150
	ahci_enable_ahci(mmio);
1151 1152

	/* global controller reset */
1153 1154 1155 1156 1157 1158
	if (!ahci_skip_host_reset) {
		tmp = readl(mmio + HOST_CTL);
		if ((tmp & HOST_RESET) == 0) {
			writel(tmp | HOST_RESET, mmio + HOST_CTL);
			readl(mmio + HOST_CTL); /* flush */
		}
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		/*
		 * to perform host reset, OS should set HOST_RESET
		 * and poll until this bit is read to be "0".
		 * reset must complete within 1 second, or
1164 1165
		 * the hardware should be considered fried.
		 */
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		tmp = ata_wait_register(mmio + HOST_CTL, HOST_RESET,
					HOST_RESET, 10, 1000);
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1169 1170 1171 1172 1173
		if (tmp & HOST_RESET) {
			dev_printk(KERN_ERR, host->dev,
				   "controller reset failed (0x%x)\n", tmp);
			return -EIO;
		}
1174

1175 1176
		/* turn on AHCI mode */
		ahci_enable_ahci(mmio);
1177

1178 1179 1180 1181 1182 1183 1184
		/* Some registers might be cleared on reset.  Restore
		 * initial values.
		 */
		ahci_restore_initial_config(host);
	} else
		dev_printk(KERN_INFO, host->dev,
			   "skipping global host reset\n");
1185 1186 1187 1188 1189 1190

	if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
		u16 tmp16;

		/* configure PCS */
		pci_read_config_word(pdev, 0x92, &tmp16);
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		if ((tmp16 & hpriv->port_map) != hpriv->port_map) {
			tmp16 |= hpriv->port_map;
			pci_write_config_word(pdev, 0x92, tmp16);
		}
1195 1196 1197 1198 1199
	}

	return 0;
}

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static void ahci_sw_activity(struct ata_link *link)
{
	struct ata_port *ap = link->ap;
	struct ahci_port_priv *pp = ap->private_data;
	struct ahci_em_priv *emp = &pp->em_priv[link->pmp];

	if (!(link->flags & ATA_LFLAG_SW_ACTIVITY))
		return;

	emp->activity++;
	if (!timer_pending(&emp->timer))
		mod_timer(&emp->timer, jiffies + msecs_to_jiffies(10));
}

static void ahci_sw_activity_blink(unsigned long arg)
{
	struct ata_link *link = (struct ata_link *)arg;
	struct ata_port *ap = link->ap;
	struct ahci_port_priv *pp = ap->private_data;
	struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
	unsigned long led_message = emp->led_state;
	u32 activity_led_state;

	led_message &= 0xffff0000;
	led_message |= ap->port_no | (link->pmp << 8);

	/* check to see if we've had activity.  If so,
	 * toggle state of LED and reset timer.  If not,
	 * turn LED to desired idle state.
	 */
	if (emp->saved_activity != emp->activity) {
		emp->saved_activity = emp->activity;
		/* get the current LED state */
		activity_led_state = led_message & 0x00010000;

		if (activity_led_state)
			activity_led_state = 0;
		else
			activity_led_state = 1;

		/* clear old state */
		led_message &= 0xfff8ffff;

		/* toggle state */
		led_message |= (activity_led_state << 16);
		mod_timer(&emp->timer, jiffies + msecs_to_jiffies(100));
	} else {
		/* switch to idle */
		led_message &= 0xfff8ffff;
		if (emp->blink_policy == BLINK_OFF)
			led_message |= (1 << 16);
	}
	ahci_transmit_led_message(ap, led_message, 4);
}

static void ahci_init_sw_activity(struct ata_link *link)
{
	struct ata_port *ap = link->ap;
	struct ahci_port_priv *pp = ap->private_data;
	struct ahci_em_priv *emp = &pp->em_priv[link->pmp];

	/* init activity stats, setup timer */
	emp->saved_activity = emp->activity = 0;
	setup_timer(&emp->timer, ahci_sw_activity_blink, (unsigned long)link);

	/* check our blink policy and set flag for link if it's enabled */
	if (emp->blink_policy)
		link->flags |= ATA_LFLAG_SW_ACTIVITY;
}

static int ahci_reset_em(struct ata_host *host)
{
	void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
	u32 em_ctl;

	em_ctl = readl(mmio + HOST_EM_CTL);
	if ((em_ctl & EM_CTL_TM) || (em_ctl & EM_CTL_RST))
		return -EINVAL;

	writel(em_ctl | EM_CTL_RST, mmio + HOST_EM_CTL);
	return 0;
}

static ssize_t ahci_transmit_led_message(struct ata_port *ap, u32 state,
					ssize_t size)
{
	struct ahci_host_priv *hpriv = ap->host->private_data;
	struct ahci_port_priv *pp = ap->private_data;
	void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR];
	u32 em_ctl;
	u32 message[] = {0, 0};
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	unsigned long flags;
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	int pmp;
	struct ahci_em_priv *emp;

	/* get the slot number from the message */
	pmp = (state & 0x0000ff00) >> 8;
	if (pmp < MAX_SLOTS)
		emp = &pp->em_priv[pmp];
	else
		return -EINVAL;

	spin_lock_irqsave(ap->lock, flags);

	/*
	 * if we are still busy transmitting a previous message,
	 * do not allow
	 */
	em_ctl = readl(mmio + HOST_EM_CTL);
	if (em_ctl & EM_CTL_TM) {
		spin_unlock_irqrestore(ap->lock, flags);
		return -EINVAL;
	}

	/*
	 * create message header - this is all zero except for
	 * the message size, which is 4 bytes.
	 */
	message[0] |= (4 << 8);

	/* ignore 0:4 of byte zero, fill in port info yourself */
	message[1] = ((state & 0xfffffff0) | ap->port_no);

	/* write message to EM_LOC */
	writel(message[0], mmio + hpriv->em_loc);
	writel(message[1], mmio + hpriv->em_loc+4);

	/* save off new led state for port/slot */
	emp->led_state = message[1];

	/*
	 * tell hardware to transmit the message
	 */
	writel(em_ctl | EM_CTL_TM, mmio + HOST_EM_CTL);

	spin_unlock_irqrestore(ap->lock, flags);
	return size;
}

static ssize_t ahci_led_show(struct ata_port *ap, char *buf)
{
	struct ahci_port_priv *pp = ap->private_data;
	struct ata_link *link;
	struct ahci_em_priv *emp;
	int rc = 0;

	ata_port_for_each_link(link, ap) {
		emp = &pp->em_priv[link->pmp];
		rc += sprintf(buf, "%lx\n", emp->led_state);
	}
	return rc;
}

static ssize_t ahci_led_store(struct ata_port *ap, const char *buf,
				size_t size)
{
	int state;
	int pmp;
	struct ahci_port_priv *pp = ap->private_data;
	struct ahci_em_priv *emp;

	state = simple_strtoul(buf, NULL, 0);

	/* get the slot number from the message */
	pmp = (state & 0x0000ff00) >> 8;
	if (pmp < MAX_SLOTS)
		emp = &pp->em_priv[pmp];
	else
		return -EINVAL;

	/* mask off the activity bits if we are in sw_activity
	 * mode, user should turn off sw_activity before setting
	 * activity led through em_message
	 */
	if (emp->blink_policy)
		state &= 0xfff8ffff;

	return ahci_transmit_led_message(ap, state, size);
}

static ssize_t ahci_activity_store(struct ata_device *dev, enum sw_activity val)
{
	struct ata_link *link = dev->link;
	struct ata_port *ap = link->ap;
	struct ahci_port_priv *pp = ap->private_data;
	struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
	u32 port_led_state = emp->led_state;

	/* save the desired Activity LED behavior */
	if (val == OFF) {
		/* clear LFLAG */
		link->flags &= ~(ATA_LFLAG_SW_ACTIVITY);

		/* set the LED to OFF */
		port_led_state &= 0xfff80000;
		port_led_state |= (ap->port_no | (link->pmp << 8));
		ahci_transmit_led_message(ap, port_led_state, 4);
	} else {
		link->flags |= ATA_LFLAG_SW_ACTIVITY;
		if (val == BLINK_OFF) {
			/* set LED to ON for idle */
			port_led_state &= 0xfff80000;
			port_led_state |= (ap->port_no | (link->pmp << 8));
			port_led_state |= 0x00010000; /* check this */
			ahci_transmit_led_message(ap, port_led_state, 4);
		}
	}
	emp->blink_policy = val;
	return 0;
}

static ssize_t ahci_activity_show(struct ata_device *dev, char *buf)
{
	struct ata_link *link = dev->link;
	struct ata_port *ap = link->ap;
	struct ahci_port_priv *pp = ap->private_data;
	struct ahci_em_priv *emp = &pp->em_priv[link->pmp];

	/* display the saved value of activity behavior for this
	 * disk.
	 */
	return sprintf(buf, "%d\n", emp->blink_policy);
}

1424 1425 1426 1427 1428 1429 1430 1431 1432 1433 1434 1435 1436 1437 1438 1439 1440 1441 1442 1443 1444 1445 1446 1447 1448 1449 1450 1451
static void ahci_port_init(struct pci_dev *pdev, struct ata_port *ap,
			   int port_no, void __iomem *mmio,
			   void __iomem *port_mmio)
{
	const char *emsg = NULL;
	int rc;
	u32 tmp;

	/* make sure port is not active */
	rc = ahci_deinit_port(ap, &emsg);
	if (rc)
		dev_printk(KERN_WARNING, &pdev->dev,
			   "%s (%d)\n", emsg, rc);

	/* clear SError */
	tmp = readl(port_mmio + PORT_SCR_ERR);
	VPRINTK("PORT_SCR_ERR 0x%x\n", tmp);
	writel(tmp, port_mmio + PORT_SCR_ERR);

	/* clear port IRQ */
	tmp = readl(port_mmio + PORT_IRQ_STAT);
	VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
	if (tmp)
		writel(tmp, port_mmio + PORT_IRQ_STAT);

	writel(1 << port_no, mmio + HOST_IRQ_STAT);
}

1452
static void ahci_init_controller(struct ata_host *host)
1453
{
1454
	struct ahci_host_priv *hpriv = host->private_data;
1455 1456
	struct pci_dev *pdev = to_pci_dev(host->dev);
	void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
1457
	int i;
1458
	void __iomem *port_mmio;
1459
	u32 tmp;
1460
	int mv;
1461

1462
	if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
1463 1464 1465 1466 1467
		if (pdev->device == 0x6121)
			mv = 2;
		else
			mv = 4;
		port_mmio = __ahci_port_base(host, mv);
1468 1469 1470 1471 1472 1473 1474 1475 1476 1477

		writel(0, port_mmio + PORT_IRQ_MASK);

		/* clear port IRQ */
		tmp = readl(port_mmio + PORT_IRQ_STAT);
		VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
		if (tmp)
			writel(tmp, port_mmio + PORT_IRQ_STAT);
	}

1478 1479
	for (i = 0; i < host->n_ports; i++) {
		struct ata_port *ap = host->ports[i];
1480

1481
		port_mmio = ahci_port_base(ap);
1482
		if (ata_port_is_dummy(ap))
1483 1484
			continue;

1485
		ahci_port_init(pdev, ap, i, mmio, port_mmio);
1486 1487 1488 1489 1490 1491 1492 1493 1494
	}

	tmp = readl(mmio + HOST_CTL);
	VPRINTK("HOST_CTL 0x%x\n", tmp);
	writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL);
	tmp = readl(mmio + HOST_CTL);
	VPRINTK("HOST_CTL 0x%x\n", tmp);
}

1495 1496 1497 1498
static void ahci_dev_config(struct ata_device *dev)
{
	struct ahci_host_priv *hpriv = dev->link->ap->host->private_data;

1499
	if (hpriv->flags & AHCI_HFLAG_SECT255) {
1500
		dev->max_sectors = 255;
1501 1502 1503
		ata_dev_printk(dev, KERN_INFO,
			       "SB600 AHCI: limiting to 255 sectors per cmd\n");
	}
1504 1505
}

1506
static unsigned int ahci_dev_classify(struct ata_port *ap)
L
Linus Torvalds 已提交
1507
{
1508
	void __iomem *port_mmio = ahci_port_base(ap);
L
Linus Torvalds 已提交
1509
	struct ata_taskfile tf;
1510 1511 1512 1513 1514 1515 1516 1517 1518 1519 1520
	u32 tmp;

	tmp = readl(port_mmio + PORT_SIG);
	tf.lbah		= (tmp >> 24)	& 0xff;
	tf.lbam		= (tmp >> 16)	& 0xff;
	tf.lbal		= (tmp >> 8)	& 0xff;
	tf.nsect	= (tmp)		& 0xff;

	return ata_dev_classify(&tf);
}

T
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1521 1522
static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,
			       u32 opts)
1523
{
T
Tejun Heo 已提交
1524 1525 1526 1527 1528 1529 1530 1531
	dma_addr_t cmd_tbl_dma;

	cmd_tbl_dma = pp->cmd_tbl_dma + tag * AHCI_CMD_TBL_SZ;

	pp->cmd_slot[tag].opts = cpu_to_le32(opts);
	pp->cmd_slot[tag].status = 0;
	pp->cmd_slot[tag].tbl_addr = cpu_to_le32(cmd_tbl_dma & 0xffffffff);
	pp->cmd_slot[tag].tbl_addr_hi = cpu_to_le32((cmd_tbl_dma >> 16) >> 16);
1532 1533
}

1534
static int ahci_kick_engine(struct ata_port *ap, int force_restart)
T
Tejun Heo 已提交
1535
{
1536
	void __iomem *port_mmio = ahci_port_base(ap);
J
Jeff Garzik 已提交
1537
	struct ahci_host_priv *hpriv = ap->host->private_data;
1538
	u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
1539
	u32 tmp;
1540
	int busy, rc;
1541

1542
	/* do we need to kick the port? */
1543
	busy = status & (ATA_BUSY | ATA_DRQ);
1544 1545 1546 1547 1548 1549 1550 1551 1552 1553 1554 1555 1556 1557 1558 1559 1560 1561
	if (!busy && !force_restart)
		return 0;

	/* stop engine */
	rc = ahci_stop_engine(ap);
	if (rc)
		goto out_restart;

	/* need to do CLO? */
	if (!busy) {
		rc = 0;
		goto out_restart;
	}

	if (!(hpriv->cap & HOST_CAP_CLO)) {
		rc = -EOPNOTSUPP;
		goto out_restart;
	}
1562

1563
	/* perform CLO */
1564 1565 1566 1567
	tmp = readl(port_mmio + PORT_CMD);
	tmp |= PORT_CMD_CLO;
	writel(tmp, port_mmio + PORT_CMD);

1568
	rc = 0;
1569 1570 1571
	tmp = ata_wait_register(port_mmio + PORT_CMD,
				PORT_CMD_CLO, PORT_CMD_CLO, 1, 500);
	if (tmp & PORT_CMD_CLO)
1572
		rc = -EIO;
1573

1574 1575 1576 1577
	/* restart engine */
 out_restart:
	ahci_start_engine(ap);
	return rc;
1578 1579
}

1580 1581 1582
static int ahci_exec_polled_cmd(struct ata_port *ap, int pmp,
				struct ata_taskfile *tf, int is_cmd, u16 flags,
				unsigned long timeout_msec)
1583
{
1584
	const u32 cmd_fis_len = 5; /* five dwords */
T
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1585
	struct ahci_port_priv *pp = ap->private_data;
1586
	void __iomem *port_mmio = ahci_port_base(ap);
1587 1588 1589 1590 1591 1592 1593 1594 1595 1596 1597 1598 1599 1600 1601 1602 1603 1604 1605 1606 1607 1608 1609
	u8 *fis = pp->cmd_tbl;
	u32 tmp;

	/* prep the command */
	ata_tf_to_fis(tf, pmp, is_cmd, fis);
	ahci_fill_cmd_slot(pp, 0, cmd_fis_len | flags | (pmp << 12));

	/* issue & wait */
	writel(1, port_mmio + PORT_CMD_ISSUE);

	if (timeout_msec) {
		tmp = ata_wait_register(port_mmio + PORT_CMD_ISSUE, 0x1, 0x1,
					1, timeout_msec);
		if (tmp & 0x1) {
			ahci_kick_engine(ap, 1);
			return -EBUSY;
		}
	} else
		readl(port_mmio + PORT_CMD_ISSUE);	/* flush */

	return 0;
}

1610 1611 1612
static int ahci_do_softreset(struct ata_link *link, unsigned int *class,
			     int pmp, unsigned long deadline,
			     int (*check_ready)(struct ata_link *link))
1613
{
T
Tejun Heo 已提交
1614
	struct ata_port *ap = link->ap;
T
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1615
	const char *reason = NULL;
1616
	unsigned long now, msecs;
T
Tejun Heo 已提交
1617 1618 1619 1620 1621 1622
	struct ata_taskfile tf;
	int rc;

	DPRINTK("ENTER\n");

	/* prepare for SRST (AHCI-1.1 10.4.1) */
1623
	rc = ahci_kick_engine(ap, 1);
T
Tejun Heo 已提交
1624
	if (rc && rc != -EOPNOTSUPP)
T
Tejun Heo 已提交
1625
		ata_link_printk(link, KERN_WARNING,
T
Tejun Heo 已提交
1626
				"failed to reset engine (errno=%d)\n", rc);
T
Tejun Heo 已提交
1627

T
Tejun Heo 已提交
1628
	ata_tf_init(link->device, &tf);
T
Tejun Heo 已提交
1629 1630

	/* issue the first D2H Register FIS */
1631 1632 1633 1634 1635
	msecs = 0;
	now = jiffies;
	if (time_after(now, deadline))
		msecs = jiffies_to_msecs(deadline - now);

T
Tejun Heo 已提交
1636
	tf.ctl |= ATA_SRST;
1637
	if (ahci_exec_polled_cmd(ap, pmp, &tf, 0,
1638
				 AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY, msecs)) {
T
Tejun Heo 已提交
1639 1640 1641 1642 1643 1644 1645 1646 1647 1648
		rc = -EIO;
		reason = "1st FIS failed";
		goto fail;
	}

	/* spec says at least 5us, but be generous and sleep for 1ms */
	msleep(1);

	/* issue the second D2H Register FIS */
	tf.ctl &= ~ATA_SRST;
1649
	ahci_exec_polled_cmd(ap, pmp, &tf, 0, 0, 0);
T
Tejun Heo 已提交
1650

1651
	/* wait for link to become ready */
1652
	rc = ata_wait_after_reset(link, deadline, check_ready);
T
Tejun Heo 已提交
1653 1654 1655 1656
	/* link occupied, -ENODEV too is an error */
	if (rc) {
		reason = "device not ready";
		goto fail;
T
Tejun Heo 已提交
1657
	}
T
Tejun Heo 已提交
1658
	*class = ahci_dev_classify(ap);
T
Tejun Heo 已提交
1659 1660 1661 1662 1663

	DPRINTK("EXIT, class=%u\n", *class);
	return 0;

 fail:
T
Tejun Heo 已提交
1664
	ata_link_printk(link, KERN_ERR, "softreset failed (%s)\n", reason);
T
Tejun Heo 已提交
1665 1666 1667
	return rc;
}

1668 1669 1670 1671 1672 1673 1674 1675 1676 1677 1678 1679 1680 1681 1682 1683 1684 1685 1686 1687 1688 1689 1690 1691 1692 1693 1694 1695 1696 1697 1698 1699 1700 1701 1702 1703 1704 1705 1706 1707 1708 1709 1710 1711 1712 1713 1714 1715 1716 1717 1718 1719 1720 1721 1722 1723 1724 1725 1726 1727 1728 1729 1730 1731 1732 1733
static int ahci_check_ready(struct ata_link *link)
{
	void __iomem *port_mmio = ahci_port_base(link->ap);
	u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;

	return ata_check_ready(status);
}

static int ahci_softreset(struct ata_link *link, unsigned int *class,
			  unsigned long deadline)
{
	int pmp = sata_srst_pmp(link);

	DPRINTK("ENTER\n");

	return ahci_do_softreset(link, class, pmp, deadline, ahci_check_ready);
}

static int ahci_sb600_check_ready(struct ata_link *link)
{
	void __iomem *port_mmio = ahci_port_base(link->ap);
	u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
	u32 irq_status = readl(port_mmio + PORT_IRQ_STAT);

	/*
	 * There is no need to check TFDATA if BAD PMP is found due to HW bug,
	 * which can save timeout delay.
	 */
	if (irq_status & PORT_IRQ_BAD_PMP)
		return -EIO;

	return ata_check_ready(status);
}

static int ahci_sb600_softreset(struct ata_link *link, unsigned int *class,
				unsigned long deadline)
{
	struct ata_port *ap = link->ap;
	void __iomem *port_mmio = ahci_port_base(ap);
	int pmp = sata_srst_pmp(link);
	int rc;
	u32 irq_sts;

	DPRINTK("ENTER\n");

	rc = ahci_do_softreset(link, class, pmp, deadline,
			       ahci_sb600_check_ready);

	/*
	 * Soft reset fails on some ATI chips with IPMS set when PMP
	 * is enabled but SATA HDD/ODD is connected to SATA port,
	 * do soft reset again to port 0.
	 */
	if (rc == -EIO) {
		irq_sts = readl(port_mmio + PORT_IRQ_STAT);
		if (irq_sts & PORT_IRQ_BAD_PMP) {
			ata_link_printk(link, KERN_WARNING,
					"failed due to HW bug, retry pmp=0\n");
			rc = ahci_do_softreset(link, class, 0, deadline,
					       ahci_check_ready);
		}
	}

	return rc;
}

T
Tejun Heo 已提交
1734
static int ahci_hardreset(struct ata_link *link, unsigned int *class,
1735
			  unsigned long deadline)
1736
{
1737
	const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context);
T
Tejun Heo 已提交
1738
	struct ata_port *ap = link->ap;
1739 1740 1741
	struct ahci_port_priv *pp = ap->private_data;
	u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
	struct ata_taskfile tf;
1742
	bool online;
1743 1744 1745
	int rc;

	DPRINTK("ENTER\n");
L
Linus Torvalds 已提交
1746

1747
	ahci_stop_engine(ap);
1748 1749

	/* clear D2H reception area to properly wait for D2H FIS */
T
Tejun Heo 已提交
1750
	ata_tf_init(link->device, &tf);
1751
	tf.command = 0x80;
1752
	ata_tf_to_fis(&tf, 0, 0, d2h_fis);
1753

1754 1755
	rc = sata_link_hardreset(link, timing, deadline, &online,
				 ahci_check_ready);
1756

1757
	ahci_start_engine(ap);
L
Linus Torvalds 已提交
1758

1759
	if (online)
1760
		*class = ahci_dev_classify(ap);
L
Linus Torvalds 已提交
1761

1762 1763 1764 1765
	DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
	return rc;
}

T
Tejun Heo 已提交
1766
static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
1767
				 unsigned long deadline)
1768
{
T
Tejun Heo 已提交
1769
	struct ata_port *ap = link->ap;
1770
	bool online;
1771 1772 1773 1774
	int rc;

	DPRINTK("ENTER\n");

1775
	ahci_stop_engine(ap);
1776

T
Tejun Heo 已提交
1777
	rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
1778
				 deadline, &online, NULL);
1779

1780
	ahci_start_engine(ap);
1781 1782 1783 1784 1785 1786

	DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);

	/* vt8251 doesn't clear BSY on signature FIS reception,
	 * request follow-up softreset.
	 */
1787
	return online ? -EAGAIN : rc;
1788 1789
}

1790 1791 1792 1793 1794 1795 1796
static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
				unsigned long deadline)
{
	struct ata_port *ap = link->ap;
	struct ahci_port_priv *pp = ap->private_data;
	u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
	struct ata_taskfile tf;
1797
	bool online;
1798 1799 1800 1801 1802 1803 1804 1805 1806 1807
	int rc;

	ahci_stop_engine(ap);

	/* clear D2H reception area to properly wait for D2H FIS */
	ata_tf_init(link->device, &tf);
	tf.command = 0x80;
	ata_tf_to_fis(&tf, 0, 0, d2h_fis);

	rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
1808
				 deadline, &online, NULL);
1809 1810 1811 1812 1813 1814 1815 1816 1817 1818 1819 1820 1821 1822 1823 1824

	ahci_start_engine(ap);

	/* The pseudo configuration device on SIMG4726 attached to
	 * ASUS P5W-DH Deluxe doesn't send signature FIS after
	 * hardreset if no device is attached to the first downstream
	 * port && the pseudo device locks up on SRST w/ PMP==0.  To
	 * work around this, wait for !BSY only briefly.  If BSY isn't
	 * cleared, perform CLO and proceed to IDENTIFY (achieved by
	 * ATA_LFLAG_NO_SRST and ATA_LFLAG_ASSUME_ATA).
	 *
	 * Wait for two seconds.  Devices attached to downstream port
	 * which can't process the following IDENTIFY after this will
	 * have to be reset again.  For most cases, this should
	 * suffice while making probing snappish enough.
	 */
1825 1826 1827 1828 1829 1830 1831
	if (online) {
		rc = ata_wait_after_reset(link, jiffies + 2 * HZ,
					  ahci_check_ready);
		if (rc)
			ahci_kick_engine(ap, 0);
	}
	return rc;
1832 1833
}

T
Tejun Heo 已提交
1834
static void ahci_postreset(struct ata_link *link, unsigned int *class)
1835
{
T
Tejun Heo 已提交
1836
	struct ata_port *ap = link->ap;
1837
	void __iomem *port_mmio = ahci_port_base(ap);
1838 1839
	u32 new_tmp, tmp;

1840
	ata_std_postreset(link, class);
1841 1842 1843

	/* Make sure port's ATAPI bit is set appropriately */
	new_tmp = tmp = readl(port_mmio + PORT_CMD);
1844
	if (*class == ATA_DEV_ATAPI)
1845 1846 1847 1848 1849 1850 1851
		new_tmp |= PORT_CMD_ATAPI;
	else
		new_tmp &= ~PORT_CMD_ATAPI;
	if (new_tmp != tmp) {
		writel(new_tmp, port_mmio + PORT_CMD);
		readl(port_mmio + PORT_CMD); /* flush */
	}
L
Linus Torvalds 已提交
1852 1853
}

T
Tejun Heo 已提交
1854
static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl)
L
Linus Torvalds 已提交
1855
{
1856
	struct scatterlist *sg;
T
Tejun Heo 已提交
1857 1858
	struct ahci_sg *ahci_sg = cmd_tbl + AHCI_CMD_TBL_HDR_SZ;
	unsigned int si;
L
Linus Torvalds 已提交
1859 1860 1861 1862 1863 1864

	VPRINTK("ENTER\n");

	/*
	 * Next, the S/G list.
	 */
T
Tejun Heo 已提交
1865
	for_each_sg(qc->sg, sg, qc->n_elem, si) {
1866 1867 1868
		dma_addr_t addr = sg_dma_address(sg);
		u32 sg_len = sg_dma_len(sg);

T
Tejun Heo 已提交
1869 1870 1871
		ahci_sg[si].addr = cpu_to_le32(addr & 0xffffffff);
		ahci_sg[si].addr_hi = cpu_to_le32((addr >> 16) >> 16);
		ahci_sg[si].flags_size = cpu_to_le32(sg_len - 1);
L
Linus Torvalds 已提交
1872
	}
1873

T
Tejun Heo 已提交
1874
	return si;
L
Linus Torvalds 已提交
1875 1876 1877 1878
}

static void ahci_qc_prep(struct ata_queued_cmd *qc)
{
1879 1880
	struct ata_port *ap = qc->ap;
	struct ahci_port_priv *pp = ap->private_data;
T
Tejun Heo 已提交
1881
	int is_atapi = ata_is_atapi(qc->tf.protocol);
T
Tejun Heo 已提交
1882
	void *cmd_tbl;
L
Linus Torvalds 已提交
1883 1884
	u32 opts;
	const u32 cmd_fis_len = 5; /* five dwords */
1885
	unsigned int n_elem;
L
Linus Torvalds 已提交
1886 1887 1888 1889 1890

	/*
	 * Fill in command table information.  First, the header,
	 * a SATA Register - Host to Device command FIS.
	 */
T
Tejun Heo 已提交
1891 1892
	cmd_tbl = pp->cmd_tbl + qc->tag * AHCI_CMD_TBL_SZ;

T
Tejun Heo 已提交
1893
	ata_tf_to_fis(&qc->tf, qc->dev->link->pmp, 1, cmd_tbl);
1894
	if (is_atapi) {
T
Tejun Heo 已提交
1895 1896
		memset(cmd_tbl + AHCI_CMD_TBL_CDB, 0, 32);
		memcpy(cmd_tbl + AHCI_CMD_TBL_CDB, qc->cdb, qc->dev->cdb_len);
1897
	}
L
Linus Torvalds 已提交
1898

1899 1900
	n_elem = 0;
	if (qc->flags & ATA_QCFLAG_DMAMAP)
T
Tejun Heo 已提交
1901
		n_elem = ahci_fill_sg(qc, cmd_tbl);
L
Linus Torvalds 已提交
1902

1903 1904 1905
	/*
	 * Fill in command slot information.
	 */
T
Tejun Heo 已提交
1906
	opts = cmd_fis_len | n_elem << 16 | (qc->dev->link->pmp << 12);
1907 1908 1909
	if (qc->tf.flags & ATA_TFLAG_WRITE)
		opts |= AHCI_CMD_WRITE;
	if (is_atapi)
1910
		opts |= AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH;
1911

T
Tejun Heo 已提交
1912
	ahci_fill_cmd_slot(pp, qc->tag, opts);
L
Linus Torvalds 已提交
1913 1914
}

T
Tejun Heo 已提交
1915
static void ahci_error_intr(struct ata_port *ap, u32 irq_stat)
L
Linus Torvalds 已提交
1916
{
1917
	struct ahci_host_priv *hpriv = ap->host->private_data;
T
Tejun Heo 已提交
1918
	struct ahci_port_priv *pp = ap->private_data;
T
Tejun Heo 已提交
1919 1920 1921 1922
	struct ata_eh_info *host_ehi = &ap->link.eh_info;
	struct ata_link *link = NULL;
	struct ata_queued_cmd *active_qc;
	struct ata_eh_info *active_ehi;
T
Tejun Heo 已提交
1923
	u32 serror;
L
Linus Torvalds 已提交
1924

T
Tejun Heo 已提交
1925 1926 1927 1928 1929 1930 1931 1932 1933 1934 1935 1936 1937
	/* determine active link */
	ata_port_for_each_link(link, ap)
		if (ata_link_active(link))
			break;
	if (!link)
		link = &ap->link;

	active_qc = ata_qc_from_tag(ap, link->active_tag);
	active_ehi = &link->eh_info;

	/* record irq stat */
	ata_ehi_clear_desc(host_ehi);
	ata_ehi_push_desc(host_ehi, "irq_stat 0x%08x", irq_stat);
L
Linus Torvalds 已提交
1938

T
Tejun Heo 已提交
1939
	/* AHCI needs SError cleared; otherwise, it might lock up */
1940
	ahci_scr_read(ap, SCR_ERROR, &serror);
T
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1941
	ahci_scr_write(ap, SCR_ERROR, serror);
T
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1942
	host_ehi->serror |= serror;
T
Tejun Heo 已提交
1943

1944
	/* some controllers set IRQ_IF_ERR on device errors, ignore it */
1945
	if (hpriv->flags & AHCI_HFLAG_IGN_IRQ_IF_ERR)
1946 1947
		irq_stat &= ~PORT_IRQ_IF_ERR;

1948
	if (irq_stat & PORT_IRQ_TF_ERR) {
T
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1949 1950 1951 1952 1953 1954 1955 1956 1957
		/* If qc is active, charge it; otherwise, the active
		 * link.  There's no active qc on NCQ errors.  It will
		 * be determined by EH by reading log page 10h.
		 */
		if (active_qc)
			active_qc->err_mask |= AC_ERR_DEV;
		else
			active_ehi->err_mask |= AC_ERR_DEV;

1958
		if (hpriv->flags & AHCI_HFLAG_IGN_SERR_INTERNAL)
T
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1959 1960 1961 1962 1963 1964 1965
			host_ehi->serror &= ~SERR_INTERNAL;
	}

	if (irq_stat & PORT_IRQ_UNK_FIS) {
		u32 *unk = (u32 *)(pp->rx_fis + RX_FIS_UNK);

		active_ehi->err_mask |= AC_ERR_HSM;
T
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1966
		active_ehi->action |= ATA_EH_RESET;
T
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1967 1968 1969 1970 1971
		ata_ehi_push_desc(active_ehi,
				  "unknown FIS %08x %08x %08x %08x" ,
				  unk[0], unk[1], unk[2], unk[3]);
	}

T
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1972
	if (sata_pmp_attached(ap) && (irq_stat & PORT_IRQ_BAD_PMP)) {
T
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1973
		active_ehi->err_mask |= AC_ERR_HSM;
T
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1974
		active_ehi->action |= ATA_EH_RESET;
T
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1975
		ata_ehi_push_desc(active_ehi, "incorrect PMP");
1976
	}
T
Tejun Heo 已提交
1977 1978

	if (irq_stat & (PORT_IRQ_HBUS_ERR | PORT_IRQ_HBUS_DATA_ERR)) {
T
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1979
		host_ehi->err_mask |= AC_ERR_HOST_BUS;
T
Tejun Heo 已提交
1980
		host_ehi->action |= ATA_EH_RESET;
T
Tejun Heo 已提交
1981
		ata_ehi_push_desc(host_ehi, "host bus error");
L
Linus Torvalds 已提交
1982 1983
	}

T
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1984
	if (irq_stat & PORT_IRQ_IF_ERR) {
T
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1985
		host_ehi->err_mask |= AC_ERR_ATA_BUS;
T
Tejun Heo 已提交
1986
		host_ehi->action |= ATA_EH_RESET;
T
Tejun Heo 已提交
1987
		ata_ehi_push_desc(host_ehi, "interface fatal error");
T
Tejun Heo 已提交
1988
	}
L
Linus Torvalds 已提交
1989

T
Tejun Heo 已提交
1990
	if (irq_stat & (PORT_IRQ_CONNECT | PORT_IRQ_PHYRDY)) {
T
Tejun Heo 已提交
1991 1992 1993
		ata_ehi_hotplugged(host_ehi);
		ata_ehi_push_desc(host_ehi, "%s",
			irq_stat & PORT_IRQ_CONNECT ?
T
Tejun Heo 已提交
1994 1995 1996 1997
			"connection status changed" : "PHY RDY changed");
	}

	/* okay, let's hand over to EH */
1998

T
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1999 2000 2001 2002
	if (irq_stat & PORT_IRQ_FREEZE)
		ata_port_freeze(ap);
	else
		ata_port_abort(ap);
L
Linus Torvalds 已提交
2003 2004
}

2005
static void ahci_port_intr(struct ata_port *ap)
L
Linus Torvalds 已提交
2006
{
2007
	void __iomem *port_mmio = ahci_port_base(ap);
T
Tejun Heo 已提交
2008
	struct ata_eh_info *ehi = &ap->link.eh_info;
2009
	struct ahci_port_priv *pp = ap->private_data;
T
Tejun Heo 已提交
2010
	struct ahci_host_priv *hpriv = ap->host->private_data;
2011
	int resetting = !!(ap->pflags & ATA_PFLAG_RESETTING);
T
Tejun Heo 已提交
2012
	u32 status, qc_active;
2013
	int rc;
L
Linus Torvalds 已提交
2014 2015 2016 2017

	status = readl(port_mmio + PORT_IRQ_STAT);
	writel(status, port_mmio + PORT_IRQ_STAT);

2018 2019 2020 2021
	/* ignore BAD_PMP while resetting */
	if (unlikely(resetting))
		status &= ~PORT_IRQ_BAD_PMP;

2022 2023 2024 2025 2026 2027 2028 2029 2030 2031 2032
	/* If we are getting PhyRdy, this is
 	 * just a power state change, we should
 	 * clear out this, plus the PhyRdy/Comm
 	 * Wake bits from Serror
 	 */
	if ((hpriv->flags & AHCI_HFLAG_NO_HOTPLUG) &&
		(status & PORT_IRQ_PHYRDY)) {
		status &= ~PORT_IRQ_PHYRDY;
		ahci_scr_write(ap, SCR_ERROR, ((1 << 16) | (1 << 18)));
	}

T
Tejun Heo 已提交
2033 2034 2035
	if (unlikely(status & PORT_IRQ_ERROR)) {
		ahci_error_intr(ap, status);
		return;
L
Linus Torvalds 已提交
2036 2037
	}

2038
	if (status & PORT_IRQ_SDB_FIS) {
T
Tejun Heo 已提交
2039 2040 2041 2042 2043 2044 2045 2046
		/* If SNotification is available, leave notification
		 * handling to sata_async_notification().  If not,
		 * emulate it by snooping SDB FIS RX area.
		 *
		 * Snooping FIS RX area is probably cheaper than
		 * poking SNotification but some constrollers which
		 * implement SNotification, ICH9 for example, don't
		 * store AN SDB FIS into receive area.
2047
		 */
T
Tejun Heo 已提交
2048
		if (hpriv->cap & HOST_CAP_SNTF)
2049
			sata_async_notification(ap);
T
Tejun Heo 已提交
2050 2051 2052 2053 2054 2055 2056 2057 2058 2059 2060
		else {
			/* If the 'N' bit in word 0 of the FIS is set,
			 * we just received asynchronous notification.
			 * Tell libata about it.
			 */
			const __le32 *f = pp->rx_fis + RX_FIS_SDB;
			u32 f0 = le32_to_cpu(f[0]);

			if (f0 & (1 << 15))
				sata_async_notification(ap);
		}
2061 2062
	}

T
Tejun Heo 已提交
2063 2064
	/* pp->active_link is valid iff any command is in flight */
	if (ap->qc_active && pp->active_link->sactive)
T
Tejun Heo 已提交
2065 2066 2067 2068
		qc_active = readl(port_mmio + PORT_SCR_ACT);
	else
		qc_active = readl(port_mmio + PORT_CMD_ISSUE);

2069
	rc = ata_qc_complete_multiple(ap, qc_active);
2070

2071 2072
	/* while resetting, invalid completions are expected */
	if (unlikely(rc < 0 && !resetting)) {
T
Tejun Heo 已提交
2073
		ehi->err_mask |= AC_ERR_HSM;
T
Tejun Heo 已提交
2074
		ehi->action |= ATA_EH_RESET;
T
Tejun Heo 已提交
2075
		ata_port_freeze(ap);
L
Linus Torvalds 已提交
2076 2077 2078
	}
}

2079
static irqreturn_t ahci_interrupt(int irq, void *dev_instance)
L
Linus Torvalds 已提交
2080
{
J
Jeff Garzik 已提交
2081
	struct ata_host *host = dev_instance;
L
Linus Torvalds 已提交
2082 2083
	struct ahci_host_priv *hpriv;
	unsigned int i, handled = 0;
2084
	void __iomem *mmio;
2085
	u32 irq_stat, irq_masked;
L
Linus Torvalds 已提交
2086 2087 2088

	VPRINTK("ENTER\n");

J
Jeff Garzik 已提交
2089
	hpriv = host->private_data;
T
Tejun Heo 已提交
2090
	mmio = host->iomap[AHCI_PCI_BAR];
L
Linus Torvalds 已提交
2091 2092 2093 2094 2095 2096

	/* sigh.  0xffffffff is a valid return from h/w */
	irq_stat = readl(mmio + HOST_IRQ_STAT);
	if (!irq_stat)
		return IRQ_NONE;

2097 2098
	irq_masked = irq_stat & hpriv->port_map;

2099
	spin_lock(&host->lock);
L
Linus Torvalds 已提交
2100

2101
	for (i = 0; i < host->n_ports; i++) {
L
Linus Torvalds 已提交
2102 2103
		struct ata_port *ap;

2104
		if (!(irq_masked & (1 << i)))
2105 2106
			continue;

J
Jeff Garzik 已提交
2107
		ap = host->ports[i];
2108
		if (ap) {
2109
			ahci_port_intr(ap);
2110 2111 2112
			VPRINTK("port %u\n", i);
		} else {
			VPRINTK("port %u (no irq)\n", i);
2113
			if (ata_ratelimit())
J
Jeff Garzik 已提交
2114
				dev_printk(KERN_WARNING, host->dev,
2115
					"interrupt on disabled port %u\n", i);
L
Linus Torvalds 已提交
2116
		}
2117

L
Linus Torvalds 已提交
2118 2119 2120
		handled = 1;
	}

2121 2122 2123 2124 2125 2126 2127 2128 2129
	/* HOST_IRQ_STAT behaves as level triggered latch meaning that
	 * it should be cleared after all the port events are cleared;
	 * otherwise, it will raise a spurious interrupt after each
	 * valid one.  Please read section 10.6.2 of ahci 1.1 for more
	 * information.
	 *
	 * Also, use the unmasked value to clear interrupt as spurious
	 * pending event on a dummy port might cause screaming IRQ.
	 */
2130 2131
	writel(irq_stat, mmio + HOST_IRQ_STAT);

J
Jeff Garzik 已提交
2132
	spin_unlock(&host->lock);
L
Linus Torvalds 已提交
2133 2134 2135 2136 2137 2138

	VPRINTK("EXIT\n");

	return IRQ_RETVAL(handled);
}

2139
static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc)
L
Linus Torvalds 已提交
2140 2141
{
	struct ata_port *ap = qc->ap;
2142
	void __iomem *port_mmio = ahci_port_base(ap);
T
Tejun Heo 已提交
2143 2144 2145 2146 2147 2148 2149
	struct ahci_port_priv *pp = ap->private_data;

	/* Keep track of the currently active link.  It will be used
	 * in completion path to determine whether NCQ phase is in
	 * progress.
	 */
	pp->active_link = qc->dev->link;
L
Linus Torvalds 已提交
2150

T
Tejun Heo 已提交
2151 2152 2153
	if (qc->tf.protocol == ATA_PROT_NCQ)
		writel(1 << qc->tag, port_mmio + PORT_SCR_ACT);
	writel(1 << qc->tag, port_mmio + PORT_CMD_ISSUE);
L
Linus Torvalds 已提交
2154

2155 2156
	ahci_sw_activity(qc->dev->link);

L
Linus Torvalds 已提交
2157 2158 2159
	return 0;
}

2160 2161 2162 2163 2164 2165 2166 2167 2168
static bool ahci_qc_fill_rtf(struct ata_queued_cmd *qc)
{
	struct ahci_port_priv *pp = qc->ap->private_data;
	u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;

	ata_tf_from_fis(d2h_fis, &qc->result_tf);
	return true;
}

T
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2169 2170
static void ahci_freeze(struct ata_port *ap)
{
2171
	void __iomem *port_mmio = ahci_port_base(ap);
T
Tejun Heo 已提交
2172 2173 2174 2175 2176 2177 2178

	/* turn IRQ off */
	writel(0, port_mmio + PORT_IRQ_MASK);
}

static void ahci_thaw(struct ata_port *ap)
{
T
Tejun Heo 已提交
2179
	void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR];
2180
	void __iomem *port_mmio = ahci_port_base(ap);
T
Tejun Heo 已提交
2181
	u32 tmp;
2182
	struct ahci_port_priv *pp = ap->private_data;
T
Tejun Heo 已提交
2183 2184 2185 2186

	/* clear IRQ */
	tmp = readl(port_mmio + PORT_IRQ_STAT);
	writel(tmp, port_mmio + PORT_IRQ_STAT);
2187
	writel(1 << ap->port_no, mmio + HOST_IRQ_STAT);
T
Tejun Heo 已提交
2188

2189 2190
	/* turn IRQ back on */
	writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
T
Tejun Heo 已提交
2191 2192 2193 2194
}

static void ahci_error_handler(struct ata_port *ap)
{
2195
	if (!(ap->pflags & ATA_PFLAG_FROZEN)) {
T
Tejun Heo 已提交
2196
		/* restart engine */
2197 2198
		ahci_stop_engine(ap);
		ahci_start_engine(ap);
T
Tejun Heo 已提交
2199 2200
	}

2201
	sata_pmp_error_handler(ap);
2202 2203
}

T
Tejun Heo 已提交
2204 2205 2206 2207
static void ahci_post_internal_cmd(struct ata_queued_cmd *qc)
{
	struct ata_port *ap = qc->ap;

2208 2209 2210
	/* make DMA engine forget about the failed command */
	if (qc->flags & ATA_QCFLAG_FAILED)
		ahci_kick_engine(ap, 1);
T
Tejun Heo 已提交
2211 2212
}

T
Tejun Heo 已提交
2213 2214 2215
static void ahci_pmp_attach(struct ata_port *ap)
{
	void __iomem *port_mmio = ahci_port_base(ap);
2216
	struct ahci_port_priv *pp = ap->private_data;
T
Tejun Heo 已提交
2217 2218 2219 2220 2221
	u32 cmd;

	cmd = readl(port_mmio + PORT_CMD);
	cmd |= PORT_CMD_PMP;
	writel(cmd, port_mmio + PORT_CMD);
2222 2223 2224

	pp->intr_mask |= PORT_IRQ_BAD_PMP;
	writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
T
Tejun Heo 已提交
2225 2226 2227 2228 2229
}

static void ahci_pmp_detach(struct ata_port *ap)
{
	void __iomem *port_mmio = ahci_port_base(ap);
2230
	struct ahci_port_priv *pp = ap->private_data;
T
Tejun Heo 已提交
2231 2232 2233 2234 2235
	u32 cmd;

	cmd = readl(port_mmio + PORT_CMD);
	cmd &= ~PORT_CMD_PMP;
	writel(cmd, port_mmio + PORT_CMD);
2236 2237 2238

	pp->intr_mask &= ~PORT_IRQ_BAD_PMP;
	writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
T
Tejun Heo 已提交
2239 2240
}

2241 2242 2243 2244 2245
static int ahci_port_resume(struct ata_port *ap)
{
	ahci_power_up(ap);
	ahci_start_port(ap);

T
Tejun Heo 已提交
2246
	if (sata_pmp_attached(ap))
T
Tejun Heo 已提交
2247 2248 2249 2250
		ahci_pmp_attach(ap);
	else
		ahci_pmp_detach(ap);

2251 2252 2253
	return 0;
}

2254
#ifdef CONFIG_PM
2255 2256 2257 2258 2259
static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg)
{
	const char *emsg = NULL;
	int rc;

2260
	rc = ahci_deinit_port(ap, &emsg);
2261
	if (rc == 0)
2262
		ahci_power_down(ap);
2263
	else {
2264
		ata_port_printk(ap, KERN_ERR, "%s (%d)\n", emsg, rc);
2265
		ahci_start_port(ap);
2266 2267 2268 2269 2270 2271 2272
	}

	return rc;
}

static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
{
J
Jeff Garzik 已提交
2273
	struct ata_host *host = dev_get_drvdata(&pdev->dev);
T
Tejun Heo 已提交
2274
	void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
2275 2276
	u32 ctl;

2277
	if (mesg.event & PM_EVENT_SLEEP) {
2278 2279 2280 2281 2282 2283 2284 2285 2286 2287 2288 2289 2290 2291 2292
		/* AHCI spec rev1.1 section 8.3.3:
		 * Software must disable interrupts prior to requesting a
		 * transition of the HBA to D3 state.
		 */
		ctl = readl(mmio + HOST_CTL);
		ctl &= ~HOST_IRQ_EN;
		writel(ctl, mmio + HOST_CTL);
		readl(mmio + HOST_CTL); /* flush */
	}

	return ata_pci_device_suspend(pdev, mesg);
}

static int ahci_pci_device_resume(struct pci_dev *pdev)
{
J
Jeff Garzik 已提交
2293
	struct ata_host *host = dev_get_drvdata(&pdev->dev);
2294 2295
	int rc;

2296 2297 2298
	rc = ata_pci_device_do_resume(pdev);
	if (rc)
		return rc;
2299 2300

	if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
2301
		rc = ahci_reset_controller(host);
2302 2303 2304
		if (rc)
			return rc;

2305
		ahci_init_controller(host);
2306 2307
	}

J
Jeff Garzik 已提交
2308
	ata_host_resume(host);
2309 2310 2311

	return 0;
}
2312
#endif
2313

2314 2315
static int ahci_port_start(struct ata_port *ap)
{
J
Jeff Garzik 已提交
2316
	struct device *dev = ap->host->dev;
2317 2318 2319 2320
	struct ahci_port_priv *pp;
	void *mem;
	dma_addr_t mem_dma;

2321
	pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
2322 2323 2324
	if (!pp)
		return -ENOMEM;

2325 2326 2327
	mem = dmam_alloc_coherent(dev, AHCI_PORT_PRIV_DMA_SZ, &mem_dma,
				  GFP_KERNEL);
	if (!mem)
2328 2329 2330 2331 2332 2333 2334 2335 2336 2337 2338 2339 2340 2341 2342 2343 2344 2345 2346 2347 2348 2349 2350 2351 2352 2353 2354 2355 2356
		return -ENOMEM;
	memset(mem, 0, AHCI_PORT_PRIV_DMA_SZ);

	/*
	 * First item in chunk of DMA memory: 32-slot command table,
	 * 32 bytes each in size
	 */
	pp->cmd_slot = mem;
	pp->cmd_slot_dma = mem_dma;

	mem += AHCI_CMD_SLOT_SZ;
	mem_dma += AHCI_CMD_SLOT_SZ;

	/*
	 * Second item: Received-FIS area
	 */
	pp->rx_fis = mem;
	pp->rx_fis_dma = mem_dma;

	mem += AHCI_RX_FIS_SZ;
	mem_dma += AHCI_RX_FIS_SZ;

	/*
	 * Third item: data area for storing a single command
	 * and its scatter-gather table
	 */
	pp->cmd_tbl = mem;
	pp->cmd_tbl_dma = mem_dma;

2357
	/*
2358 2359 2360
	 * Save off initial list of interrupts to be enabled.
	 * This could be changed later
	 */
2361 2362
	pp->intr_mask = DEF_PORT_IRQ;

2363 2364
	ap->private_data = pp;

2365 2366
	/* engage engines, captain */
	return ahci_port_resume(ap);
2367 2368 2369 2370
}

static void ahci_port_stop(struct ata_port *ap)
{
2371 2372
	const char *emsg = NULL;
	int rc;
2373

2374
	/* de-initialize port */
2375
	rc = ahci_deinit_port(ap, &emsg);
2376 2377
	if (rc)
		ata_port_printk(ap, KERN_WARNING, "%s (%d)\n", emsg, rc);
2378 2379
}

2380
static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac)
L
Linus Torvalds 已提交
2381 2382 2383 2384 2385 2386 2387 2388 2389
{
	int rc;

	if (using_dac &&
	    !pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
		rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
		if (rc) {
			rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
			if (rc) {
2390 2391
				dev_printk(KERN_ERR, &pdev->dev,
					   "64-bit DMA enable failed\n");
L
Linus Torvalds 已提交
2392 2393 2394 2395 2396 2397
				return rc;
			}
		}
	} else {
		rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
		if (rc) {
2398 2399
			dev_printk(KERN_ERR, &pdev->dev,
				   "32-bit DMA enable failed\n");
L
Linus Torvalds 已提交
2400 2401 2402 2403
			return rc;
		}
		rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
		if (rc) {
2404 2405
			dev_printk(KERN_ERR, &pdev->dev,
				   "32-bit consistent DMA enable failed\n");
L
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2406 2407 2408 2409 2410 2411
			return rc;
		}
	}
	return 0;
}

2412
static void ahci_print_info(struct ata_host *host)
L
Linus Torvalds 已提交
2413
{
2414 2415 2416
	struct ahci_host_priv *hpriv = host->private_data;
	struct pci_dev *pdev = to_pci_dev(host->dev);
	void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
L
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2417 2418 2419 2420 2421 2422 2423 2424 2425 2426 2427 2428 2429 2430 2431 2432 2433 2434
	u32 vers, cap, impl, speed;
	const char *speed_s;
	u16 cc;
	const char *scc_s;

	vers = readl(mmio + HOST_VERSION);
	cap = hpriv->cap;
	impl = hpriv->port_map;

	speed = (cap >> 20) & 0xf;
	if (speed == 1)
		speed_s = "1.5";
	else if (speed == 2)
		speed_s = "3";
	else
		speed_s = "?";

	pci_read_config_word(pdev, 0x0a, &cc);
2435
	if (cc == PCI_CLASS_STORAGE_IDE)
L
Linus Torvalds 已提交
2436
		scc_s = "IDE";
2437
	else if (cc == PCI_CLASS_STORAGE_SATA)
L
Linus Torvalds 已提交
2438
		scc_s = "SATA";
2439
	else if (cc == PCI_CLASS_STORAGE_RAID)
L
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		scc_s = "RAID";
	else
		scc_s = "unknown";

2444 2445
	dev_printk(KERN_INFO, &pdev->dev,
		"AHCI %02x%02x.%02x%02x "
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		"%u slots %u ports %s Gbps 0x%x impl %s mode\n"
2447
		,
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2449 2450 2451 2452
		(vers >> 24) & 0xff,
		(vers >> 16) & 0xff,
		(vers >> 8) & 0xff,
		vers & 0xff,
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		((cap >> 8) & 0x1f) + 1,
		(cap & 0x1f) + 1,
		speed_s,
		impl,
		scc_s);

2460 2461
	dev_printk(KERN_INFO, &pdev->dev,
		"flags: "
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		"%s%s%s%s%s%s%s"
2463 2464
		"%s%s%s%s%s%s%s"
		"%s\n"
2465
		,
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		cap & (1 << 31) ? "64bit " : "",
		cap & (1 << 30) ? "ncq " : "",
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		cap & (1 << 29) ? "sntf " : "",
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		cap & (1 << 28) ? "ilck " : "",
		cap & (1 << 27) ? "stag " : "",
		cap & (1 << 26) ? "pm " : "",
		cap & (1 << 25) ? "led " : "",

		cap & (1 << 24) ? "clo " : "",
		cap & (1 << 19) ? "nz " : "",
		cap & (1 << 18) ? "only " : "",
		cap & (1 << 17) ? "pmp " : "",
		cap & (1 << 15) ? "pio " : "",
		cap & (1 << 14) ? "slum " : "",
2481 2482
		cap & (1 << 13) ? "part " : "",
		cap & (1 << 6) ? "ems ": ""
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		);
}

2486 2487 2488 2489 2490 2491 2492 2493 2494 2495 2496 2497 2498 2499 2500 2501 2502 2503 2504 2505 2506 2507 2508 2509 2510 2511 2512 2513 2514 2515 2516 2517 2518 2519 2520 2521 2522 2523 2524 2525 2526 2527 2528 2529 2530
/* On ASUS P5W DH Deluxe, the second port of PCI device 00:1f.2 is
 * hardwired to on-board SIMG 4726.  The chipset is ICH8 and doesn't
 * support PMP and the 4726 either directly exports the device
 * attached to the first downstream port or acts as a hardware storage
 * controller and emulate a single ATA device (can be RAID 0/1 or some
 * other configuration).
 *
 * When there's no device attached to the first downstream port of the
 * 4726, "Config Disk" appears, which is a pseudo ATA device to
 * configure the 4726.  However, ATA emulation of the device is very
 * lame.  It doesn't send signature D2H Reg FIS after the initial
 * hardreset, pukes on SRST w/ PMP==0 and has bunch of other issues.
 *
 * The following function works around the problem by always using
 * hardreset on the port and not depending on receiving signature FIS
 * afterward.  If signature FIS isn't received soon, ATA class is
 * assumed without follow-up softreset.
 */
static void ahci_p5wdh_workaround(struct ata_host *host)
{
	static struct dmi_system_id sysids[] = {
		{
			.ident = "P5W DH Deluxe",
			.matches = {
				DMI_MATCH(DMI_SYS_VENDOR,
					  "ASUSTEK COMPUTER INC"),
				DMI_MATCH(DMI_PRODUCT_NAME, "P5W DH Deluxe"),
			},
		},
		{ }
	};
	struct pci_dev *pdev = to_pci_dev(host->dev);

	if (pdev->bus->number == 0 && pdev->devfn == PCI_DEVFN(0x1f, 2) &&
	    dmi_check_system(sysids)) {
		struct ata_port *ap = host->ports[1];

		dev_printk(KERN_INFO, &pdev->dev, "enabling ASUS P5W DH "
			   "Deluxe on-board SIMG4726 workaround\n");

		ap->ops = &ahci_p5wdh_ops;
		ap->link.flags |= ATA_LFLAG_NO_SRST | ATA_LFLAG_ASSUME_ATA;
	}
}

2531
static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
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{
	static int printed_version;
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	unsigned int board_id = ent->driver_data;
	struct ata_port_info pi = ahci_port_info[board_id];
2536
	const struct ata_port_info *ppi[] = { &pi, NULL };
2537
	struct device *dev = &pdev->dev;
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	struct ahci_host_priv *hpriv;
2539
	struct ata_host *host;
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	int n_ports, i, rc;
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	VPRINTK("ENTER\n");

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	WARN_ON(ATA_MAX_QUEUE > AHCI_MAX_CMDS);

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	if (!printed_version++)
2547
		dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
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2549 2550 2551 2552 2553 2554
	/* The AHCI driver can only drive the SATA ports, the PATA driver
	   can drive them all so if both drivers are selected make sure
	   AHCI stays out of the way */
	if (pdev->vendor == PCI_VENDOR_ID_MARVELL && !marvell_enable)
		return -ENODEV;

2555
	/* acquire resources */
2556
	rc = pcim_enable_device(pdev);
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	if (rc)
		return rc;

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	/* AHCI controllers often implement SFF compatible interface.
	 * Grab all PCI BARs just in case.
	 */
	rc = pcim_iomap_regions_request_all(pdev, 1 << AHCI_PCI_BAR, DRV_NAME);
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	if (rc == -EBUSY)
2565
		pcim_pin_device(pdev);
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	if (rc)
2567
		return rc;
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2569 2570 2571 2572 2573 2574 2575 2576 2577 2578 2579 2580 2581 2582 2583 2584
	if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
	    (pdev->device == 0x2652 || pdev->device == 0x2653)) {
		u8 map;

		/* ICH6s share the same PCI ID for both piix and ahci
		 * modes.  Enabling ahci mode while MAP indicates
		 * combined mode is a bad idea.  Yield to ata_piix.
		 */
		pci_read_config_byte(pdev, ICH_MAP, &map);
		if (map & 0x3) {
			dev_printk(KERN_INFO, &pdev->dev, "controller is in "
				   "combined mode, can't enable AHCI mode\n");
			return -ENODEV;
		}
	}

2585 2586 2587
	hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
	if (!hpriv)
		return -ENOMEM;
2588 2589
	hpriv->flags |= (unsigned long)pi.private_data;

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	/* MCP65 revision A1 and A2 can't do MSI */
	if (board_id == board_ahci_mcp65 &&
	    (pdev->revision == 0xa1 || pdev->revision == 0xa2))
		hpriv->flags |= AHCI_HFLAG_NO_MSI;

2595 2596
	if ((hpriv->flags & AHCI_HFLAG_NO_MSI) || pci_enable_msi(pdev))
		pci_intx(pdev, 1);
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2598
	/* save initial config */
2599
	ahci_save_initial_config(pdev, hpriv);
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2601
	/* prepare host */
2602
	if (hpriv->cap & HOST_CAP_NCQ)
2603
		pi.flags |= ATA_FLAG_NCQ;
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	if (hpriv->cap & HOST_CAP_PMP)
		pi.flags |= ATA_FLAG_PMP;

2608 2609 2610 2611 2612 2613 2614 2615 2616 2617 2618 2619 2620 2621 2622 2623 2624 2625
	if (ahci_em_messages && (hpriv->cap & HOST_CAP_EMS)) {
		u8 messages;
		void __iomem *mmio = pcim_iomap_table(pdev)[AHCI_PCI_BAR];
		u32 em_loc = readl(mmio + HOST_EM_LOC);
		u32 em_ctl = readl(mmio + HOST_EM_CTL);

		messages = (em_ctl & 0x000f0000) >> 16;

		/* we only support LED message type right now */
		if ((messages & 0x01) && (ahci_em_messages == 1)) {
			/* store em_loc */
			hpriv->em_loc = ((em_loc >> 16) * 4);
			pi.flags |= ATA_FLAG_EM;
			if (!(em_ctl & EM_CTL_ALHD))
				pi.flags |= ATA_FLAG_SW_ACTIVITY;
		}
	}

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	/* CAP.NP sometimes indicate the index of the last enabled
	 * port, at other times, that of the last possible port, so
	 * determining the maximum port number requires looking at
	 * both CAP.NP and port_map.
	 */
	n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map));

	host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
2634 2635 2636 2637 2638
	if (!host)
		return -ENOMEM;
	host->iomap = pcim_iomap_table(pdev);
	host->private_data = hpriv;

2639 2640 2641
	if (pi.flags & ATA_FLAG_EM)
		ahci_reset_em(host);

2642
	for (i = 0; i < host->n_ports; i++) {
2643
		struct ata_port *ap = host->ports[i];
2644

2645 2646 2647 2648
		ata_port_pbar_desc(ap, AHCI_PCI_BAR, -1, "abar");
		ata_port_pbar_desc(ap, AHCI_PCI_BAR,
				   0x100 + ap->port_no * 0x80, "port");

2649 2650 2651
		/* set initial link pm policy */
		ap->pm_policy = NOT_AVAILABLE;

2652 2653 2654 2655 2656
		/* set enclosure management message type */
		if (ap->flags & ATA_FLAG_EM)
			ap->em_message_type = ahci_em_messages;


2657
		/* disabled/not-implemented port */
2658
		if (!(hpriv->port_map & (1 << i)))
2659
			ap->ops = &ata_dummy_port_ops;
2660
	}
2661

2662 2663 2664
	/* apply workaround for ASUS P5W DH Deluxe mainboard */
	ahci_p5wdh_workaround(host);

2665 2666
	/* initialize adapter */
	rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64);
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	if (rc)
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		return rc;
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2670 2671 2672
	rc = ahci_reset_controller(host);
	if (rc)
		return rc;
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2674 2675
	ahci_init_controller(host);
	ahci_print_info(host);
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2677 2678 2679
	pci_set_master(pdev);
	return ata_host_activate(host, pdev->irq, ahci_interrupt, IRQF_SHARED,
				 &ahci_sht);
2680
}
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static int __init ahci_init(void)
{
2684
	return pci_register_driver(&ahci_pci_driver);
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}

static void __exit ahci_exit(void)
{
	pci_unregister_driver(&ahci_pci_driver);
}


MODULE_AUTHOR("Jeff Garzik");
MODULE_DESCRIPTION("AHCI SATA low-level driver");
MODULE_LICENSE("GPL");
MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
2697
MODULE_VERSION(DRV_VERSION);
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module_init(ahci_init);
module_exit(ahci_exit);