ahci.c 62.8 KB
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/*
 *  ahci.c - AHCI SATA support
 *
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 *  Maintained by:  Jeff Garzik <jgarzik@pobox.com>
 *    		    Please ALWAYS copy linux-ide@vger.kernel.org
 *		    on emails.
 *
 *  Copyright 2004-2005 Red Hat, Inc.
 *
 *
 *  This program is free software; you can redistribute it and/or modify
 *  it under the terms of the GNU General Public License as published by
 *  the Free Software Foundation; either version 2, or (at your option)
 *  any later version.
 *
 *  This program is distributed in the hope that it will be useful,
 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *  GNU General Public License for more details.
 *
 *  You should have received a copy of the GNU General Public License
 *  along with this program; see the file COPYING.  If not, write to
 *  the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
 *
 *
 * libata documentation is available via 'make {ps|pdf}docs',
 * as Documentation/DocBook/libata.*
 *
 * AHCI hardware documentation:
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 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
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 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
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 *
 */

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/blkdev.h>
#include <linux/delay.h>
#include <linux/interrupt.h>
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#include <linux/dma-mapping.h>
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#include <linux/device.h>
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#include <linux/dmi.h>
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#include <scsi/scsi_host.h>
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#include <scsi/scsi_cmnd.h>
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#include <linux/libata.h>

#define DRV_NAME	"ahci"
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#define DRV_VERSION	"3.0"
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static int ahci_enable_alpm(struct ata_port *ap,
		enum link_pm policy);
static void ahci_disable_alpm(struct ata_port *ap);
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enum {
	AHCI_PCI_BAR		= 5,
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	AHCI_MAX_PORTS		= 32,
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	AHCI_MAX_SG		= 168, /* hardware max is 64K */
	AHCI_DMA_BOUNDARY	= 0xffffffff,
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	AHCI_USE_CLUSTERING	= 1,
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	AHCI_MAX_CMDS		= 32,
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	AHCI_CMD_SZ		= 32,
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	AHCI_CMD_SLOT_SZ	= AHCI_MAX_CMDS * AHCI_CMD_SZ,
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	AHCI_RX_FIS_SZ		= 256,
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	AHCI_CMD_TBL_CDB	= 0x40,
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	AHCI_CMD_TBL_HDR_SZ	= 0x80,
	AHCI_CMD_TBL_SZ		= AHCI_CMD_TBL_HDR_SZ + (AHCI_MAX_SG * 16),
	AHCI_CMD_TBL_AR_SZ	= AHCI_CMD_TBL_SZ * AHCI_MAX_CMDS,
	AHCI_PORT_PRIV_DMA_SZ	= AHCI_CMD_SLOT_SZ + AHCI_CMD_TBL_AR_SZ +
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				  AHCI_RX_FIS_SZ,
	AHCI_IRQ_ON_SG		= (1 << 31),
	AHCI_CMD_ATAPI		= (1 << 5),
	AHCI_CMD_WRITE		= (1 << 6),
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	AHCI_CMD_PREFETCH	= (1 << 7),
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	AHCI_CMD_RESET		= (1 << 8),
	AHCI_CMD_CLR_BUSY	= (1 << 10),
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	RX_FIS_D2H_REG		= 0x40,	/* offset of D2H Register FIS data */
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	RX_FIS_SDB		= 0x58, /* offset of SDB FIS data */
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	RX_FIS_UNK		= 0x60, /* offset of Unknown FIS data */
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	board_ahci		= 0,
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	board_ahci_vt8251	= 1,
	board_ahci_ign_iferr	= 2,
	board_ahci_sb600	= 3,
	board_ahci_mv		= 4,
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	board_ahci_sb700	= 5,
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	/* global controller registers */
	HOST_CAP		= 0x00, /* host capabilities */
	HOST_CTL		= 0x04, /* global host control */
	HOST_IRQ_STAT		= 0x08, /* interrupt status */
	HOST_PORTS_IMPL		= 0x0c, /* bitmap of implemented ports */
	HOST_VERSION		= 0x10, /* AHCI spec. version compliancy */

	/* HOST_CTL bits */
	HOST_RESET		= (1 << 0),  /* reset controller; self-clear */
	HOST_IRQ_EN		= (1 << 1),  /* global IRQ enable */
	HOST_AHCI_EN		= (1 << 31), /* AHCI enabled */

	/* HOST_CAP bits */
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	HOST_CAP_SSC		= (1 << 14), /* Slumber capable */
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	HOST_CAP_PMP		= (1 << 17), /* Port Multiplier support */
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	HOST_CAP_CLO		= (1 << 24), /* Command List Override support */
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	HOST_CAP_ALPM		= (1 << 26), /* Aggressive Link PM support */
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	HOST_CAP_SSS		= (1 << 27), /* Staggered Spin-up */
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	HOST_CAP_SNTF		= (1 << 29), /* SNotification register */
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	HOST_CAP_NCQ		= (1 << 30), /* Native Command Queueing */
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	HOST_CAP_64		= (1 << 31), /* PCI DAC (64-bit DMA) support */
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	/* registers for each SATA port */
	PORT_LST_ADDR		= 0x00, /* command list DMA addr */
	PORT_LST_ADDR_HI	= 0x04, /* command list DMA addr hi */
	PORT_FIS_ADDR		= 0x08, /* FIS rx buf addr */
	PORT_FIS_ADDR_HI	= 0x0c, /* FIS rx buf addr hi */
	PORT_IRQ_STAT		= 0x10, /* interrupt status */
	PORT_IRQ_MASK		= 0x14, /* interrupt enable/disable mask */
	PORT_CMD		= 0x18, /* port command */
	PORT_TFDATA		= 0x20,	/* taskfile data */
	PORT_SIG		= 0x24,	/* device TF signature */
	PORT_CMD_ISSUE		= 0x38, /* command issue */
	PORT_SCR_STAT		= 0x28, /* SATA phy register: SStatus */
	PORT_SCR_CTL		= 0x2c, /* SATA phy register: SControl */
	PORT_SCR_ERR		= 0x30, /* SATA phy register: SError */
	PORT_SCR_ACT		= 0x34, /* SATA phy register: SActive */
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	PORT_SCR_NTF		= 0x3c, /* SATA phy register: SNotification */
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	/* PORT_IRQ_{STAT,MASK} bits */
	PORT_IRQ_COLD_PRES	= (1 << 31), /* cold presence detect */
	PORT_IRQ_TF_ERR		= (1 << 30), /* task file error */
	PORT_IRQ_HBUS_ERR	= (1 << 29), /* host bus fatal error */
	PORT_IRQ_HBUS_DATA_ERR	= (1 << 28), /* host bus data error */
	PORT_IRQ_IF_ERR		= (1 << 27), /* interface fatal error */
	PORT_IRQ_IF_NONFATAL	= (1 << 26), /* interface non-fatal error */
	PORT_IRQ_OVERFLOW	= (1 << 24), /* xfer exhausted available S/G */
	PORT_IRQ_BAD_PMP	= (1 << 23), /* incorrect port multiplier */

	PORT_IRQ_PHYRDY		= (1 << 22), /* PhyRdy changed */
	PORT_IRQ_DEV_ILCK	= (1 << 7), /* device interlock */
	PORT_IRQ_CONNECT	= (1 << 6), /* port connect change status */
	PORT_IRQ_SG_DONE	= (1 << 5), /* descriptor processed */
	PORT_IRQ_UNK_FIS	= (1 << 4), /* unknown FIS rx'd */
	PORT_IRQ_SDB_FIS	= (1 << 3), /* Set Device Bits FIS rx'd */
	PORT_IRQ_DMAS_FIS	= (1 << 2), /* DMA Setup FIS rx'd */
	PORT_IRQ_PIOS_FIS	= (1 << 1), /* PIO Setup FIS rx'd */
	PORT_IRQ_D2H_REG_FIS	= (1 << 0), /* D2H Register FIS rx'd */

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	PORT_IRQ_FREEZE		= PORT_IRQ_HBUS_ERR |
				  PORT_IRQ_IF_ERR |
				  PORT_IRQ_CONNECT |
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				  PORT_IRQ_PHYRDY |
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				  PORT_IRQ_UNK_FIS |
				  PORT_IRQ_BAD_PMP,
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	PORT_IRQ_ERROR		= PORT_IRQ_FREEZE |
				  PORT_IRQ_TF_ERR |
				  PORT_IRQ_HBUS_DATA_ERR,
	DEF_PORT_IRQ		= PORT_IRQ_ERROR | PORT_IRQ_SG_DONE |
				  PORT_IRQ_SDB_FIS | PORT_IRQ_DMAS_FIS |
				  PORT_IRQ_PIOS_FIS | PORT_IRQ_D2H_REG_FIS,
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	/* PORT_CMD bits */
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	PORT_CMD_ASP		= (1 << 27), /* Aggressive Slumber/Partial */
	PORT_CMD_ALPE		= (1 << 26), /* Aggressive Link PM enable */
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	PORT_CMD_ATAPI		= (1 << 24), /* Device is ATAPI */
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	PORT_CMD_PMP		= (1 << 17), /* PMP attached */
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	PORT_CMD_LIST_ON	= (1 << 15), /* cmd list DMA engine running */
	PORT_CMD_FIS_ON		= (1 << 14), /* FIS DMA engine running */
	PORT_CMD_FIS_RX		= (1 << 4), /* Enable FIS receive DMA engine */
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	PORT_CMD_CLO		= (1 << 3), /* Command list override */
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	PORT_CMD_POWER_ON	= (1 << 2), /* Power up device */
	PORT_CMD_SPIN_UP	= (1 << 1), /* Spin up device */
	PORT_CMD_START		= (1 << 0), /* Enable port DMA engine */

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	PORT_CMD_ICC_MASK	= (0xf << 28), /* i/f ICC state mask */
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	PORT_CMD_ICC_ACTIVE	= (0x1 << 28), /* Put i/f in active state */
	PORT_CMD_ICC_PARTIAL	= (0x2 << 28), /* Put i/f in partial state */
	PORT_CMD_ICC_SLUMBER	= (0x6 << 28), /* Put i/f in slumber state */
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	/* hpriv->flags bits */
	AHCI_HFLAG_NO_NCQ		= (1 << 0),
	AHCI_HFLAG_IGN_IRQ_IF_ERR	= (1 << 1), /* ignore IRQ_IF_ERR */
	AHCI_HFLAG_IGN_SERR_INTERNAL	= (1 << 2), /* ignore SERR_INTERNAL */
	AHCI_HFLAG_32BIT_ONLY		= (1 << 3), /* force 32bit */
	AHCI_HFLAG_MV_PATA		= (1 << 4), /* PATA port */
	AHCI_HFLAG_NO_MSI		= (1 << 5), /* no PCI MSI */
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	AHCI_HFLAG_NO_PMP		= (1 << 6), /* no PMP */
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	AHCI_HFLAG_NO_HOTPLUG		= (1 << 7), /* ignore PxSERR.DIAG.N */
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	/* ap->flags bits */
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	AHCI_FLAG_COMMON		= ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
					  ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA |
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					  ATA_FLAG_ACPI_SATA | ATA_FLAG_AN |
					  ATA_FLAG_IPM,
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	AHCI_LFLAG_COMMON		= ATA_LFLAG_SKIP_D2H_BSY,
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	ICH_MAP				= 0x90, /* ICH MAP register */
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};

struct ahci_cmd_hdr {
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	__le32			opts;
	__le32			status;
	__le32			tbl_addr;
	__le32			tbl_addr_hi;
	__le32			reserved[4];
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};

struct ahci_sg {
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	__le32			addr;
	__le32			addr_hi;
	__le32			reserved;
	__le32			flags_size;
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};

struct ahci_host_priv {
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	unsigned int		flags;		/* AHCI_HFLAG_* */
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	u32			cap;		/* cap to use */
	u32			port_map;	/* port map to use */
	u32			saved_cap;	/* saved initial cap */
	u32			saved_port_map;	/* saved initial port_map */
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};

struct ahci_port_priv {
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	struct ata_link		*active_link;
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	struct ahci_cmd_hdr	*cmd_slot;
	dma_addr_t		cmd_slot_dma;
	void			*cmd_tbl;
	dma_addr_t		cmd_tbl_dma;
	void			*rx_fis;
	dma_addr_t		rx_fis_dma;
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	/* for NCQ spurious interrupt analysis */
	unsigned int		ncq_saw_d2h:1;
	unsigned int		ncq_saw_dmas:1;
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	unsigned int		ncq_saw_sdb:1;
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	u32 			intr_mask;	/* interrupts to enable */
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};

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static int ahci_scr_read(struct ata_port *ap, unsigned int sc_reg, u32 *val);
static int ahci_scr_write(struct ata_port *ap, unsigned int sc_reg, u32 val);
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static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
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static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc);
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static void ahci_irq_clear(struct ata_port *ap);
static int ahci_port_start(struct ata_port *ap);
static void ahci_port_stop(struct ata_port *ap);
static void ahci_tf_read(struct ata_port *ap, struct ata_taskfile *tf);
static void ahci_qc_prep(struct ata_queued_cmd *qc);
static u8 ahci_check_status(struct ata_port *ap);
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static void ahci_freeze(struct ata_port *ap);
static void ahci_thaw(struct ata_port *ap);
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static void ahci_pmp_attach(struct ata_port *ap);
static void ahci_pmp_detach(struct ata_port *ap);
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static void ahci_error_handler(struct ata_port *ap);
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static void ahci_vt8251_error_handler(struct ata_port *ap);
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static void ahci_p5wdh_error_handler(struct ata_port *ap);
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static void ahci_post_internal_cmd(struct ata_queued_cmd *qc);
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static int ahci_port_resume(struct ata_port *ap);
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static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl);
static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,
			       u32 opts);
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#ifdef CONFIG_PM
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static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg);
static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
static int ahci_pci_device_resume(struct pci_dev *pdev);
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#endif
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static struct class_device_attribute *ahci_shost_attrs[] = {
	&class_device_attr_link_power_management_policy,
	NULL
};

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static struct scsi_host_template ahci_sht = {
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	.module			= THIS_MODULE,
	.name			= DRV_NAME,
	.ioctl			= ata_scsi_ioctl,
	.queuecommand		= ata_scsi_queuecmd,
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	.change_queue_depth	= ata_scsi_change_queue_depth,
	.can_queue		= AHCI_MAX_CMDS - 1,
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	.this_id		= ATA_SHT_THIS_ID,
	.sg_tablesize		= AHCI_MAX_SG,
	.cmd_per_lun		= ATA_SHT_CMD_PER_LUN,
	.emulated		= ATA_SHT_EMULATED,
	.use_clustering		= AHCI_USE_CLUSTERING,
	.proc_name		= DRV_NAME,
	.dma_boundary		= AHCI_DMA_BOUNDARY,
	.slave_configure	= ata_scsi_slave_config,
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	.slave_destroy		= ata_scsi_slave_destroy,
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	.bios_param		= ata_std_bios_param,
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	.shost_attrs		= ahci_shost_attrs,
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};

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static const struct ata_port_operations ahci_ops = {
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	.check_status		= ahci_check_status,
	.check_altstatus	= ahci_check_status,
	.dev_select		= ata_noop_dev_select,

	.tf_read		= ahci_tf_read,

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	.qc_defer		= sata_pmp_qc_defer_cmd_switch,
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	.qc_prep		= ahci_qc_prep,
	.qc_issue		= ahci_qc_issue,

	.irq_clear		= ahci_irq_clear,

	.scr_read		= ahci_scr_read,
	.scr_write		= ahci_scr_write,

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	.freeze			= ahci_freeze,
	.thaw			= ahci_thaw,

	.error_handler		= ahci_error_handler,
	.post_internal_cmd	= ahci_post_internal_cmd,

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	.pmp_attach		= ahci_pmp_attach,
	.pmp_detach		= ahci_pmp_detach,

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#ifdef CONFIG_PM
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	.port_suspend		= ahci_port_suspend,
	.port_resume		= ahci_port_resume,
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#endif
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	.enable_pm		= ahci_enable_alpm,
	.disable_pm		= ahci_disable_alpm,
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	.port_start		= ahci_port_start,
	.port_stop		= ahci_port_stop,
};

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static const struct ata_port_operations ahci_vt8251_ops = {
	.check_status		= ahci_check_status,
	.check_altstatus	= ahci_check_status,
	.dev_select		= ata_noop_dev_select,

	.tf_read		= ahci_tf_read,

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	.qc_defer		= sata_pmp_qc_defer_cmd_switch,
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	.qc_prep		= ahci_qc_prep,
	.qc_issue		= ahci_qc_issue,

	.irq_clear		= ahci_irq_clear,

	.scr_read		= ahci_scr_read,
	.scr_write		= ahci_scr_write,

	.freeze			= ahci_freeze,
	.thaw			= ahci_thaw,

	.error_handler		= ahci_vt8251_error_handler,
	.post_internal_cmd	= ahci_post_internal_cmd,

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	.pmp_attach		= ahci_pmp_attach,
	.pmp_detach		= ahci_pmp_detach,

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#ifdef CONFIG_PM
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	.port_suspend		= ahci_port_suspend,
	.port_resume		= ahci_port_resume,
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#endif
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	.port_start		= ahci_port_start,
	.port_stop		= ahci_port_stop,
};

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static const struct ata_port_operations ahci_p5wdh_ops = {
	.check_status		= ahci_check_status,
	.check_altstatus	= ahci_check_status,
	.dev_select		= ata_noop_dev_select,

	.tf_read		= ahci_tf_read,

	.qc_defer		= sata_pmp_qc_defer_cmd_switch,
	.qc_prep		= ahci_qc_prep,
	.qc_issue		= ahci_qc_issue,

	.irq_clear		= ahci_irq_clear,

	.scr_read		= ahci_scr_read,
	.scr_write		= ahci_scr_write,

	.freeze			= ahci_freeze,
	.thaw			= ahci_thaw,

	.error_handler		= ahci_p5wdh_error_handler,
	.post_internal_cmd	= ahci_post_internal_cmd,

	.pmp_attach		= ahci_pmp_attach,
	.pmp_detach		= ahci_pmp_detach,

#ifdef CONFIG_PM
	.port_suspend		= ahci_port_suspend,
	.port_resume		= ahci_port_resume,
#endif

	.port_start		= ahci_port_start,
	.port_stop		= ahci_port_stop,
};

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#define AHCI_HFLAGS(flags)	.private_data	= (void *)(flags)

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static const struct ata_port_info ahci_port_info[] = {
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	/* board_ahci */
	{
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		.flags		= AHCI_FLAG_COMMON,
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		.link_flags	= AHCI_LFLAG_COMMON,
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		.pio_mask	= 0x1f, /* pio0-4 */
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		.udma_mask	= ATA_UDMA6,
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		.port_ops	= &ahci_ops,
	},
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	/* board_ahci_vt8251 */
	{
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		AHCI_HFLAGS	(AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_PMP),
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		.flags		= AHCI_FLAG_COMMON,
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		.link_flags	= AHCI_LFLAG_COMMON | ATA_LFLAG_HRST_TO_RESUME,
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		.pio_mask	= 0x1f, /* pio0-4 */
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		.udma_mask	= ATA_UDMA6,
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		.port_ops	= &ahci_vt8251_ops,
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	},
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	/* board_ahci_ign_iferr */
	{
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		AHCI_HFLAGS	(AHCI_HFLAG_IGN_IRQ_IF_ERR),
		.flags		= AHCI_FLAG_COMMON,
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		.link_flags	= AHCI_LFLAG_COMMON,
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		.pio_mask	= 0x1f, /* pio0-4 */
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		.udma_mask	= ATA_UDMA6,
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		.port_ops	= &ahci_ops,
	},
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	/* board_ahci_sb600 */
	{
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		AHCI_HFLAGS	(AHCI_HFLAG_IGN_SERR_INTERNAL |
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				 AHCI_HFLAG_32BIT_ONLY | AHCI_HFLAG_NO_PMP),
429
		.flags		= AHCI_FLAG_COMMON,
430
		.link_flags	= AHCI_LFLAG_COMMON,
431
		.pio_mask	= 0x1f, /* pio0-4 */
432
		.udma_mask	= ATA_UDMA6,
433 434
		.port_ops	= &ahci_ops,
	},
435 436
	/* board_ahci_mv */
	{
437 438
		AHCI_HFLAGS	(AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI |
				 AHCI_HFLAG_MV_PATA),
439
		.flags		= ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
440
				  ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA,
441
		.link_flags	= AHCI_LFLAG_COMMON,
442 443 444 445
		.pio_mask	= 0x1f, /* pio0-4 */
		.udma_mask	= ATA_UDMA6,
		.port_ops	= &ahci_ops,
	},
446 447 448 449 450 451 452 453 454 455
	/* board_ahci_sb700 */
	{
		AHCI_HFLAGS	(AHCI_HFLAG_IGN_SERR_INTERNAL |
				 AHCI_HFLAG_NO_PMP),
		.flags		= AHCI_FLAG_COMMON,
		.link_flags	= AHCI_LFLAG_COMMON,
		.pio_mask	= 0x1f, /* pio0-4 */
		.udma_mask	= ATA_UDMA6,
		.port_ops	= &ahci_ops,
	},
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};

458
static const struct pci_device_id ahci_pci_tbl[] = {
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	/* Intel */
460 461 462 463 464
	{ PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */
	{ PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */
	{ PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */
	{ PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */
	{ PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */
465
	{ PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */
466 467 468 469
	{ PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */
	{ PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */
	{ PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */
	{ PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */
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	{ PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */
	{ PCI_VDEVICE(INTEL, 0x2822), board_ahci }, /* ICH8 */
	{ PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */
	{ PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */
	{ PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */
	{ PCI_VDEVICE(INTEL, 0x2922), board_ahci }, /* ICH9 */
	{ PCI_VDEVICE(INTEL, 0x2923), board_ahci }, /* ICH9 */
	{ PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */
	{ PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */
	{ PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */
	{ PCI_VDEVICE(INTEL, 0x2929), board_ahci }, /* ICH9M */
	{ PCI_VDEVICE(INTEL, 0x292a), board_ahci }, /* ICH9M */
	{ PCI_VDEVICE(INTEL, 0x292b), board_ahci }, /* ICH9M */
	{ PCI_VDEVICE(INTEL, 0x292c), board_ahci }, /* ICH9M */
	{ PCI_VDEVICE(INTEL, 0x292f), board_ahci }, /* ICH9M */
	{ PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */
	{ PCI_VDEVICE(INTEL, 0x294e), board_ahci }, /* ICH9M */
487 488
	{ PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */
	{ PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */
489 490
	{ PCI_VDEVICE(INTEL, 0x3a05), board_ahci }, /* ICH10 */
	{ PCI_VDEVICE(INTEL, 0x3a25), board_ahci }, /* ICH10 */
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492 493 494
	/* JMicron 360/1/3/5/6, match class to avoid IDE function */
	{ PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
	  PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr },
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	/* ATI */
497
	{ PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */
498 499 500 501 502 503
	{ PCI_VDEVICE(ATI, 0x4390), board_ahci_sb700 }, /* ATI SB700/800 */
	{ PCI_VDEVICE(ATI, 0x4391), board_ahci_sb700 }, /* ATI SB700/800 */
	{ PCI_VDEVICE(ATI, 0x4392), board_ahci_sb700 }, /* ATI SB700/800 */
	{ PCI_VDEVICE(ATI, 0x4393), board_ahci_sb700 }, /* ATI SB700/800 */
	{ PCI_VDEVICE(ATI, 0x4394), board_ahci_sb700 }, /* ATI SB700/800 */
	{ PCI_VDEVICE(ATI, 0x4395), board_ahci_sb700 }, /* ATI SB700/800 */
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	/* VIA */
506
	{ PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */
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	{ PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */
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	/* NVIDIA */
510 511 512 513
	{ PCI_VDEVICE(NVIDIA, 0x044c), board_ahci },		/* MCP65 */
	{ PCI_VDEVICE(NVIDIA, 0x044d), board_ahci },		/* MCP65 */
	{ PCI_VDEVICE(NVIDIA, 0x044e), board_ahci },		/* MCP65 */
	{ PCI_VDEVICE(NVIDIA, 0x044f), board_ahci },		/* MCP65 */
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	{ PCI_VDEVICE(NVIDIA, 0x045c), board_ahci },		/* MCP65 */
	{ PCI_VDEVICE(NVIDIA, 0x045d), board_ahci },		/* MCP65 */
	{ PCI_VDEVICE(NVIDIA, 0x045e), board_ahci },		/* MCP65 */
	{ PCI_VDEVICE(NVIDIA, 0x045f), board_ahci },		/* MCP65 */
	{ PCI_VDEVICE(NVIDIA, 0x0550), board_ahci },		/* MCP67 */
	{ PCI_VDEVICE(NVIDIA, 0x0551), board_ahci },		/* MCP67 */
	{ PCI_VDEVICE(NVIDIA, 0x0552), board_ahci },		/* MCP67 */
	{ PCI_VDEVICE(NVIDIA, 0x0553), board_ahci },		/* MCP67 */
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	{ PCI_VDEVICE(NVIDIA, 0x0554), board_ahci },		/* MCP67 */
	{ PCI_VDEVICE(NVIDIA, 0x0555), board_ahci },		/* MCP67 */
	{ PCI_VDEVICE(NVIDIA, 0x0556), board_ahci },		/* MCP67 */
	{ PCI_VDEVICE(NVIDIA, 0x0557), board_ahci },		/* MCP67 */
	{ PCI_VDEVICE(NVIDIA, 0x0558), board_ahci },		/* MCP67 */
	{ PCI_VDEVICE(NVIDIA, 0x0559), board_ahci },		/* MCP67 */
	{ PCI_VDEVICE(NVIDIA, 0x055a), board_ahci },		/* MCP67 */
	{ PCI_VDEVICE(NVIDIA, 0x055b), board_ahci },		/* MCP67 */
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	{ PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci },		/* MCP73 */
	{ PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci },		/* MCP73 */
	{ PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci },		/* MCP73 */
	{ PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci },		/* MCP73 */
	{ PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci },		/* MCP73 */
	{ PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci },		/* MCP73 */
	{ PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci },		/* MCP73 */
	{ PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci },		/* MCP73 */
	{ PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci },		/* MCP73 */
	{ PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci },		/* MCP73 */
	{ PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci },		/* MCP73 */
	{ PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci },		/* MCP73 */
	{ PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci },		/* MCP77 */
	{ PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci },		/* MCP77 */
	{ PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci },		/* MCP77 */
	{ PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci },		/* MCP77 */
	{ PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci },		/* MCP77 */
	{ PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci },		/* MCP77 */
	{ PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci },		/* MCP77 */
	{ PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci },		/* MCP77 */
	{ PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci },		/* MCP77 */
	{ PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci },		/* MCP77 */
	{ PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci },		/* MCP77 */
	{ PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci },		/* MCP77 */
554 555 556 557
	{ PCI_VDEVICE(NVIDIA, 0x0ab4), board_ahci },		/* MCP79 */
	{ PCI_VDEVICE(NVIDIA, 0x0ab5), board_ahci },		/* MCP79 */
	{ PCI_VDEVICE(NVIDIA, 0x0ab6), board_ahci },		/* MCP79 */
	{ PCI_VDEVICE(NVIDIA, 0x0ab7), board_ahci },		/* MCP79 */
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	{ PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci },		/* MCP79 */
	{ PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci },		/* MCP79 */
	{ PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci },		/* MCP79 */
	{ PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci },		/* MCP79 */
	{ PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci },		/* MCP79 */
	{ PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci },		/* MCP79 */
	{ PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci },		/* MCP79 */
	{ PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci },		/* MCP79 */
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	/* SiS */
568 569 570
	{ PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */
	{ PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 966 */
	{ PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */
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572 573 574
	/* Marvell */
	{ PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv },	/* 6145 */

575 576
	/* Generic, PCI class code for AHCI */
	{ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
577
	  PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci },
578

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	{ }	/* terminate list */
};


static struct pci_driver ahci_pci_driver = {
	.name			= DRV_NAME,
	.id_table		= ahci_pci_tbl,
	.probe			= ahci_init_one,
587
	.remove			= ata_pci_remove_one,
588
#ifdef CONFIG_PM
589 590
	.suspend		= ahci_pci_device_suspend,
	.resume			= ahci_pci_device_resume,
591
#endif
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};


595 596 597 598 599
static inline int ahci_nr_ports(u32 cap)
{
	return (cap & 0x1f) + 1;
}

600 601
static inline void __iomem *__ahci_port_base(struct ata_host *host,
					     unsigned int port_no)
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{
603
	void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
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605 606 607 608 609 610
	return mmio + 0x100 + (port_no * 0x80);
}

static inline void __iomem *ahci_port_base(struct ata_port *ap)
{
	return __ahci_port_base(ap->host, ap->port_no);
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}

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static void ahci_enable_ahci(void __iomem *mmio)
{
	u32 tmp;

	/* turn on AHCI_EN */
	tmp = readl(mmio + HOST_CTL);
	if (!(tmp & HOST_AHCI_EN)) {
		tmp |= HOST_AHCI_EN;
		writel(tmp, mmio + HOST_CTL);
		tmp = readl(mmio + HOST_CTL);	/* flush && sanity check */
		WARN_ON(!(tmp & HOST_AHCI_EN));
	}
}

627 628
/**
 *	ahci_save_initial_config - Save and fixup initial config values
629 630
 *	@pdev: target PCI device
 *	@hpriv: host private area to store config values
631 632 633 634 635 636 637 638 639 640 641
 *
 *	Some registers containing configuration info might be setup by
 *	BIOS and might be cleared on reset.  This function saves the
 *	initial values of those registers into @hpriv such that they
 *	can be restored after controller reset.
 *
 *	If inconsistent, config values are fixed up by this function.
 *
 *	LOCKING:
 *	None.
 */
642 643
static void ahci_save_initial_config(struct pci_dev *pdev,
				     struct ahci_host_priv *hpriv)
644
{
645
	void __iomem *mmio = pcim_iomap_table(pdev)[AHCI_PCI_BAR];
646
	u32 cap, port_map;
647
	int i;
648

649 650 651
	/* make sure AHCI mode is enabled before accessing CAP */
	ahci_enable_ahci(mmio);

652 653 654 655 656 657
	/* Values prefixed with saved_ are written back to host after
	 * reset.  Values without are used for driver operation.
	 */
	hpriv->saved_cap = cap = readl(mmio + HOST_CAP);
	hpriv->saved_port_map = port_map = readl(mmio + HOST_PORTS_IMPL);

658
	/* some chips have errata preventing 64bit use */
659
	if ((cap & HOST_CAP_64) && (hpriv->flags & AHCI_HFLAG_32BIT_ONLY)) {
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		dev_printk(KERN_INFO, &pdev->dev,
			   "controller can't do 64bit DMA, forcing 32bit\n");
		cap &= ~HOST_CAP_64;
	}

665
	if ((cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_NO_NCQ)) {
666 667 668 669 670
		dev_printk(KERN_INFO, &pdev->dev,
			   "controller can't do NCQ, turning off CAP_NCQ\n");
		cap &= ~HOST_CAP_NCQ;
	}

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	if ((cap && HOST_CAP_PMP) && (hpriv->flags & AHCI_HFLAG_NO_PMP)) {
		dev_printk(KERN_INFO, &pdev->dev,
			   "controller can't do PMP, turning off CAP_PMP\n");
		cap &= ~HOST_CAP_PMP;
	}

677 678 679 680 681
	/*
	 * Temporary Marvell 6145 hack: PATA port presence
	 * is asserted through the standard AHCI port
	 * presence register, as bit 4 (counting from 0)
	 */
682
	if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
683 684 685 686 687 688 689 690
		dev_printk(KERN_ERR, &pdev->dev,
			   "MV_AHCI HACK: port_map %x -> %x\n",
			   hpriv->port_map,
			   hpriv->port_map & 0xf);

		port_map &= 0xf;
	}

691
	/* cross check port_map and cap.n_ports */
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	if (port_map) {
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		int map_ports = 0;
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		for (i = 0; i < AHCI_MAX_PORTS; i++)
			if (port_map & (1 << i))
				map_ports++;
698

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		/* If PI has more ports than n_ports, whine, clear
		 * port_map and let it be generated from n_ports.
701
		 */
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		if (map_ports > ahci_nr_ports(cap)) {
703
			dev_printk(KERN_WARNING, &pdev->dev,
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				   "implemented port map (0x%x) contains more "
				   "ports than nr_ports (%u), using nr_ports\n",
				   port_map, ahci_nr_ports(cap));
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			port_map = 0;
		}
	}

	/* fabricate port_map from cap.nr_ports */
	if (!port_map) {
713
		port_map = (1 << ahci_nr_ports(cap)) - 1;
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		dev_printk(KERN_WARNING, &pdev->dev,
			   "forcing PORTS_IMPL to 0x%x\n", port_map);

		/* write the fixed up value to the PI register */
		hpriv->saved_port_map = port_map;
719 720
	}

721 722 723 724 725 726 727
	/* record values to use during operation */
	hpriv->cap = cap;
	hpriv->port_map = port_map;
}

/**
 *	ahci_restore_initial_config - Restore initial config
728
 *	@host: target ATA host
729 730 731 732 733 734
 *
 *	Restore initial config stored by ahci_save_initial_config().
 *
 *	LOCKING:
 *	None.
 */
735
static void ahci_restore_initial_config(struct ata_host *host)
736
{
737 738 739
	struct ahci_host_priv *hpriv = host->private_data;
	void __iomem *mmio = host->iomap[AHCI_PCI_BAR];

740 741 742 743 744
	writel(hpriv->saved_cap, mmio + HOST_CAP);
	writel(hpriv->saved_port_map, mmio + HOST_PORTS_IMPL);
	(void) readl(mmio + HOST_PORTS_IMPL);	/* flush */
}

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static unsigned ahci_scr_offset(struct ata_port *ap, unsigned int sc_reg)
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{
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	static const int offset[] = {
		[SCR_STATUS]		= PORT_SCR_STAT,
		[SCR_CONTROL]		= PORT_SCR_CTL,
		[SCR_ERROR]		= PORT_SCR_ERR,
		[SCR_ACTIVE]		= PORT_SCR_ACT,
		[SCR_NOTIFICATION]	= PORT_SCR_NTF,
	};
	struct ahci_host_priv *hpriv = ap->host->private_data;
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	if (sc_reg < ARRAY_SIZE(offset) &&
	    (sc_reg != SCR_NOTIFICATION || (hpriv->cap & HOST_CAP_SNTF)))
		return offset[sc_reg];
759
	return 0;
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}

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static int ahci_scr_read(struct ata_port *ap, unsigned int sc_reg, u32 *val)
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{
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	void __iomem *port_mmio = ahci_port_base(ap);
	int offset = ahci_scr_offset(ap, sc_reg);

	if (offset) {
		*val = readl(port_mmio + offset);
		return 0;
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	}
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	return -EINVAL;
}
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static int ahci_scr_write(struct ata_port *ap, unsigned int sc_reg, u32 val)
{
	void __iomem *port_mmio = ahci_port_base(ap);
	int offset = ahci_scr_offset(ap, sc_reg);

	if (offset) {
		writel(val, port_mmio + offset);
		return 0;
	}
	return -EINVAL;
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}

786
static void ahci_start_engine(struct ata_port *ap)
787
{
788
	void __iomem *port_mmio = ahci_port_base(ap);
789 790
	u32 tmp;

791
	/* start DMA */
792
	tmp = readl(port_mmio + PORT_CMD);
793 794 795 796 797
	tmp |= PORT_CMD_START;
	writel(tmp, port_mmio + PORT_CMD);
	readl(port_mmio + PORT_CMD); /* flush */
}

798
static int ahci_stop_engine(struct ata_port *ap)
799
{
800
	void __iomem *port_mmio = ahci_port_base(ap);
801 802 803 804
	u32 tmp;

	tmp = readl(port_mmio + PORT_CMD);

805
	/* check if the HBA is idle */
806 807 808
	if ((tmp & (PORT_CMD_START | PORT_CMD_LIST_ON)) == 0)
		return 0;

809
	/* setting HBA to idle */
810 811 812
	tmp &= ~PORT_CMD_START;
	writel(tmp, port_mmio + PORT_CMD);

813
	/* wait for engine to stop. This could be as long as 500 msec */
814
	tmp = ata_wait_register(port_mmio + PORT_CMD,
815
				PORT_CMD_LIST_ON, PORT_CMD_LIST_ON, 1, 500);
816
	if (tmp & PORT_CMD_LIST_ON)
817 818 819 820 821
		return -EIO;

	return 0;
}

822
static void ahci_start_fis_rx(struct ata_port *ap)
823
{
824 825 826
	void __iomem *port_mmio = ahci_port_base(ap);
	struct ahci_host_priv *hpriv = ap->host->private_data;
	struct ahci_port_priv *pp = ap->private_data;
827 828 829
	u32 tmp;

	/* set FIS registers */
830 831 832 833
	if (hpriv->cap & HOST_CAP_64)
		writel((pp->cmd_slot_dma >> 16) >> 16,
		       port_mmio + PORT_LST_ADDR_HI);
	writel(pp->cmd_slot_dma & 0xffffffff, port_mmio + PORT_LST_ADDR);
834

835 836 837 838
	if (hpriv->cap & HOST_CAP_64)
		writel((pp->rx_fis_dma >> 16) >> 16,
		       port_mmio + PORT_FIS_ADDR_HI);
	writel(pp->rx_fis_dma & 0xffffffff, port_mmio + PORT_FIS_ADDR);
839 840 841 842 843 844 845 846 847 848

	/* enable FIS reception */
	tmp = readl(port_mmio + PORT_CMD);
	tmp |= PORT_CMD_FIS_RX;
	writel(tmp, port_mmio + PORT_CMD);

	/* flush */
	readl(port_mmio + PORT_CMD);
}

849
static int ahci_stop_fis_rx(struct ata_port *ap)
850
{
851
	void __iomem *port_mmio = ahci_port_base(ap);
852 853 854 855 856 857 858 859 860 861 862 863 864 865 866 867
	u32 tmp;

	/* disable FIS reception */
	tmp = readl(port_mmio + PORT_CMD);
	tmp &= ~PORT_CMD_FIS_RX;
	writel(tmp, port_mmio + PORT_CMD);

	/* wait for completion, spec says 500ms, give it 1000 */
	tmp = ata_wait_register(port_mmio + PORT_CMD, PORT_CMD_FIS_ON,
				PORT_CMD_FIS_ON, 10, 1000);
	if (tmp & PORT_CMD_FIS_ON)
		return -EBUSY;

	return 0;
}

868
static void ahci_power_up(struct ata_port *ap)
869
{
870 871
	struct ahci_host_priv *hpriv = ap->host->private_data;
	void __iomem *port_mmio = ahci_port_base(ap);
872 873 874 875 876
	u32 cmd;

	cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;

	/* spin up device */
877
	if (hpriv->cap & HOST_CAP_SSS) {
878 879 880 881 882 883 884 885
		cmd |= PORT_CMD_SPIN_UP;
		writel(cmd, port_mmio + PORT_CMD);
	}

	/* wake up link */
	writel(cmd | PORT_CMD_ICC_ACTIVE, port_mmio + PORT_CMD);
}

886 887 888 889 890 891 892 893 894 895 896 897 898 899 900 901 902 903 904 905 906 907 908 909 910 911 912 913 914 915 916 917 918 919 920 921 922 923 924 925 926 927 928 929 930 931 932 933 934 935 936 937 938 939 940 941 942 943 944 945 946 947 948 949 950 951 952 953 954 955 956 957 958 959 960 961 962 963 964 965 966 967 968 969 970 971 972 973 974 975 976 977 978 979 980 981 982 983 984 985 986 987 988 989 990 991 992 993 994 995 996 997 998 999 1000 1001 1002 1003 1004 1005 1006 1007 1008 1009
static void ahci_disable_alpm(struct ata_port *ap)
{
	struct ahci_host_priv *hpriv = ap->host->private_data;
	void __iomem *port_mmio = ahci_port_base(ap);
	u32 cmd;
	struct ahci_port_priv *pp = ap->private_data;

	/* IPM bits should be disabled by libata-core */
	/* get the existing command bits */
	cmd = readl(port_mmio + PORT_CMD);

	/* disable ALPM and ASP */
	cmd &= ~PORT_CMD_ASP;
	cmd &= ~PORT_CMD_ALPE;

	/* force the interface back to active */
	cmd |= PORT_CMD_ICC_ACTIVE;

	/* write out new cmd value */
	writel(cmd, port_mmio + PORT_CMD);
	cmd = readl(port_mmio + PORT_CMD);

	/* wait 10ms to be sure we've come out of any low power state */
	msleep(10);

	/* clear out any PhyRdy stuff from interrupt status */
	writel(PORT_IRQ_PHYRDY, port_mmio + PORT_IRQ_STAT);

	/* go ahead and clean out PhyRdy Change from Serror too */
	ahci_scr_write(ap, SCR_ERROR, ((1 << 16) | (1 << 18)));

	/*
 	 * Clear flag to indicate that we should ignore all PhyRdy
 	 * state changes
 	 */
	hpriv->flags &= ~AHCI_HFLAG_NO_HOTPLUG;

	/*
 	 * Enable interrupts on Phy Ready.
 	 */
	pp->intr_mask |= PORT_IRQ_PHYRDY;
	writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);

	/*
 	 * don't change the link pm policy - we can be called
 	 * just to turn of link pm temporarily
 	 */
}

static int ahci_enable_alpm(struct ata_port *ap,
	enum link_pm policy)
{
	struct ahci_host_priv *hpriv = ap->host->private_data;
	void __iomem *port_mmio = ahci_port_base(ap);
	u32 cmd;
	struct ahci_port_priv *pp = ap->private_data;
	u32 asp;

	/* Make sure the host is capable of link power management */
	if (!(hpriv->cap & HOST_CAP_ALPM))
		return -EINVAL;

	switch (policy) {
	case MAX_PERFORMANCE:
	case NOT_AVAILABLE:
		/*
 		 * if we came here with NOT_AVAILABLE,
 		 * it just means this is the first time we
 		 * have tried to enable - default to max performance,
 		 * and let the user go to lower power modes on request.
 		 */
		ahci_disable_alpm(ap);
		return 0;
	case MIN_POWER:
		/* configure HBA to enter SLUMBER */
		asp = PORT_CMD_ASP;
		break;
	case MEDIUM_POWER:
		/* configure HBA to enter PARTIAL */
		asp = 0;
		break;
	default:
		return -EINVAL;
	}

	/*
 	 * Disable interrupts on Phy Ready. This keeps us from
 	 * getting woken up due to spurious phy ready interrupts
	 * TBD - Hot plug should be done via polling now, is
	 * that even supported?
 	 */
	pp->intr_mask &= ~PORT_IRQ_PHYRDY;
	writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);

	/*
 	 * Set a flag to indicate that we should ignore all PhyRdy
 	 * state changes since these can happen now whenever we
 	 * change link state
 	 */
	hpriv->flags |= AHCI_HFLAG_NO_HOTPLUG;

	/* get the existing command bits */
	cmd = readl(port_mmio + PORT_CMD);

	/*
 	 * Set ASP based on Policy
 	 */
	cmd |= asp;

	/*
 	 * Setting this bit will instruct the HBA to aggressively
 	 * enter a lower power link state when it's appropriate and
 	 * based on the value set above for ASP
 	 */
	cmd |= PORT_CMD_ALPE;

	/* write out new cmd value */
	writel(cmd, port_mmio + PORT_CMD);
	cmd = readl(port_mmio + PORT_CMD);

	/* IPM bits should be set by libata-core */
	return 0;
}

1010
#ifdef CONFIG_PM
1011
static void ahci_power_down(struct ata_port *ap)
1012
{
1013 1014
	struct ahci_host_priv *hpriv = ap->host->private_data;
	void __iomem *port_mmio = ahci_port_base(ap);
1015 1016
	u32 cmd, scontrol;

1017
	if (!(hpriv->cap & HOST_CAP_SSS))
1018
		return;
1019

1020 1021 1022 1023
	/* put device into listen mode, first set PxSCTL.DET to 0 */
	scontrol = readl(port_mmio + PORT_SCR_CTL);
	scontrol &= ~0xf;
	writel(scontrol, port_mmio + PORT_SCR_CTL);
1024

1025 1026 1027 1028
	/* then set PxCMD.SUD to 0 */
	cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
	cmd &= ~PORT_CMD_SPIN_UP;
	writel(cmd, port_mmio + PORT_CMD);
1029
}
1030
#endif
1031

1032
static void ahci_start_port(struct ata_port *ap)
1033 1034
{
	/* enable FIS reception */
1035
	ahci_start_fis_rx(ap);
1036 1037

	/* enable DMA */
1038
	ahci_start_engine(ap);
1039 1040
}

1041
static int ahci_deinit_port(struct ata_port *ap, const char **emsg)
1042 1043 1044 1045
{
	int rc;

	/* disable DMA */
1046
	rc = ahci_stop_engine(ap);
1047 1048 1049 1050 1051 1052
	if (rc) {
		*emsg = "failed to stop engine";
		return rc;
	}

	/* disable FIS reception */
1053
	rc = ahci_stop_fis_rx(ap);
1054 1055 1056 1057 1058 1059 1060 1061
	if (rc) {
		*emsg = "failed stop FIS RX";
		return rc;
	}

	return 0;
}

1062
static int ahci_reset_controller(struct ata_host *host)
1063
{
1064
	struct pci_dev *pdev = to_pci_dev(host->dev);
T
Tejun Heo 已提交
1065
	struct ahci_host_priv *hpriv = host->private_data;
1066
	void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
1067
	u32 tmp;
1068

1069 1070 1071
	/* we must be in AHCI mode, before using anything
	 * AHCI-specific, such as HOST_RESET.
	 */
1072
	ahci_enable_ahci(mmio);
1073 1074

	/* global controller reset */
1075
	tmp = readl(mmio + HOST_CTL);
1076 1077 1078 1079 1080 1081 1082 1083 1084 1085 1086 1087
	if ((tmp & HOST_RESET) == 0) {
		writel(tmp | HOST_RESET, mmio + HOST_CTL);
		readl(mmio + HOST_CTL); /* flush */
	}

	/* reset must complete within 1 second, or
	 * the hardware should be considered fried.
	 */
	ssleep(1);

	tmp = readl(mmio + HOST_CTL);
	if (tmp & HOST_RESET) {
1088
		dev_printk(KERN_ERR, host->dev,
1089 1090 1091 1092
			   "controller reset failed (0x%x)\n", tmp);
		return -EIO;
	}

1093
	/* turn on AHCI mode */
1094
	ahci_enable_ahci(mmio);
1095

1096
	/* some registers might be cleared on reset.  restore initial values */
1097
	ahci_restore_initial_config(host);
1098 1099 1100 1101 1102 1103

	if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
		u16 tmp16;

		/* configure PCS */
		pci_read_config_word(pdev, 0x92, &tmp16);
T
Tejun Heo 已提交
1104 1105 1106 1107
		if ((tmp16 & hpriv->port_map) != hpriv->port_map) {
			tmp16 |= hpriv->port_map;
			pci_write_config_word(pdev, 0x92, tmp16);
		}
1108 1109 1110 1111 1112
	}

	return 0;
}

1113 1114 1115 1116 1117 1118 1119 1120 1121 1122 1123 1124 1125 1126 1127 1128 1129 1130 1131 1132 1133 1134 1135 1136 1137 1138 1139 1140
static void ahci_port_init(struct pci_dev *pdev, struct ata_port *ap,
			   int port_no, void __iomem *mmio,
			   void __iomem *port_mmio)
{
	const char *emsg = NULL;
	int rc;
	u32 tmp;

	/* make sure port is not active */
	rc = ahci_deinit_port(ap, &emsg);
	if (rc)
		dev_printk(KERN_WARNING, &pdev->dev,
			   "%s (%d)\n", emsg, rc);

	/* clear SError */
	tmp = readl(port_mmio + PORT_SCR_ERR);
	VPRINTK("PORT_SCR_ERR 0x%x\n", tmp);
	writel(tmp, port_mmio + PORT_SCR_ERR);

	/* clear port IRQ */
	tmp = readl(port_mmio + PORT_IRQ_STAT);
	VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
	if (tmp)
		writel(tmp, port_mmio + PORT_IRQ_STAT);

	writel(1 << port_no, mmio + HOST_IRQ_STAT);
}

1141
static void ahci_init_controller(struct ata_host *host)
1142
{
1143
	struct ahci_host_priv *hpriv = host->private_data;
1144 1145
	struct pci_dev *pdev = to_pci_dev(host->dev);
	void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
1146
	int i;
1147
	void __iomem *port_mmio;
1148 1149
	u32 tmp;

1150
	if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
1151 1152 1153 1154 1155 1156 1157 1158 1159 1160 1161
		port_mmio = __ahci_port_base(host, 4);

		writel(0, port_mmio + PORT_IRQ_MASK);

		/* clear port IRQ */
		tmp = readl(port_mmio + PORT_IRQ_STAT);
		VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
		if (tmp)
			writel(tmp, port_mmio + PORT_IRQ_STAT);
	}

1162 1163
	for (i = 0; i < host->n_ports; i++) {
		struct ata_port *ap = host->ports[i];
1164

1165
		port_mmio = ahci_port_base(ap);
1166
		if (ata_port_is_dummy(ap))
1167 1168
			continue;

1169
		ahci_port_init(pdev, ap, i, mmio, port_mmio);
1170 1171 1172 1173 1174 1175 1176 1177 1178
	}

	tmp = readl(mmio + HOST_CTL);
	VPRINTK("HOST_CTL 0x%x\n", tmp);
	writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL);
	tmp = readl(mmio + HOST_CTL);
	VPRINTK("HOST_CTL 0x%x\n", tmp);
}

1179
static unsigned int ahci_dev_classify(struct ata_port *ap)
L
Linus Torvalds 已提交
1180
{
1181
	void __iomem *port_mmio = ahci_port_base(ap);
L
Linus Torvalds 已提交
1182
	struct ata_taskfile tf;
1183 1184 1185 1186 1187 1188 1189 1190 1191 1192 1193
	u32 tmp;

	tmp = readl(port_mmio + PORT_SIG);
	tf.lbah		= (tmp >> 24)	& 0xff;
	tf.lbam		= (tmp >> 16)	& 0xff;
	tf.lbal		= (tmp >> 8)	& 0xff;
	tf.nsect	= (tmp)		& 0xff;

	return ata_dev_classify(&tf);
}

T
Tejun Heo 已提交
1194 1195
static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,
			       u32 opts)
1196
{
T
Tejun Heo 已提交
1197 1198 1199 1200 1201 1202 1203 1204
	dma_addr_t cmd_tbl_dma;

	cmd_tbl_dma = pp->cmd_tbl_dma + tag * AHCI_CMD_TBL_SZ;

	pp->cmd_slot[tag].opts = cpu_to_le32(opts);
	pp->cmd_slot[tag].status = 0;
	pp->cmd_slot[tag].tbl_addr = cpu_to_le32(cmd_tbl_dma & 0xffffffff);
	pp->cmd_slot[tag].tbl_addr_hi = cpu_to_le32((cmd_tbl_dma >> 16) >> 16);
1205 1206
}

1207
static int ahci_kick_engine(struct ata_port *ap, int force_restart)
T
Tejun Heo 已提交
1208
{
T
Tejun Heo 已提交
1209
	void __iomem *port_mmio = ap->ioaddr.cmd_addr;
J
Jeff Garzik 已提交
1210
	struct ahci_host_priv *hpriv = ap->host->private_data;
1211
	u32 tmp;
1212
	int busy, rc;
1213

1214 1215 1216 1217 1218 1219 1220 1221 1222 1223 1224 1225 1226 1227 1228 1229 1230 1231 1232 1233
	/* do we need to kick the port? */
	busy = ahci_check_status(ap) & (ATA_BUSY | ATA_DRQ);
	if (!busy && !force_restart)
		return 0;

	/* stop engine */
	rc = ahci_stop_engine(ap);
	if (rc)
		goto out_restart;

	/* need to do CLO? */
	if (!busy) {
		rc = 0;
		goto out_restart;
	}

	if (!(hpriv->cap & HOST_CAP_CLO)) {
		rc = -EOPNOTSUPP;
		goto out_restart;
	}
1234

1235
	/* perform CLO */
1236 1237 1238 1239
	tmp = readl(port_mmio + PORT_CMD);
	tmp |= PORT_CMD_CLO;
	writel(tmp, port_mmio + PORT_CMD);

1240
	rc = 0;
1241 1242 1243
	tmp = ata_wait_register(port_mmio + PORT_CMD,
				PORT_CMD_CLO, PORT_CMD_CLO, 1, 500);
	if (tmp & PORT_CMD_CLO)
1244
		rc = -EIO;
1245

1246 1247 1248 1249
	/* restart engine */
 out_restart:
	ahci_start_engine(ap);
	return rc;
1250 1251
}

1252 1253 1254
static int ahci_exec_polled_cmd(struct ata_port *ap, int pmp,
				struct ata_taskfile *tf, int is_cmd, u16 flags,
				unsigned long timeout_msec)
1255
{
1256
	const u32 cmd_fis_len = 5; /* five dwords */
T
Tejun Heo 已提交
1257
	struct ahci_port_priv *pp = ap->private_data;
1258
	void __iomem *port_mmio = ahci_port_base(ap);
1259 1260 1261 1262 1263 1264 1265 1266 1267 1268 1269 1270 1271 1272 1273 1274 1275 1276 1277 1278 1279 1280 1281
	u8 *fis = pp->cmd_tbl;
	u32 tmp;

	/* prep the command */
	ata_tf_to_fis(tf, pmp, is_cmd, fis);
	ahci_fill_cmd_slot(pp, 0, cmd_fis_len | flags | (pmp << 12));

	/* issue & wait */
	writel(1, port_mmio + PORT_CMD_ISSUE);

	if (timeout_msec) {
		tmp = ata_wait_register(port_mmio + PORT_CMD_ISSUE, 0x1, 0x1,
					1, timeout_msec);
		if (tmp & 0x1) {
			ahci_kick_engine(ap, 1);
			return -EBUSY;
		}
	} else
		readl(port_mmio + PORT_CMD_ISSUE);	/* flush */

	return 0;
}

T
Tejun Heo 已提交
1282
static int ahci_do_softreset(struct ata_link *link, unsigned int *class,
1283
			     int pmp, unsigned long deadline)
1284
{
T
Tejun Heo 已提交
1285
	struct ata_port *ap = link->ap;
T
Tejun Heo 已提交
1286
	const char *reason = NULL;
1287
	unsigned long now, msecs;
T
Tejun Heo 已提交
1288 1289 1290 1291 1292
	struct ata_taskfile tf;
	int rc;

	DPRINTK("ENTER\n");

T
Tejun Heo 已提交
1293
	if (ata_link_offline(link)) {
1294 1295 1296 1297 1298
		DPRINTK("PHY reports no device\n");
		*class = ATA_DEV_NONE;
		return 0;
	}

T
Tejun Heo 已提交
1299
	/* prepare for SRST (AHCI-1.1 10.4.1) */
1300
	rc = ahci_kick_engine(ap, 1);
T
Tejun Heo 已提交
1301
	if (rc && rc != -EOPNOTSUPP)
T
Tejun Heo 已提交
1302
		ata_link_printk(link, KERN_WARNING,
T
Tejun Heo 已提交
1303
				"failed to reset engine (errno=%d)\n", rc);
T
Tejun Heo 已提交
1304

T
Tejun Heo 已提交
1305
	ata_tf_init(link->device, &tf);
T
Tejun Heo 已提交
1306 1307

	/* issue the first D2H Register FIS */
1308 1309 1310 1311 1312
	msecs = 0;
	now = jiffies;
	if (time_after(now, deadline))
		msecs = jiffies_to_msecs(deadline - now);

T
Tejun Heo 已提交
1313
	tf.ctl |= ATA_SRST;
1314
	if (ahci_exec_polled_cmd(ap, pmp, &tf, 0,
1315
				 AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY, msecs)) {
T
Tejun Heo 已提交
1316 1317 1318 1319 1320 1321 1322 1323 1324 1325
		rc = -EIO;
		reason = "1st FIS failed";
		goto fail;
	}

	/* spec says at least 5us, but be generous and sleep for 1ms */
	msleep(1);

	/* issue the second D2H Register FIS */
	tf.ctl &= ~ATA_SRST;
1326
	ahci_exec_polled_cmd(ap, pmp, &tf, 0, 0, 0);
T
Tejun Heo 已提交
1327

1328 1329
	/* wait a while before checking status */
	ata_wait_after_reset(ap, deadline);
T
Tejun Heo 已提交
1330

T
Tejun Heo 已提交
1331 1332 1333 1334 1335
	rc = ata_wait_ready(ap, deadline);
	/* link occupied, -ENODEV too is an error */
	if (rc) {
		reason = "device not ready";
		goto fail;
T
Tejun Heo 已提交
1336
	}
T
Tejun Heo 已提交
1337
	*class = ahci_dev_classify(ap);
T
Tejun Heo 已提交
1338 1339 1340 1341 1342

	DPRINTK("EXIT, class=%u\n", *class);
	return 0;

 fail:
T
Tejun Heo 已提交
1343
	ata_link_printk(link, KERN_ERR, "softreset failed (%s)\n", reason);
T
Tejun Heo 已提交
1344 1345 1346
	return rc;
}

T
Tejun Heo 已提交
1347
static int ahci_softreset(struct ata_link *link, unsigned int *class,
1348 1349
			  unsigned long deadline)
{
T
Tejun Heo 已提交
1350 1351 1352 1353 1354 1355
	int pmp = 0;

	if (link->ap->flags & ATA_FLAG_PMP)
		pmp = SATA_PMP_CTRL_PORT;

	return ahci_do_softreset(link, class, pmp, deadline);
1356 1357
}

T
Tejun Heo 已提交
1358
static int ahci_hardreset(struct ata_link *link, unsigned int *class,
1359
			  unsigned long deadline)
1360
{
T
Tejun Heo 已提交
1361
	struct ata_port *ap = link->ap;
1362 1363 1364
	struct ahci_port_priv *pp = ap->private_data;
	u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
	struct ata_taskfile tf;
1365 1366 1367
	int rc;

	DPRINTK("ENTER\n");
L
Linus Torvalds 已提交
1368

1369
	ahci_stop_engine(ap);
1370 1371

	/* clear D2H reception area to properly wait for D2H FIS */
T
Tejun Heo 已提交
1372
	ata_tf_init(link->device, &tf);
1373
	tf.command = 0x80;
1374
	ata_tf_to_fis(&tf, 0, 0, d2h_fis);
1375

T
Tejun Heo 已提交
1376
	rc = sata_std_hardreset(link, class, deadline);
1377

1378
	ahci_start_engine(ap);
L
Linus Torvalds 已提交
1379

T
Tejun Heo 已提交
1380
	if (rc == 0 && ata_link_online(link))
1381
		*class = ahci_dev_classify(ap);
T
Tejun Heo 已提交
1382
	if (rc != -EAGAIN && *class == ATA_DEV_UNKNOWN)
1383
		*class = ATA_DEV_NONE;
L
Linus Torvalds 已提交
1384

1385 1386 1387 1388
	DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
	return rc;
}

T
Tejun Heo 已提交
1389
static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
1390
				 unsigned long deadline)
1391
{
T
Tejun Heo 已提交
1392
	struct ata_port *ap = link->ap;
1393
	u32 serror;
1394 1395 1396 1397
	int rc;

	DPRINTK("ENTER\n");

1398
	ahci_stop_engine(ap);
1399

T
Tejun Heo 已提交
1400
	rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
1401
				 deadline);
1402 1403

	/* vt8251 needs SError cleared for the port to operate */
1404 1405
	ahci_scr_read(ap, SCR_ERROR, &serror);
	ahci_scr_write(ap, SCR_ERROR, serror);
1406

1407
	ahci_start_engine(ap);
1408 1409 1410 1411 1412 1413 1414 1415 1416

	DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);

	/* vt8251 doesn't clear BSY on signature FIS reception,
	 * request follow-up softreset.
	 */
	return rc ?: -EAGAIN;
}

1417 1418 1419 1420 1421 1422 1423 1424 1425 1426 1427 1428 1429 1430 1431 1432 1433 1434 1435 1436 1437 1438 1439 1440 1441 1442 1443 1444 1445 1446 1447 1448 1449 1450 1451 1452 1453 1454 1455 1456 1457 1458 1459 1460 1461 1462 1463
static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
				unsigned long deadline)
{
	struct ata_port *ap = link->ap;
	struct ahci_port_priv *pp = ap->private_data;
	u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
	struct ata_taskfile tf;
	int rc;

	ahci_stop_engine(ap);

	/* clear D2H reception area to properly wait for D2H FIS */
	ata_tf_init(link->device, &tf);
	tf.command = 0x80;
	ata_tf_to_fis(&tf, 0, 0, d2h_fis);

	rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
				 deadline);

	ahci_start_engine(ap);

	if (rc || ata_link_offline(link))
		return rc;

	/* spec mandates ">= 2ms" before checking status */
	msleep(150);

	/* The pseudo configuration device on SIMG4726 attached to
	 * ASUS P5W-DH Deluxe doesn't send signature FIS after
	 * hardreset if no device is attached to the first downstream
	 * port && the pseudo device locks up on SRST w/ PMP==0.  To
	 * work around this, wait for !BSY only briefly.  If BSY isn't
	 * cleared, perform CLO and proceed to IDENTIFY (achieved by
	 * ATA_LFLAG_NO_SRST and ATA_LFLAG_ASSUME_ATA).
	 *
	 * Wait for two seconds.  Devices attached to downstream port
	 * which can't process the following IDENTIFY after this will
	 * have to be reset again.  For most cases, this should
	 * suffice while making probing snappish enough.
	 */
	rc = ata_wait_ready(ap, jiffies + 2 * HZ);
	if (rc)
		ahci_kick_engine(ap, 0);

	return 0;
}

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static void ahci_postreset(struct ata_link *link, unsigned int *class)
1465
{
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	struct ata_port *ap = link->ap;
1467
	void __iomem *port_mmio = ahci_port_base(ap);
1468 1469
	u32 new_tmp, tmp;

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	ata_std_postreset(link, class);
1471 1472 1473

	/* Make sure port's ATAPI bit is set appropriately */
	new_tmp = tmp = readl(port_mmio + PORT_CMD);
1474
	if (*class == ATA_DEV_ATAPI)
1475 1476 1477 1478 1479 1480 1481
		new_tmp |= PORT_CMD_ATAPI;
	else
		new_tmp &= ~PORT_CMD_ATAPI;
	if (new_tmp != tmp) {
		writel(new_tmp, port_mmio + PORT_CMD);
		readl(port_mmio + PORT_CMD); /* flush */
	}
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}

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static int ahci_pmp_softreset(struct ata_link *link, unsigned int *class,
			      unsigned long deadline)
{
	return ahci_do_softreset(link, class, link->pmp, deadline);
}

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static u8 ahci_check_status(struct ata_port *ap)
{
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	void __iomem *mmio = ap->ioaddr.cmd_addr;
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	return readl(mmio + PORT_TFDATA) & 0xFF;
}

static void ahci_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
{
	struct ahci_port_priv *pp = ap->private_data;
	u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;

	ata_tf_from_fis(d2h_fis, tf);
}

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static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl)
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{
1507
	struct scatterlist *sg;
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	struct ahci_sg *ahci_sg = cmd_tbl + AHCI_CMD_TBL_HDR_SZ;
	unsigned int si;
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	VPRINTK("ENTER\n");

	/*
	 * Next, the S/G list.
	 */
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	for_each_sg(qc->sg, sg, qc->n_elem, si) {
1517 1518 1519
		dma_addr_t addr = sg_dma_address(sg);
		u32 sg_len = sg_dma_len(sg);

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		ahci_sg[si].addr = cpu_to_le32(addr & 0xffffffff);
		ahci_sg[si].addr_hi = cpu_to_le32((addr >> 16) >> 16);
		ahci_sg[si].flags_size = cpu_to_le32(sg_len - 1);
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	}
1524

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	return si;
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}

static void ahci_qc_prep(struct ata_queued_cmd *qc)
{
1530 1531
	struct ata_port *ap = qc->ap;
	struct ahci_port_priv *pp = ap->private_data;
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	int is_atapi = ata_is_atapi(qc->tf.protocol);
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	void *cmd_tbl;
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	u32 opts;
	const u32 cmd_fis_len = 5; /* five dwords */
1536
	unsigned int n_elem;
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	/*
	 * Fill in command table information.  First, the header,
	 * a SATA Register - Host to Device command FIS.
	 */
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	cmd_tbl = pp->cmd_tbl + qc->tag * AHCI_CMD_TBL_SZ;

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	ata_tf_to_fis(&qc->tf, qc->dev->link->pmp, 1, cmd_tbl);
1545
	if (is_atapi) {
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		memset(cmd_tbl + AHCI_CMD_TBL_CDB, 0, 32);
		memcpy(cmd_tbl + AHCI_CMD_TBL_CDB, qc->cdb, qc->dev->cdb_len);
1548
	}
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1550 1551
	n_elem = 0;
	if (qc->flags & ATA_QCFLAG_DMAMAP)
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		n_elem = ahci_fill_sg(qc, cmd_tbl);
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1554 1555 1556
	/*
	 * Fill in command slot information.
	 */
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	opts = cmd_fis_len | n_elem << 16 | (qc->dev->link->pmp << 12);
1558 1559 1560
	if (qc->tf.flags & ATA_TFLAG_WRITE)
		opts |= AHCI_CMD_WRITE;
	if (is_atapi)
1561
		opts |= AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH;
1562

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	ahci_fill_cmd_slot(pp, qc->tag, opts);
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}

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static void ahci_error_intr(struct ata_port *ap, u32 irq_stat)
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{
1568
	struct ahci_host_priv *hpriv = ap->host->private_data;
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	struct ahci_port_priv *pp = ap->private_data;
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	struct ata_eh_info *host_ehi = &ap->link.eh_info;
	struct ata_link *link = NULL;
	struct ata_queued_cmd *active_qc;
	struct ata_eh_info *active_ehi;
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	u32 serror;
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	/* determine active link */
	ata_port_for_each_link(link, ap)
		if (ata_link_active(link))
			break;
	if (!link)
		link = &ap->link;

	active_qc = ata_qc_from_tag(ap, link->active_tag);
	active_ehi = &link->eh_info;

	/* record irq stat */
	ata_ehi_clear_desc(host_ehi);
	ata_ehi_push_desc(host_ehi, "irq_stat 0x%08x", irq_stat);
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	/* AHCI needs SError cleared; otherwise, it might lock up */
1591
	ahci_scr_read(ap, SCR_ERROR, &serror);
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	ahci_scr_write(ap, SCR_ERROR, serror);
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	host_ehi->serror |= serror;
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1595
	/* some controllers set IRQ_IF_ERR on device errors, ignore it */
1596
	if (hpriv->flags & AHCI_HFLAG_IGN_IRQ_IF_ERR)
1597 1598
		irq_stat &= ~PORT_IRQ_IF_ERR;

1599
	if (irq_stat & PORT_IRQ_TF_ERR) {
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		/* If qc is active, charge it; otherwise, the active
		 * link.  There's no active qc on NCQ errors.  It will
		 * be determined by EH by reading log page 10h.
		 */
		if (active_qc)
			active_qc->err_mask |= AC_ERR_DEV;
		else
			active_ehi->err_mask |= AC_ERR_DEV;

1609
		if (hpriv->flags & AHCI_HFLAG_IGN_SERR_INTERNAL)
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			host_ehi->serror &= ~SERR_INTERNAL;
	}

	if (irq_stat & PORT_IRQ_UNK_FIS) {
		u32 *unk = (u32 *)(pp->rx_fis + RX_FIS_UNK);

		active_ehi->err_mask |= AC_ERR_HSM;
		active_ehi->action |= ATA_EH_SOFTRESET;
		ata_ehi_push_desc(active_ehi,
				  "unknown FIS %08x %08x %08x %08x" ,
				  unk[0], unk[1], unk[2], unk[3]);
	}

	if (ap->nr_pmp_links && (irq_stat & PORT_IRQ_BAD_PMP)) {
		active_ehi->err_mask |= AC_ERR_HSM;
		active_ehi->action |= ATA_EH_SOFTRESET;
		ata_ehi_push_desc(active_ehi, "incorrect PMP");
1627
	}
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	if (irq_stat & (PORT_IRQ_HBUS_ERR | PORT_IRQ_HBUS_DATA_ERR)) {
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		host_ehi->err_mask |= AC_ERR_HOST_BUS;
		host_ehi->action |= ATA_EH_SOFTRESET;
		ata_ehi_push_desc(host_ehi, "host bus error");
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	}

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	if (irq_stat & PORT_IRQ_IF_ERR) {
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		host_ehi->err_mask |= AC_ERR_ATA_BUS;
		host_ehi->action |= ATA_EH_SOFTRESET;
		ata_ehi_push_desc(host_ehi, "interface fatal error");
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	}
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	if (irq_stat & (PORT_IRQ_CONNECT | PORT_IRQ_PHYRDY)) {
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		ata_ehi_hotplugged(host_ehi);
		ata_ehi_push_desc(host_ehi, "%s",
			irq_stat & PORT_IRQ_CONNECT ?
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			"connection status changed" : "PHY RDY changed");
	}

	/* okay, let's hand over to EH */
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	if (irq_stat & PORT_IRQ_FREEZE)
		ata_port_freeze(ap);
	else
		ata_port_abort(ap);
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}

1656
static void ahci_port_intr(struct ata_port *ap)
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{
1658
	void __iomem *port_mmio = ap->ioaddr.cmd_addr;
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	struct ata_eh_info *ehi = &ap->link.eh_info;
1660
	struct ahci_port_priv *pp = ap->private_data;
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	struct ahci_host_priv *hpriv = ap->host->private_data;
1662
	int resetting = !!(ap->pflags & ATA_PFLAG_RESETTING);
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	u32 status, qc_active;
1664
	int rc;
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	status = readl(port_mmio + PORT_IRQ_STAT);
	writel(status, port_mmio + PORT_IRQ_STAT);

1669 1670 1671 1672
	/* ignore BAD_PMP while resetting */
	if (unlikely(resetting))
		status &= ~PORT_IRQ_BAD_PMP;

1673 1674 1675 1676 1677 1678 1679 1680 1681 1682 1683
	/* If we are getting PhyRdy, this is
 	 * just a power state change, we should
 	 * clear out this, plus the PhyRdy/Comm
 	 * Wake bits from Serror
 	 */
	if ((hpriv->flags & AHCI_HFLAG_NO_HOTPLUG) &&
		(status & PORT_IRQ_PHYRDY)) {
		status &= ~PORT_IRQ_PHYRDY;
		ahci_scr_write(ap, SCR_ERROR, ((1 << 16) | (1 << 18)));
	}

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	if (unlikely(status & PORT_IRQ_ERROR)) {
		ahci_error_intr(ap, status);
		return;
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	}

1689
	if (status & PORT_IRQ_SDB_FIS) {
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		/* If SNotification is available, leave notification
		 * handling to sata_async_notification().  If not,
		 * emulate it by snooping SDB FIS RX area.
		 *
		 * Snooping FIS RX area is probably cheaper than
		 * poking SNotification but some constrollers which
		 * implement SNotification, ICH9 for example, don't
		 * store AN SDB FIS into receive area.
1698
		 */
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		if (hpriv->cap & HOST_CAP_SNTF)
1700
			sata_async_notification(ap);
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		else {
			/* If the 'N' bit in word 0 of the FIS is set,
			 * we just received asynchronous notification.
			 * Tell libata about it.
			 */
			const __le32 *f = pp->rx_fis + RX_FIS_SDB;
			u32 f0 = le32_to_cpu(f[0]);

			if (f0 & (1 << 15))
				sata_async_notification(ap);
		}
1712 1713
	}

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	/* pp->active_link is valid iff any command is in flight */
	if (ap->qc_active && pp->active_link->sactive)
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		qc_active = readl(port_mmio + PORT_SCR_ACT);
	else
		qc_active = readl(port_mmio + PORT_CMD_ISSUE);

	rc = ata_qc_complete_multiple(ap, qc_active, NULL);
1721

1722 1723
	/* while resetting, invalid completions are expected */
	if (unlikely(rc < 0 && !resetting)) {
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		ehi->err_mask |= AC_ERR_HSM;
		ehi->action |= ATA_EH_SOFTRESET;
		ata_port_freeze(ap);
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	}
}

static void ahci_irq_clear(struct ata_port *ap)
{
	/* TODO */
}

1735
static irqreturn_t ahci_interrupt(int irq, void *dev_instance)
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{
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	struct ata_host *host = dev_instance;
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	struct ahci_host_priv *hpriv;
	unsigned int i, handled = 0;
1740
	void __iomem *mmio;
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	u32 irq_stat, irq_ack = 0;

	VPRINTK("ENTER\n");

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	hpriv = host->private_data;
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	mmio = host->iomap[AHCI_PCI_BAR];
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	/* sigh.  0xffffffff is a valid return from h/w */
	irq_stat = readl(mmio + HOST_IRQ_STAT);
	irq_stat &= hpriv->port_map;
	if (!irq_stat)
		return IRQ_NONE;

1754
	spin_lock(&host->lock);
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1756
	for (i = 0; i < host->n_ports; i++) {
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		struct ata_port *ap;

1759 1760 1761
		if (!(irq_stat & (1 << i)))
			continue;

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		ap = host->ports[i];
1763
		if (ap) {
1764
			ahci_port_intr(ap);
1765 1766 1767
			VPRINTK("port %u\n", i);
		} else {
			VPRINTK("port %u (no irq)\n", i);
1768
			if (ata_ratelimit())
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				dev_printk(KERN_WARNING, host->dev,
1770
					"interrupt on disabled port %u\n", i);
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		}
1772 1773

		irq_ack |= (1 << i);
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	}

	if (irq_ack) {
		writel(irq_ack, mmio + HOST_IRQ_STAT);
		handled = 1;
	}

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	spin_unlock(&host->lock);
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	VPRINTK("EXIT\n");

	return IRQ_RETVAL(handled);
}

1788
static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc)
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{
	struct ata_port *ap = qc->ap;
1791
	void __iomem *port_mmio = ahci_port_base(ap);
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	struct ahci_port_priv *pp = ap->private_data;

	/* Keep track of the currently active link.  It will be used
	 * in completion path to determine whether NCQ phase is in
	 * progress.
	 */
	pp->active_link = qc->dev->link;
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	if (qc->tf.protocol == ATA_PROT_NCQ)
		writel(1 << qc->tag, port_mmio + PORT_SCR_ACT);
	writel(1 << qc->tag, port_mmio + PORT_CMD_ISSUE);
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	readl(port_mmio + PORT_CMD_ISSUE);	/* flush */

	return 0;
}

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static void ahci_freeze(struct ata_port *ap)
{
1810
	void __iomem *port_mmio = ahci_port_base(ap);
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	/* turn IRQ off */
	writel(0, port_mmio + PORT_IRQ_MASK);
}

static void ahci_thaw(struct ata_port *ap)
{
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	void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR];
1819
	void __iomem *port_mmio = ahci_port_base(ap);
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	u32 tmp;
1821
	struct ahci_port_priv *pp = ap->private_data;
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	/* clear IRQ */
	tmp = readl(port_mmio + PORT_IRQ_STAT);
	writel(tmp, port_mmio + PORT_IRQ_STAT);
1826
	writel(1 << ap->port_no, mmio + HOST_IRQ_STAT);
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1828 1829
	/* turn IRQ back on */
	writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
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}

static void ahci_error_handler(struct ata_port *ap)
{
1834
	if (!(ap->pflags & ATA_PFLAG_FROZEN)) {
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		/* restart engine */
1836 1837
		ahci_stop_engine(ap);
		ahci_start_engine(ap);
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	}

	/* perform recovery */
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	sata_pmp_do_eh(ap, ata_std_prereset, ahci_softreset,
		       ahci_hardreset, ahci_postreset,
		       sata_pmp_std_prereset, ahci_pmp_softreset,
		       sata_pmp_std_hardreset, sata_pmp_std_postreset);
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}

1847 1848 1849 1850
static void ahci_vt8251_error_handler(struct ata_port *ap)
{
	if (!(ap->pflags & ATA_PFLAG_FROZEN)) {
		/* restart engine */
1851 1852
		ahci_stop_engine(ap);
		ahci_start_engine(ap);
1853 1854 1855 1856 1857 1858 1859
	}

	/* perform recovery */
	ata_do_eh(ap, ata_std_prereset, ahci_softreset, ahci_vt8251_hardreset,
		  ahci_postreset);
}

1860 1861 1862 1863 1864 1865 1866 1867 1868 1869 1870 1871 1872
static void ahci_p5wdh_error_handler(struct ata_port *ap)
{
	if (!(ap->pflags & ATA_PFLAG_FROZEN)) {
		/* restart engine */
		ahci_stop_engine(ap);
		ahci_start_engine(ap);
	}

	/* perform recovery */
	ata_do_eh(ap, ata_std_prereset, ahci_softreset, ahci_p5wdh_hardreset,
		  ahci_postreset);
}

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static void ahci_post_internal_cmd(struct ata_queued_cmd *qc)
{
	struct ata_port *ap = qc->ap;

1877 1878 1879
	/* make DMA engine forget about the failed command */
	if (qc->flags & ATA_QCFLAG_FAILED)
		ahci_kick_engine(ap, 1);
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}

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static void ahci_pmp_attach(struct ata_port *ap)
{
	void __iomem *port_mmio = ahci_port_base(ap);
1885
	struct ahci_port_priv *pp = ap->private_data;
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	u32 cmd;

	cmd = readl(port_mmio + PORT_CMD);
	cmd |= PORT_CMD_PMP;
	writel(cmd, port_mmio + PORT_CMD);
1891 1892 1893

	pp->intr_mask |= PORT_IRQ_BAD_PMP;
	writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
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}

static void ahci_pmp_detach(struct ata_port *ap)
{
	void __iomem *port_mmio = ahci_port_base(ap);
1899
	struct ahci_port_priv *pp = ap->private_data;
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	u32 cmd;

	cmd = readl(port_mmio + PORT_CMD);
	cmd &= ~PORT_CMD_PMP;
	writel(cmd, port_mmio + PORT_CMD);
1905 1906 1907

	pp->intr_mask &= ~PORT_IRQ_BAD_PMP;
	writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
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}

1910 1911 1912 1913 1914
static int ahci_port_resume(struct ata_port *ap)
{
	ahci_power_up(ap);
	ahci_start_port(ap);

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	if (ap->nr_pmp_links)
		ahci_pmp_attach(ap);
	else
		ahci_pmp_detach(ap);

1920 1921 1922
	return 0;
}

1923
#ifdef CONFIG_PM
1924 1925 1926 1927 1928
static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg)
{
	const char *emsg = NULL;
	int rc;

1929
	rc = ahci_deinit_port(ap, &emsg);
1930
	if (rc == 0)
1931
		ahci_power_down(ap);
1932
	else {
1933
		ata_port_printk(ap, KERN_ERR, "%s (%d)\n", emsg, rc);
1934
		ahci_start_port(ap);
1935 1936 1937 1938 1939 1940 1941
	}

	return rc;
}

static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
{
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	struct ata_host *host = dev_get_drvdata(&pdev->dev);
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	void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
1944 1945
	u32 ctl;

1946
	if (mesg.event & PM_EVENT_SLEEP) {
1947 1948 1949 1950 1951 1952 1953 1954 1955 1956 1957 1958 1959 1960 1961
		/* AHCI spec rev1.1 section 8.3.3:
		 * Software must disable interrupts prior to requesting a
		 * transition of the HBA to D3 state.
		 */
		ctl = readl(mmio + HOST_CTL);
		ctl &= ~HOST_IRQ_EN;
		writel(ctl, mmio + HOST_CTL);
		readl(mmio + HOST_CTL); /* flush */
	}

	return ata_pci_device_suspend(pdev, mesg);
}

static int ahci_pci_device_resume(struct pci_dev *pdev)
{
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	struct ata_host *host = dev_get_drvdata(&pdev->dev);
1963 1964
	int rc;

1965 1966 1967
	rc = ata_pci_device_do_resume(pdev);
	if (rc)
		return rc;
1968 1969

	if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
1970
		rc = ahci_reset_controller(host);
1971 1972 1973
		if (rc)
			return rc;

1974
		ahci_init_controller(host);
1975 1976
	}

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	ata_host_resume(host);
1978 1979 1980

	return 0;
}
1981
#endif
1982

1983 1984
static int ahci_port_start(struct ata_port *ap)
{
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	struct device *dev = ap->host->dev;
1986 1987 1988 1989
	struct ahci_port_priv *pp;
	void *mem;
	dma_addr_t mem_dma;

1990
	pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
1991 1992 1993
	if (!pp)
		return -ENOMEM;

1994 1995 1996
	mem = dmam_alloc_coherent(dev, AHCI_PORT_PRIV_DMA_SZ, &mem_dma,
				  GFP_KERNEL);
	if (!mem)
1997 1998 1999 2000 2001 2002 2003 2004 2005 2006 2007 2008 2009 2010 2011 2012 2013 2014 2015 2016 2017 2018 2019 2020 2021 2022 2023 2024 2025
		return -ENOMEM;
	memset(mem, 0, AHCI_PORT_PRIV_DMA_SZ);

	/*
	 * First item in chunk of DMA memory: 32-slot command table,
	 * 32 bytes each in size
	 */
	pp->cmd_slot = mem;
	pp->cmd_slot_dma = mem_dma;

	mem += AHCI_CMD_SLOT_SZ;
	mem_dma += AHCI_CMD_SLOT_SZ;

	/*
	 * Second item: Received-FIS area
	 */
	pp->rx_fis = mem;
	pp->rx_fis_dma = mem_dma;

	mem += AHCI_RX_FIS_SZ;
	mem_dma += AHCI_RX_FIS_SZ;

	/*
	 * Third item: data area for storing a single command
	 * and its scatter-gather table
	 */
	pp->cmd_tbl = mem;
	pp->cmd_tbl_dma = mem_dma;

2026
	/*
2027 2028 2029
	 * Save off initial list of interrupts to be enabled.
	 * This could be changed later
	 */
2030 2031
	pp->intr_mask = DEF_PORT_IRQ;

2032 2033
	ap->private_data = pp;

2034 2035
	/* engage engines, captain */
	return ahci_port_resume(ap);
2036 2037 2038 2039
}

static void ahci_port_stop(struct ata_port *ap)
{
2040 2041
	const char *emsg = NULL;
	int rc;
2042

2043
	/* de-initialize port */
2044
	rc = ahci_deinit_port(ap, &emsg);
2045 2046
	if (rc)
		ata_port_printk(ap, KERN_WARNING, "%s (%d)\n", emsg, rc);
2047 2048
}

2049
static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac)
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{
	int rc;

	if (using_dac &&
	    !pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
		rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
		if (rc) {
			rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
			if (rc) {
2059 2060
				dev_printk(KERN_ERR, &pdev->dev,
					   "64-bit DMA enable failed\n");
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				return rc;
			}
		}
	} else {
		rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
		if (rc) {
2067 2068
			dev_printk(KERN_ERR, &pdev->dev,
				   "32-bit DMA enable failed\n");
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			return rc;
		}
		rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
		if (rc) {
2073 2074
			dev_printk(KERN_ERR, &pdev->dev,
				   "32-bit consistent DMA enable failed\n");
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			return rc;
		}
	}
	return 0;
}

2081
static void ahci_print_info(struct ata_host *host)
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{
2083 2084 2085
	struct ahci_host_priv *hpriv = host->private_data;
	struct pci_dev *pdev = to_pci_dev(host->dev);
	void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
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2086 2087 2088 2089 2090 2091 2092 2093 2094 2095 2096 2097 2098 2099 2100 2101 2102 2103
	u32 vers, cap, impl, speed;
	const char *speed_s;
	u16 cc;
	const char *scc_s;

	vers = readl(mmio + HOST_VERSION);
	cap = hpriv->cap;
	impl = hpriv->port_map;

	speed = (cap >> 20) & 0xf;
	if (speed == 1)
		speed_s = "1.5";
	else if (speed == 2)
		speed_s = "3";
	else
		speed_s = "?";

	pci_read_config_word(pdev, 0x0a, &cc);
2104
	if (cc == PCI_CLASS_STORAGE_IDE)
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		scc_s = "IDE";
2106
	else if (cc == PCI_CLASS_STORAGE_SATA)
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		scc_s = "SATA";
2108
	else if (cc == PCI_CLASS_STORAGE_RAID)
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		scc_s = "RAID";
	else
		scc_s = "unknown";

2113 2114
	dev_printk(KERN_INFO, &pdev->dev,
		"AHCI %02x%02x.%02x%02x "
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		"%u slots %u ports %s Gbps 0x%x impl %s mode\n"
2116
		,
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2118 2119 2120 2121
		(vers >> 24) & 0xff,
		(vers >> 16) & 0xff,
		(vers >> 8) & 0xff,
		vers & 0xff,
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2122 2123 2124 2125 2126 2127 2128

		((cap >> 8) & 0x1f) + 1,
		(cap & 0x1f) + 1,
		speed_s,
		impl,
		scc_s);

2129 2130
	dev_printk(KERN_INFO, &pdev->dev,
		"flags: "
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		"%s%s%s%s%s%s%s"
		"%s%s%s%s%s%s%s\n"
2133
		,
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		cap & (1 << 31) ? "64bit " : "",
		cap & (1 << 30) ? "ncq " : "",
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		cap & (1 << 29) ? "sntf " : "",
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		cap & (1 << 28) ? "ilck " : "",
		cap & (1 << 27) ? "stag " : "",
		cap & (1 << 26) ? "pm " : "",
		cap & (1 << 25) ? "led " : "",

		cap & (1 << 24) ? "clo " : "",
		cap & (1 << 19) ? "nz " : "",
		cap & (1 << 18) ? "only " : "",
		cap & (1 << 17) ? "pmp " : "",
		cap & (1 << 15) ? "pio " : "",
		cap & (1 << 14) ? "slum " : "",
		cap & (1 << 13) ? "part " : ""
		);
}

2153 2154 2155 2156 2157 2158 2159 2160 2161 2162 2163 2164 2165 2166 2167 2168 2169 2170 2171 2172 2173 2174 2175 2176 2177 2178 2179 2180 2181 2182 2183 2184 2185 2186 2187 2188 2189 2190 2191 2192 2193 2194 2195 2196 2197
/* On ASUS P5W DH Deluxe, the second port of PCI device 00:1f.2 is
 * hardwired to on-board SIMG 4726.  The chipset is ICH8 and doesn't
 * support PMP and the 4726 either directly exports the device
 * attached to the first downstream port or acts as a hardware storage
 * controller and emulate a single ATA device (can be RAID 0/1 or some
 * other configuration).
 *
 * When there's no device attached to the first downstream port of the
 * 4726, "Config Disk" appears, which is a pseudo ATA device to
 * configure the 4726.  However, ATA emulation of the device is very
 * lame.  It doesn't send signature D2H Reg FIS after the initial
 * hardreset, pukes on SRST w/ PMP==0 and has bunch of other issues.
 *
 * The following function works around the problem by always using
 * hardreset on the port and not depending on receiving signature FIS
 * afterward.  If signature FIS isn't received soon, ATA class is
 * assumed without follow-up softreset.
 */
static void ahci_p5wdh_workaround(struct ata_host *host)
{
	static struct dmi_system_id sysids[] = {
		{
			.ident = "P5W DH Deluxe",
			.matches = {
				DMI_MATCH(DMI_SYS_VENDOR,
					  "ASUSTEK COMPUTER INC"),
				DMI_MATCH(DMI_PRODUCT_NAME, "P5W DH Deluxe"),
			},
		},
		{ }
	};
	struct pci_dev *pdev = to_pci_dev(host->dev);

	if (pdev->bus->number == 0 && pdev->devfn == PCI_DEVFN(0x1f, 2) &&
	    dmi_check_system(sysids)) {
		struct ata_port *ap = host->ports[1];

		dev_printk(KERN_INFO, &pdev->dev, "enabling ASUS P5W DH "
			   "Deluxe on-board SIMG4726 workaround\n");

		ap->ops = &ahci_p5wdh_ops;
		ap->link.flags |= ATA_LFLAG_NO_SRST | ATA_LFLAG_ASSUME_ATA;
	}
}

2198
static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
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{
	static int printed_version;
2201 2202
	struct ata_port_info pi = ahci_port_info[ent->driver_data];
	const struct ata_port_info *ppi[] = { &pi, NULL };
2203
	struct device *dev = &pdev->dev;
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2204
	struct ahci_host_priv *hpriv;
2205
	struct ata_host *host;
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2206
	int n_ports, i, rc;
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2207 2208 2209

	VPRINTK("ENTER\n");

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2210 2211
	WARN_ON(ATA_MAX_QUEUE > AHCI_MAX_CMDS);

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2212
	if (!printed_version++)
2213
		dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
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2214

2215
	/* acquire resources */
2216
	rc = pcim_enable_device(pdev);
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2217 2218 2219
	if (rc)
		return rc;

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2220 2221
	rc = pcim_iomap_regions(pdev, 1 << AHCI_PCI_BAR, DRV_NAME);
	if (rc == -EBUSY)
2222
		pcim_pin_device(pdev);
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2223
	if (rc)
2224
		return rc;
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2225

2226 2227 2228 2229 2230 2231 2232 2233 2234 2235 2236 2237 2238 2239 2240 2241
	if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
	    (pdev->device == 0x2652 || pdev->device == 0x2653)) {
		u8 map;

		/* ICH6s share the same PCI ID for both piix and ahci
		 * modes.  Enabling ahci mode while MAP indicates
		 * combined mode is a bad idea.  Yield to ata_piix.
		 */
		pci_read_config_byte(pdev, ICH_MAP, &map);
		if (map & 0x3) {
			dev_printk(KERN_INFO, &pdev->dev, "controller is in "
				   "combined mode, can't enable AHCI mode\n");
			return -ENODEV;
		}
	}

2242 2243 2244
	hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
	if (!hpriv)
		return -ENOMEM;
2245 2246 2247 2248
	hpriv->flags |= (unsigned long)pi.private_data;

	if ((hpriv->flags & AHCI_HFLAG_NO_MSI) || pci_enable_msi(pdev))
		pci_intx(pdev, 1);
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2249

2250
	/* save initial config */
2251
	ahci_save_initial_config(pdev, hpriv);
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2252

2253
	/* prepare host */
2254
	if (hpriv->cap & HOST_CAP_NCQ)
2255
		pi.flags |= ATA_FLAG_NCQ;
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2256

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2257 2258 2259
	if (hpriv->cap & HOST_CAP_PMP)
		pi.flags |= ATA_FLAG_PMP;

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2260 2261 2262 2263 2264 2265 2266 2267
	/* CAP.NP sometimes indicate the index of the last enabled
	 * port, at other times, that of the last possible port, so
	 * determining the maximum port number requires looking at
	 * both CAP.NP and port_map.
	 */
	n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map));

	host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
2268 2269 2270 2271 2272 2273
	if (!host)
		return -ENOMEM;
	host->iomap = pcim_iomap_table(pdev);
	host->private_data = hpriv;

	for (i = 0; i < host->n_ports; i++) {
2274 2275
		struct ata_port *ap = host->ports[i];
		void __iomem *port_mmio = ahci_port_base(ap);
2276

2277 2278 2279 2280
		ata_port_pbar_desc(ap, AHCI_PCI_BAR, -1, "abar");
		ata_port_pbar_desc(ap, AHCI_PCI_BAR,
				   0x100 + ap->port_no * 0x80, "port");

2281 2282 2283
		/* set initial link pm policy */
		ap->pm_policy = NOT_AVAILABLE;

2284
		/* standard SATA port setup */
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2285
		if (hpriv->port_map & (1 << i))
2286
			ap->ioaddr.cmd_addr = port_mmio;
2287 2288 2289 2290

		/* disabled/not-implemented port */
		else
			ap->ops = &ata_dummy_port_ops;
2291
	}
2292

2293 2294 2295
	/* apply workaround for ASUS P5W DH Deluxe mainboard */
	ahci_p5wdh_workaround(host);

2296 2297
	/* initialize adapter */
	rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64);
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	if (rc)
2299
		return rc;
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2301 2302 2303
	rc = ahci_reset_controller(host);
	if (rc)
		return rc;
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2304

2305 2306
	ahci_init_controller(host);
	ahci_print_info(host);
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2308 2309 2310
	pci_set_master(pdev);
	return ata_host_activate(host, pdev->irq, ahci_interrupt, IRQF_SHARED,
				 &ahci_sht);
2311
}
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static int __init ahci_init(void)
{
2315
	return pci_register_driver(&ahci_pci_driver);
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}

static void __exit ahci_exit(void)
{
	pci_unregister_driver(&ahci_pci_driver);
}


MODULE_AUTHOR("Jeff Garzik");
MODULE_DESCRIPTION("AHCI SATA low-level driver");
MODULE_LICENSE("GPL");
MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
2328
MODULE_VERSION(DRV_VERSION);
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module_init(ahci_init);
module_exit(ahci_exit);