clock-exynos4.c 41.6 KB
Newer Older
1
/*
2
 * Copyright (c) 2010-2012 Samsung Electronics Co., Ltd.
K
Kukjin Kim 已提交
3
 *		http://www.samsung.com
4
 *
K
Kukjin Kim 已提交
5
 * EXYNOS4 - Clock support
6 7 8 9 10 11 12 13 14
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
*/

#include <linux/kernel.h>
#include <linux/err.h>
#include <linux/io.h>
15
#include <linux/syscore_ops.h>
16 17 18 19 20 21 22

#include <plat/cpu-freq.h>
#include <plat/clock.h>
#include <plat/cpu.h>
#include <plat/pll.h>
#include <plat/s5p-clock.h>
#include <plat/clock-clksrc.h>
23
#include <plat/pm.h>
24 25 26

#include <mach/map.h>
#include <mach/regs-clock.h>
27
#include <mach/sysmmu.h>
28

29
#include "common.h"
30
#include "clock-exynos4.h"
31

32
#ifdef CONFIG_PM_SLEEP
33
static struct sleep_save exynos4_clock_save[] = {
34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94
	SAVE_ITEM(EXYNOS4_CLKDIV_LEFTBUS),
	SAVE_ITEM(EXYNOS4_CLKGATE_IP_LEFTBUS),
	SAVE_ITEM(EXYNOS4_CLKDIV_RIGHTBUS),
	SAVE_ITEM(EXYNOS4_CLKGATE_IP_RIGHTBUS),
	SAVE_ITEM(EXYNOS4_CLKSRC_TOP0),
	SAVE_ITEM(EXYNOS4_CLKSRC_TOP1),
	SAVE_ITEM(EXYNOS4_CLKSRC_CAM),
	SAVE_ITEM(EXYNOS4_CLKSRC_TV),
	SAVE_ITEM(EXYNOS4_CLKSRC_MFC),
	SAVE_ITEM(EXYNOS4_CLKSRC_G3D),
	SAVE_ITEM(EXYNOS4_CLKSRC_LCD0),
	SAVE_ITEM(EXYNOS4_CLKSRC_MAUDIO),
	SAVE_ITEM(EXYNOS4_CLKSRC_FSYS),
	SAVE_ITEM(EXYNOS4_CLKSRC_PERIL0),
	SAVE_ITEM(EXYNOS4_CLKSRC_PERIL1),
	SAVE_ITEM(EXYNOS4_CLKDIV_CAM),
	SAVE_ITEM(EXYNOS4_CLKDIV_TV),
	SAVE_ITEM(EXYNOS4_CLKDIV_MFC),
	SAVE_ITEM(EXYNOS4_CLKDIV_G3D),
	SAVE_ITEM(EXYNOS4_CLKDIV_LCD0),
	SAVE_ITEM(EXYNOS4_CLKDIV_MAUDIO),
	SAVE_ITEM(EXYNOS4_CLKDIV_FSYS0),
	SAVE_ITEM(EXYNOS4_CLKDIV_FSYS1),
	SAVE_ITEM(EXYNOS4_CLKDIV_FSYS2),
	SAVE_ITEM(EXYNOS4_CLKDIV_FSYS3),
	SAVE_ITEM(EXYNOS4_CLKDIV_PERIL0),
	SAVE_ITEM(EXYNOS4_CLKDIV_PERIL1),
	SAVE_ITEM(EXYNOS4_CLKDIV_PERIL2),
	SAVE_ITEM(EXYNOS4_CLKDIV_PERIL3),
	SAVE_ITEM(EXYNOS4_CLKDIV_PERIL4),
	SAVE_ITEM(EXYNOS4_CLKDIV_PERIL5),
	SAVE_ITEM(EXYNOS4_CLKDIV_TOP),
	SAVE_ITEM(EXYNOS4_CLKSRC_MASK_TOP),
	SAVE_ITEM(EXYNOS4_CLKSRC_MASK_CAM),
	SAVE_ITEM(EXYNOS4_CLKSRC_MASK_TV),
	SAVE_ITEM(EXYNOS4_CLKSRC_MASK_LCD0),
	SAVE_ITEM(EXYNOS4_CLKSRC_MASK_MAUDIO),
	SAVE_ITEM(EXYNOS4_CLKSRC_MASK_FSYS),
	SAVE_ITEM(EXYNOS4_CLKSRC_MASK_PERIL0),
	SAVE_ITEM(EXYNOS4_CLKSRC_MASK_PERIL1),
	SAVE_ITEM(EXYNOS4_CLKDIV2_RATIO),
	SAVE_ITEM(EXYNOS4_CLKGATE_SCLKCAM),
	SAVE_ITEM(EXYNOS4_CLKGATE_IP_CAM),
	SAVE_ITEM(EXYNOS4_CLKGATE_IP_TV),
	SAVE_ITEM(EXYNOS4_CLKGATE_IP_MFC),
	SAVE_ITEM(EXYNOS4_CLKGATE_IP_G3D),
	SAVE_ITEM(EXYNOS4_CLKGATE_IP_LCD0),
	SAVE_ITEM(EXYNOS4_CLKGATE_IP_FSYS),
	SAVE_ITEM(EXYNOS4_CLKGATE_IP_GPS),
	SAVE_ITEM(EXYNOS4_CLKGATE_IP_PERIL),
	SAVE_ITEM(EXYNOS4_CLKGATE_BLOCK),
	SAVE_ITEM(EXYNOS4_CLKSRC_MASK_DMC),
	SAVE_ITEM(EXYNOS4_CLKSRC_DMC),
	SAVE_ITEM(EXYNOS4_CLKDIV_DMC0),
	SAVE_ITEM(EXYNOS4_CLKDIV_DMC1),
	SAVE_ITEM(EXYNOS4_CLKGATE_IP_DMC),
	SAVE_ITEM(EXYNOS4_CLKSRC_CPU),
	SAVE_ITEM(EXYNOS4_CLKDIV_CPU),
	SAVE_ITEM(EXYNOS4_CLKDIV_CPU + 0x4),
	SAVE_ITEM(EXYNOS4_CLKGATE_SCLKCPU),
	SAVE_ITEM(EXYNOS4_CLKGATE_IP_CPU),
95
};
96
#endif
97

98
static struct clk exynos4_clk_sclk_hdmi27m = {
99 100 101 102
	.name		= "sclk_hdmi27m",
	.rate		= 27000000,
};

103
static struct clk exynos4_clk_sclk_hdmiphy = {
104 105 106
	.name		= "sclk_hdmiphy",
};

107
static struct clk exynos4_clk_sclk_usbphy0 = {
108 109 110 111
	.name		= "sclk_usbphy0",
	.rate		= 27000000,
};

112
static struct clk exynos4_clk_sclk_usbphy1 = {
113 114 115
	.name		= "sclk_usbphy1",
};

116 117 118 119 120
static struct clk dummy_apb_pclk = {
	.name		= "apb_pclk",
	.id		= -1,
};

K
Kukjin Kim 已提交
121
static int exynos4_clksrc_mask_top_ctrl(struct clk *clk, int enable)
122
{
123
	return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_TOP, clk, enable);
124 125
}

K
Kukjin Kim 已提交
126
static int exynos4_clksrc_mask_cam_ctrl(struct clk *clk, int enable)
127
{
128
	return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_CAM, clk, enable);
129 130
}

K
Kukjin Kim 已提交
131
static int exynos4_clksrc_mask_lcd0_ctrl(struct clk *clk, int enable)
132
{
133
	return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_LCD0, clk, enable);
134 135
}

136
int exynos4_clksrc_mask_fsys_ctrl(struct clk *clk, int enable)
137
{
138
	return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_FSYS, clk, enable);
139 140
}

K
Kukjin Kim 已提交
141
static int exynos4_clksrc_mask_peril0_ctrl(struct clk *clk, int enable)
142
{
143
	return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_PERIL0, clk, enable);
144 145
}

K
Kukjin Kim 已提交
146
static int exynos4_clksrc_mask_peril1_ctrl(struct clk *clk, int enable)
147
{
148
	return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_PERIL1, clk, enable);
149 150
}

151 152
static int exynos4_clk_ip_mfc_ctrl(struct clk *clk, int enable)
{
153
	return s5p_gatectrl(EXYNOS4_CLKGATE_IP_MFC, clk, enable);
154 155
}

156 157
static int exynos4_clksrc_mask_tv_ctrl(struct clk *clk, int enable)
{
158
	return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_TV, clk, enable);
159 160
}

K
Kukjin Kim 已提交
161
static int exynos4_clk_ip_cam_ctrl(struct clk *clk, int enable)
J
Jongpill Lee 已提交
162
{
163
	return s5p_gatectrl(EXYNOS4_CLKGATE_IP_CAM, clk, enable);
J
Jongpill Lee 已提交
164 165
}

166 167
static int exynos4_clk_ip_tv_ctrl(struct clk *clk, int enable)
{
168
	return s5p_gatectrl(EXYNOS4_CLKGATE_IP_TV, clk, enable);
169 170
}

K
Kukjin Kim 已提交
171
static int exynos4_clk_ip_image_ctrl(struct clk *clk, int enable)
J
Jongpill Lee 已提交
172
{
173
	return s5p_gatectrl(EXYNOS4_CLKGATE_IP_IMAGE, clk, enable);
J
Jongpill Lee 已提交
174 175
}

K
Kukjin Kim 已提交
176
static int exynos4_clk_ip_lcd0_ctrl(struct clk *clk, int enable)
J
Jongpill Lee 已提交
177
{
178
	return s5p_gatectrl(EXYNOS4_CLKGATE_IP_LCD0, clk, enable);
J
Jongpill Lee 已提交
179 180
}

181
int exynos4_clk_ip_lcd1_ctrl(struct clk *clk, int enable)
J
Jongpill Lee 已提交
182
{
183
	return s5p_gatectrl(EXYNOS4210_CLKGATE_IP_LCD1, clk, enable);
J
Jongpill Lee 已提交
184 185
}

186
int exynos4_clk_ip_fsys_ctrl(struct clk *clk, int enable)
187
{
188
	return s5p_gatectrl(EXYNOS4_CLKGATE_IP_FSYS, clk, enable);
189 190
}

K
Kukjin Kim 已提交
191
static int exynos4_clk_ip_peril_ctrl(struct clk *clk, int enable)
192
{
193
	return s5p_gatectrl(EXYNOS4_CLKGATE_IP_PERIL, clk, enable);
194 195
}

K
Kukjin Kim 已提交
196
static int exynos4_clk_ip_perir_ctrl(struct clk *clk, int enable)
J
Jongpill Lee 已提交
197
{
198
	return s5p_gatectrl(EXYNOS4_CLKGATE_IP_PERIR, clk, enable);
J
Jongpill Lee 已提交
199 200
}

201 202 203 204 205 206 207 208 209 210
static int exynos4_clk_hdmiphy_ctrl(struct clk *clk, int enable)
{
	return s5p_gatectrl(S5P_HDMI_PHY_CONTROL, clk, enable);
}

static int exynos4_clk_dac_ctrl(struct clk *clk, int enable)
{
	return s5p_gatectrl(S5P_DAC_PHY_CONTROL, clk, enable);
}

211 212
/* Core list of CMU_CPU side */

213
static struct clksrc_clk exynos4_clk_mout_apll = {
214 215 216
	.clk	= {
		.name		= "mout_apll",
	},
217
	.sources = &clk_src_apll,
218
	.reg_src = { .reg = EXYNOS4_CLKSRC_CPU, .shift = 0, .size = 1 },
219 220
};

221
static struct clksrc_clk exynos4_clk_sclk_apll = {
222 223
	.clk	= {
		.name		= "sclk_apll",
224
		.parent		= &exynos4_clk_mout_apll.clk,
225
	},
226
	.reg_div = { .reg = EXYNOS4_CLKDIV_CPU, .shift = 24, .size = 3 },
227 228
};

229
static struct clksrc_clk exynos4_clk_mout_epll = {
230 231 232
	.clk	= {
		.name		= "mout_epll",
	},
233
	.sources = &clk_src_epll,
234
	.reg_src = { .reg = EXYNOS4_CLKSRC_TOP0, .shift = 4, .size = 1 },
235 236
};

237
struct clksrc_clk exynos4_clk_mout_mpll = {
238
	.clk	= {
239 240
		.name		= "mout_mpll",
	},
241
	.sources = &clk_src_mpll,
242 243

	/* reg_src will be added in each SoCs' clock */
244 245
};

246 247 248
static struct clk *exynos4_clkset_moutcore_list[] = {
	[0] = &exynos4_clk_mout_apll.clk,
	[1] = &exynos4_clk_mout_mpll.clk,
249 250
};

251 252 253
static struct clksrc_sources exynos4_clkset_moutcore = {
	.sources	= exynos4_clkset_moutcore_list,
	.nr_sources	= ARRAY_SIZE(exynos4_clkset_moutcore_list),
254 255
};

256
static struct clksrc_clk exynos4_clk_moutcore = {
257 258 259
	.clk	= {
		.name		= "moutcore",
	},
260 261
	.sources = &exynos4_clkset_moutcore,
	.reg_src = { .reg = EXYNOS4_CLKSRC_CPU, .shift = 16, .size = 1 },
262 263
};

264
static struct clksrc_clk exynos4_clk_coreclk = {
265 266
	.clk	= {
		.name		= "core_clk",
267
		.parent		= &exynos4_clk_moutcore.clk,
268
	},
269
	.reg_div = { .reg = EXYNOS4_CLKDIV_CPU, .shift = 0, .size = 3 },
270 271
};

272
static struct clksrc_clk exynos4_clk_armclk = {
273 274
	.clk	= {
		.name		= "armclk",
275
		.parent		= &exynos4_clk_coreclk.clk,
276 277 278
	},
};

279
static struct clksrc_clk exynos4_clk_aclk_corem0 = {
280 281
	.clk	= {
		.name		= "aclk_corem0",
282
		.parent		= &exynos4_clk_coreclk.clk,
283
	},
284
	.reg_div = { .reg = EXYNOS4_CLKDIV_CPU, .shift = 4, .size = 3 },
285 286
};

287
static struct clksrc_clk exynos4_clk_aclk_cores = {
288 289
	.clk	= {
		.name		= "aclk_cores",
290
		.parent		= &exynos4_clk_coreclk.clk,
291
	},
292
	.reg_div = { .reg = EXYNOS4_CLKDIV_CPU, .shift = 4, .size = 3 },
293 294
};

295
static struct clksrc_clk exynos4_clk_aclk_corem1 = {
296 297
	.clk	= {
		.name		= "aclk_corem1",
298
		.parent		= &exynos4_clk_coreclk.clk,
299
	},
300
	.reg_div = { .reg = EXYNOS4_CLKDIV_CPU, .shift = 8, .size = 3 },
301 302
};

303
static struct clksrc_clk exynos4_clk_periphclk = {
304 305
	.clk	= {
		.name		= "periphclk",
306
		.parent		= &exynos4_clk_coreclk.clk,
307
	},
308
	.reg_div = { .reg = EXYNOS4_CLKDIV_CPU, .shift = 12, .size = 3 },
309 310 311 312
};

/* Core list of CMU_CORE side */

313 314 315
static struct clk *exynos4_clkset_corebus_list[] = {
	[0] = &exynos4_clk_mout_mpll.clk,
	[1] = &exynos4_clk_sclk_apll.clk,
316 317
};

318 319 320
struct clksrc_sources exynos4_clkset_mout_corebus = {
	.sources	= exynos4_clkset_corebus_list,
	.nr_sources	= ARRAY_SIZE(exynos4_clkset_corebus_list),
321 322
};

323
static struct clksrc_clk exynos4_clk_mout_corebus = {
324 325 326
	.clk	= {
		.name		= "mout_corebus",
	},
327 328
	.sources = &exynos4_clkset_mout_corebus,
	.reg_src = { .reg = EXYNOS4_CLKSRC_DMC, .shift = 4, .size = 1 },
329 330
};

331
static struct clksrc_clk exynos4_clk_sclk_dmc = {
332 333
	.clk	= {
		.name		= "sclk_dmc",
334
		.parent		= &exynos4_clk_mout_corebus.clk,
335
	},
336
	.reg_div = { .reg = EXYNOS4_CLKDIV_DMC0, .shift = 12, .size = 3 },
337 338
};

339
static struct clksrc_clk exynos4_clk_aclk_cored = {
340 341
	.clk	= {
		.name		= "aclk_cored",
342
		.parent		= &exynos4_clk_sclk_dmc.clk,
343
	},
344
	.reg_div = { .reg = EXYNOS4_CLKDIV_DMC0, .shift = 16, .size = 3 },
345 346
};

347
static struct clksrc_clk exynos4_clk_aclk_corep = {
348 349
	.clk	= {
		.name		= "aclk_corep",
350
		.parent		= &exynos4_clk_aclk_cored.clk,
351
	},
352
	.reg_div = { .reg = EXYNOS4_CLKDIV_DMC0, .shift = 20, .size = 3 },
353 354
};

355
static struct clksrc_clk exynos4_clk_aclk_acp = {
356 357
	.clk	= {
		.name		= "aclk_acp",
358
		.parent		= &exynos4_clk_mout_corebus.clk,
359
	},
360
	.reg_div = { .reg = EXYNOS4_CLKDIV_DMC0, .shift = 0, .size = 3 },
361 362
};

363
static struct clksrc_clk exynos4_clk_pclk_acp = {
364 365
	.clk	= {
		.name		= "pclk_acp",
366
		.parent		= &exynos4_clk_aclk_acp.clk,
367
	},
368
	.reg_div = { .reg = EXYNOS4_CLKDIV_DMC0, .shift = 4, .size = 3 },
369 370 371 372
};

/* Core list of CMU_TOP side */

373 374 375
struct clk *exynos4_clkset_aclk_top_list[] = {
	[0] = &exynos4_clk_mout_mpll.clk,
	[1] = &exynos4_clk_sclk_apll.clk,
376 377
};

378 379 380
static struct clksrc_sources exynos4_clkset_aclk = {
	.sources	= exynos4_clkset_aclk_top_list,
	.nr_sources	= ARRAY_SIZE(exynos4_clkset_aclk_top_list),
381 382
};

383
static struct clksrc_clk exynos4_clk_aclk_200 = {
384 385 386
	.clk	= {
		.name		= "aclk_200",
	},
387 388 389
	.sources = &exynos4_clkset_aclk,
	.reg_src = { .reg = EXYNOS4_CLKSRC_TOP0, .shift = 12, .size = 1 },
	.reg_div = { .reg = EXYNOS4_CLKDIV_TOP, .shift = 0, .size = 3 },
390 391
};

392
static struct clksrc_clk exynos4_clk_aclk_100 = {
393 394 395
	.clk	= {
		.name		= "aclk_100",
	},
396 397 398
	.sources = &exynos4_clkset_aclk,
	.reg_src = { .reg = EXYNOS4_CLKSRC_TOP0, .shift = 16, .size = 1 },
	.reg_div = { .reg = EXYNOS4_CLKDIV_TOP, .shift = 4, .size = 4 },
399 400
};

401
static struct clksrc_clk exynos4_clk_aclk_160 = {
402 403 404
	.clk	= {
		.name		= "aclk_160",
	},
405 406 407
	.sources = &exynos4_clkset_aclk,
	.reg_src = { .reg = EXYNOS4_CLKSRC_TOP0, .shift = 20, .size = 1 },
	.reg_div = { .reg = EXYNOS4_CLKDIV_TOP, .shift = 8, .size = 3 },
408 409
};

410
struct clksrc_clk exynos4_clk_aclk_133 = {
411 412 413
	.clk	= {
		.name		= "aclk_133",
	},
414 415 416
	.sources = &exynos4_clkset_aclk,
	.reg_src = { .reg = EXYNOS4_CLKSRC_TOP0, .shift = 24, .size = 1 },
	.reg_div = { .reg = EXYNOS4_CLKDIV_TOP, .shift = 12, .size = 3 },
417 418
};

419
static struct clk *exynos4_clkset_vpllsrc_list[] = {
420
	[0] = &clk_fin_vpll,
421
	[1] = &exynos4_clk_sclk_hdmi27m,
422 423
};

424 425 426
static struct clksrc_sources exynos4_clkset_vpllsrc = {
	.sources	= exynos4_clkset_vpllsrc_list,
	.nr_sources	= ARRAY_SIZE(exynos4_clkset_vpllsrc_list),
427 428
};

429
static struct clksrc_clk exynos4_clk_vpllsrc = {
430 431
	.clk	= {
		.name		= "vpll_src",
K
Kukjin Kim 已提交
432
		.enable		= exynos4_clksrc_mask_top_ctrl,
433
		.ctrlbit	= (1 << 0),
434
	},
435 436
	.sources = &exynos4_clkset_vpllsrc,
	.reg_src = { .reg = EXYNOS4_CLKSRC_TOP1, .shift = 0, .size = 1 },
437 438
};

439 440
static struct clk *exynos4_clkset_sclk_vpll_list[] = {
	[0] = &exynos4_clk_vpllsrc.clk,
441 442 443
	[1] = &clk_fout_vpll,
};

444 445 446
static struct clksrc_sources exynos4_clkset_sclk_vpll = {
	.sources	= exynos4_clkset_sclk_vpll_list,
	.nr_sources	= ARRAY_SIZE(exynos4_clkset_sclk_vpll_list),
447 448
};

449
static struct clksrc_clk exynos4_clk_sclk_vpll = {
450 451 452
	.clk	= {
		.name		= "sclk_vpll",
	},
453 454
	.sources = &exynos4_clkset_sclk_vpll,
	.reg_src = { .reg = EXYNOS4_CLKSRC_TOP0, .shift = 8, .size = 1 },
455 456
};

457
static struct clk exynos4_init_clocks_off[] = {
458 459
	{
		.name		= "timers",
460
		.parent		= &exynos4_clk_aclk_100.clk,
K
Kukjin Kim 已提交
461
		.enable		= exynos4_clk_ip_peril_ctrl,
462
		.ctrlbit	= (1<<24),
J
Jongpill Lee 已提交
463 464
	}, {
		.name		= "csis",
465
		.devname	= "s5p-mipi-csis.0",
K
Kukjin Kim 已提交
466
		.enable		= exynos4_clk_ip_cam_ctrl,
J
Jongpill Lee 已提交
467 468 469
		.ctrlbit	= (1 << 4),
	}, {
		.name		= "csis",
470
		.devname	= "s5p-mipi-csis.1",
K
Kukjin Kim 已提交
471
		.enable		= exynos4_clk_ip_cam_ctrl,
J
Jongpill Lee 已提交
472 473 474
		.ctrlbit	= (1 << 5),
	}, {
		.name		= "fimc",
475
		.devname	= "exynos4-fimc.0",
K
Kukjin Kim 已提交
476
		.enable		= exynos4_clk_ip_cam_ctrl,
J
Jongpill Lee 已提交
477 478 479
		.ctrlbit	= (1 << 0),
	}, {
		.name		= "fimc",
480
		.devname	= "exynos4-fimc.1",
K
Kukjin Kim 已提交
481
		.enable		= exynos4_clk_ip_cam_ctrl,
J
Jongpill Lee 已提交
482 483 484
		.ctrlbit	= (1 << 1),
	}, {
		.name		= "fimc",
485
		.devname	= "exynos4-fimc.2",
K
Kukjin Kim 已提交
486
		.enable		= exynos4_clk_ip_cam_ctrl,
J
Jongpill Lee 已提交
487 488 489
		.ctrlbit	= (1 << 2),
	}, {
		.name		= "fimc",
490
		.devname	= "exynos4-fimc.3",
K
Kukjin Kim 已提交
491
		.enable		= exynos4_clk_ip_cam_ctrl,
J
Jongpill Lee 已提交
492 493 494
		.ctrlbit	= (1 << 3),
	}, {
		.name		= "fimd",
495
		.devname	= "exynos4-fb.0",
K
Kukjin Kim 已提交
496
		.enable		= exynos4_clk_ip_lcd0_ctrl,
J
Jongpill Lee 已提交
497
		.ctrlbit	= (1 << 0),
498 499
	}, {
		.name		= "hsmmc",
500
		.devname	= "s3c-sdhci.0",
501
		.parent		= &exynos4_clk_aclk_133.clk,
K
Kukjin Kim 已提交
502
		.enable		= exynos4_clk_ip_fsys_ctrl,
503 504 505
		.ctrlbit	= (1 << 5),
	}, {
		.name		= "hsmmc",
506
		.devname	= "s3c-sdhci.1",
507
		.parent		= &exynos4_clk_aclk_133.clk,
K
Kukjin Kim 已提交
508
		.enable		= exynos4_clk_ip_fsys_ctrl,
509 510 511
		.ctrlbit	= (1 << 6),
	}, {
		.name		= "hsmmc",
512
		.devname	= "s3c-sdhci.2",
513
		.parent		= &exynos4_clk_aclk_133.clk,
K
Kukjin Kim 已提交
514
		.enable		= exynos4_clk_ip_fsys_ctrl,
515 516 517
		.ctrlbit	= (1 << 7),
	}, {
		.name		= "hsmmc",
518
		.devname	= "s3c-sdhci.3",
519
		.parent		= &exynos4_clk_aclk_133.clk,
K
Kukjin Kim 已提交
520
		.enable		= exynos4_clk_ip_fsys_ctrl,
521 522
		.ctrlbit	= (1 << 8),
	}, {
523
		.name		= "dwmmc",
524
		.parent		= &exynos4_clk_aclk_133.clk,
K
Kukjin Kim 已提交
525
		.enable		= exynos4_clk_ip_fsys_ctrl,
526
		.ctrlbit	= (1 << 9),
J
Jassi Brar 已提交
527
	}, {
528 529 530 531 532 533 534 535 536 537 538 539 540 541 542 543 544 545 546 547 548 549 550 551 552 553 554 555 556
		.name		= "dac",
		.devname	= "s5p-sdo",
		.enable		= exynos4_clk_ip_tv_ctrl,
		.ctrlbit	= (1 << 2),
	}, {
		.name		= "mixer",
		.devname	= "s5p-mixer",
		.enable		= exynos4_clk_ip_tv_ctrl,
		.ctrlbit	= (1 << 1),
	}, {
		.name		= "vp",
		.devname	= "s5p-mixer",
		.enable		= exynos4_clk_ip_tv_ctrl,
		.ctrlbit	= (1 << 0),
	}, {
		.name		= "hdmi",
		.devname	= "exynos4-hdmi",
		.enable		= exynos4_clk_ip_tv_ctrl,
		.ctrlbit	= (1 << 3),
	}, {
		.name		= "hdmiphy",
		.devname	= "exynos4-hdmi",
		.enable		= exynos4_clk_hdmiphy_ctrl,
		.ctrlbit	= (1 << 0),
	}, {
		.name		= "dacphy",
		.devname	= "s5p-sdo",
		.enable		= exynos4_clk_dac_ctrl,
		.ctrlbit	= (1 << 0),
J
Jongpill Lee 已提交
557 558
	}, {
		.name		= "adc",
K
Kukjin Kim 已提交
559
		.enable		= exynos4_clk_ip_peril_ctrl,
J
Jongpill Lee 已提交
560
		.ctrlbit	= (1 << 15),
561 562 563 564
	}, {
		.name		= "keypad",
		.enable		= exynos4_clk_ip_perir_ctrl,
		.ctrlbit	= (1 << 16),
C
Changhwan Youn 已提交
565 566
	}, {
		.name		= "rtc",
K
Kukjin Kim 已提交
567
		.enable		= exynos4_clk_ip_perir_ctrl,
C
Changhwan Youn 已提交
568
		.ctrlbit	= (1 << 15),
J
Jongpill Lee 已提交
569 570
	}, {
		.name		= "watchdog",
571
		.parent		= &exynos4_clk_aclk_100.clk,
K
Kukjin Kim 已提交
572
		.enable		= exynos4_clk_ip_perir_ctrl,
J
Jongpill Lee 已提交
573 574 575
		.ctrlbit	= (1 << 14),
	}, {
		.name		= "usbhost",
K
Kukjin Kim 已提交
576
		.enable		= exynos4_clk_ip_fsys_ctrl ,
J
Jongpill Lee 已提交
577 578 579
		.ctrlbit	= (1 << 12),
	}, {
		.name		= "otg",
K
Kukjin Kim 已提交
580
		.enable		= exynos4_clk_ip_fsys_ctrl,
J
Jongpill Lee 已提交
581 582 583
		.ctrlbit	= (1 << 13),
	}, {
		.name		= "spi",
584
		.devname	= "s3c64xx-spi.0",
K
Kukjin Kim 已提交
585
		.enable		= exynos4_clk_ip_peril_ctrl,
J
Jongpill Lee 已提交
586 587 588
		.ctrlbit	= (1 << 16),
	}, {
		.name		= "spi",
589
		.devname	= "s3c64xx-spi.1",
K
Kukjin Kim 已提交
590
		.enable		= exynos4_clk_ip_peril_ctrl,
J
Jongpill Lee 已提交
591 592 593
		.ctrlbit	= (1 << 17),
	}, {
		.name		= "spi",
594
		.devname	= "s3c64xx-spi.2",
K
Kukjin Kim 已提交
595
		.enable		= exynos4_clk_ip_peril_ctrl,
J
Jongpill Lee 已提交
596
		.ctrlbit	= (1 << 18),
J
Jassi Brar 已提交
597 598
	}, {
		.name		= "iis",
599
		.devname	= "samsung-i2s.0",
K
Kukjin Kim 已提交
600
		.enable		= exynos4_clk_ip_peril_ctrl,
J
Jassi Brar 已提交
601 602 603
		.ctrlbit	= (1 << 19),
	}, {
		.name		= "iis",
604
		.devname	= "samsung-i2s.1",
K
Kukjin Kim 已提交
605
		.enable		= exynos4_clk_ip_peril_ctrl,
J
Jassi Brar 已提交
606 607 608
		.ctrlbit	= (1 << 20),
	}, {
		.name		= "iis",
609
		.devname	= "samsung-i2s.2",
K
Kukjin Kim 已提交
610
		.enable		= exynos4_clk_ip_peril_ctrl,
J
Jassi Brar 已提交
611
		.ctrlbit	= (1 << 21),
J
Jassi Brar 已提交
612 613
	}, {
		.name		= "ac97",
614
		.devname	= "samsung-ac97",
K
Kukjin Kim 已提交
615
		.enable		= exynos4_clk_ip_peril_ctrl,
J
Jassi Brar 已提交
616
		.ctrlbit	= (1 << 27),
J
Jongpill Lee 已提交
617 618
	}, {
		.name		= "fimg2d",
K
Kukjin Kim 已提交
619
		.enable		= exynos4_clk_ip_image_ctrl,
J
Jongpill Lee 已提交
620
		.ctrlbit	= (1 << 0),
621 622 623 624 625
	}, {
		.name		= "mfc",
		.devname	= "s5p-mfc",
		.enable		= exynos4_clk_ip_mfc_ctrl,
		.ctrlbit	= (1 << 0),
J
Jongpill Lee 已提交
626 627
	}, {
		.name		= "i2c",
628
		.devname	= "s3c2440-i2c.0",
629
		.parent		= &exynos4_clk_aclk_100.clk,
K
Kukjin Kim 已提交
630
		.enable		= exynos4_clk_ip_peril_ctrl,
J
Jongpill Lee 已提交
631 632 633
		.ctrlbit	= (1 << 6),
	}, {
		.name		= "i2c",
634
		.devname	= "s3c2440-i2c.1",
635
		.parent		= &exynos4_clk_aclk_100.clk,
K
Kukjin Kim 已提交
636
		.enable		= exynos4_clk_ip_peril_ctrl,
J
Jongpill Lee 已提交
637 638 639
		.ctrlbit	= (1 << 7),
	}, {
		.name		= "i2c",
640
		.devname	= "s3c2440-i2c.2",
641
		.parent		= &exynos4_clk_aclk_100.clk,
K
Kukjin Kim 已提交
642
		.enable		= exynos4_clk_ip_peril_ctrl,
J
Jongpill Lee 已提交
643 644 645
		.ctrlbit	= (1 << 8),
	}, {
		.name		= "i2c",
646
		.devname	= "s3c2440-i2c.3",
647
		.parent		= &exynos4_clk_aclk_100.clk,
K
Kukjin Kim 已提交
648
		.enable		= exynos4_clk_ip_peril_ctrl,
J
Jongpill Lee 已提交
649 650 651
		.ctrlbit	= (1 << 9),
	}, {
		.name		= "i2c",
652
		.devname	= "s3c2440-i2c.4",
653
		.parent		= &exynos4_clk_aclk_100.clk,
K
Kukjin Kim 已提交
654
		.enable		= exynos4_clk_ip_peril_ctrl,
J
Jongpill Lee 已提交
655 656 657
		.ctrlbit	= (1 << 10),
	}, {
		.name		= "i2c",
658
		.devname	= "s3c2440-i2c.5",
659
		.parent		= &exynos4_clk_aclk_100.clk,
K
Kukjin Kim 已提交
660
		.enable		= exynos4_clk_ip_peril_ctrl,
J
Jongpill Lee 已提交
661 662 663
		.ctrlbit	= (1 << 11),
	}, {
		.name		= "i2c",
664
		.devname	= "s3c2440-i2c.6",
665
		.parent		= &exynos4_clk_aclk_100.clk,
K
Kukjin Kim 已提交
666
		.enable		= exynos4_clk_ip_peril_ctrl,
J
Jongpill Lee 已提交
667 668 669
		.ctrlbit	= (1 << 12),
	}, {
		.name		= "i2c",
670
		.devname	= "s3c2440-i2c.7",
671
		.parent		= &exynos4_clk_aclk_100.clk,
K
Kukjin Kim 已提交
672
		.enable		= exynos4_clk_ip_peril_ctrl,
J
Jongpill Lee 已提交
673
		.ctrlbit	= (1 << 13),
674 675 676
	}, {
		.name		= "i2c",
		.devname	= "s3c2440-hdmiphy-i2c",
677
		.parent		= &exynos4_clk_aclk_100.clk,
678 679
		.enable		= exynos4_clk_ip_peril_ctrl,
		.ctrlbit	= (1 << 14),
680 681 682 683 684 685 686 687 688 689 690 691 692 693 694 695 696 697 698 699 700 701 702 703 704 705 706 707 708 709 710 711 712 713 714 715 716 717 718 719 720 721 722 723 724 725 726 727 728 729 730 731 732 733 734 735 736
	}, {
		.name		= "SYSMMU_MDMA",
		.enable		= exynos4_clk_ip_image_ctrl,
		.ctrlbit	= (1 << 5),
	}, {
		.name		= "SYSMMU_FIMC0",
		.enable		= exynos4_clk_ip_cam_ctrl,
		.ctrlbit	= (1 << 7),
	}, {
		.name		= "SYSMMU_FIMC1",
		.enable		= exynos4_clk_ip_cam_ctrl,
		.ctrlbit	= (1 << 8),
	}, {
		.name		= "SYSMMU_FIMC2",
		.enable		= exynos4_clk_ip_cam_ctrl,
		.ctrlbit	= (1 << 9),
	}, {
		.name		= "SYSMMU_FIMC3",
		.enable		= exynos4_clk_ip_cam_ctrl,
		.ctrlbit	= (1 << 10),
	}, {
		.name		= "SYSMMU_JPEG",
		.enable		= exynos4_clk_ip_cam_ctrl,
		.ctrlbit	= (1 << 11),
	}, {
		.name		= "SYSMMU_FIMD0",
		.enable		= exynos4_clk_ip_lcd0_ctrl,
		.ctrlbit	= (1 << 4),
	}, {
		.name		= "SYSMMU_FIMD1",
		.enable		= exynos4_clk_ip_lcd1_ctrl,
		.ctrlbit	= (1 << 4),
	}, {
		.name		= "SYSMMU_PCIe",
		.enable		= exynos4_clk_ip_fsys_ctrl,
		.ctrlbit	= (1 << 18),
	}, {
		.name		= "SYSMMU_G2D",
		.enable		= exynos4_clk_ip_image_ctrl,
		.ctrlbit	= (1 << 3),
	}, {
		.name		= "SYSMMU_ROTATOR",
		.enable		= exynos4_clk_ip_image_ctrl,
		.ctrlbit	= (1 << 4),
	}, {
		.name		= "SYSMMU_TV",
		.enable		= exynos4_clk_ip_tv_ctrl,
		.ctrlbit	= (1 << 4),
	}, {
		.name		= "SYSMMU_MFC_L",
		.enable		= exynos4_clk_ip_mfc_ctrl,
		.ctrlbit	= (1 << 1),
	}, {
		.name		= "SYSMMU_MFC_R",
		.enable		= exynos4_clk_ip_mfc_ctrl,
		.ctrlbit	= (1 << 2),
	}
737 738
};

739
static struct clk exynos4_init_clocks_on[] = {
740 741
	{
		.name		= "uart",
742
		.devname	= "s5pv210-uart.0",
K
Kukjin Kim 已提交
743
		.enable		= exynos4_clk_ip_peril_ctrl,
744 745 746
		.ctrlbit	= (1 << 0),
	}, {
		.name		= "uart",
747
		.devname	= "s5pv210-uart.1",
K
Kukjin Kim 已提交
748
		.enable		= exynos4_clk_ip_peril_ctrl,
749 750 751
		.ctrlbit	= (1 << 1),
	}, {
		.name		= "uart",
752
		.devname	= "s5pv210-uart.2",
K
Kukjin Kim 已提交
753
		.enable		= exynos4_clk_ip_peril_ctrl,
754 755 756
		.ctrlbit	= (1 << 2),
	}, {
		.name		= "uart",
757
		.devname	= "s5pv210-uart.3",
K
Kukjin Kim 已提交
758
		.enable		= exynos4_clk_ip_peril_ctrl,
759 760 761
		.ctrlbit	= (1 << 3),
	}, {
		.name		= "uart",
762
		.devname	= "s5pv210-uart.4",
K
Kukjin Kim 已提交
763
		.enable		= exynos4_clk_ip_peril_ctrl,
764 765 766
		.ctrlbit	= (1 << 4),
	}, {
		.name		= "uart",
767
		.devname	= "s5pv210-uart.5",
K
Kukjin Kim 已提交
768
		.enable		= exynos4_clk_ip_peril_ctrl,
769 770
		.ctrlbit	= (1 << 5),
	}
771 772
};

773
static struct clk exynos4_clk_pdma0 = {
774 775 776 777 778 779
	.name		= "dma",
	.devname	= "dma-pl330.0",
	.enable		= exynos4_clk_ip_fsys_ctrl,
	.ctrlbit	= (1 << 0),
};

780
static struct clk exynos4_clk_pdma1 = {
781 782 783 784 785 786
	.name		= "dma",
	.devname	= "dma-pl330.1",
	.enable		= exynos4_clk_ip_fsys_ctrl,
	.ctrlbit	= (1 << 1),
};

787
struct clk *exynos4_clkset_group_list[] = {
788 789
	[0] = &clk_ext_xtal_mux,
	[1] = &clk_xusbxti,
790 791 792 793 794 795 796
	[2] = &exynos4_clk_sclk_hdmi27m,
	[3] = &exynos4_clk_sclk_usbphy0,
	[4] = &exynos4_clk_sclk_usbphy1,
	[5] = &exynos4_clk_sclk_hdmiphy,
	[6] = &exynos4_clk_mout_mpll.clk,
	[7] = &exynos4_clk_mout_epll.clk,
	[8] = &exynos4_clk_sclk_vpll.clk,
797 798
};

799 800 801
struct clksrc_sources exynos4_clkset_group = {
	.sources	= exynos4_clkset_group_list,
	.nr_sources	= ARRAY_SIZE(exynos4_clkset_group_list),
802 803
};

804 805 806
static struct clk *exynos4_clkset_mout_g2d0_list[] = {
	[0] = &exynos4_clk_mout_mpll.clk,
	[1] = &exynos4_clk_sclk_apll.clk,
J
Jongpill Lee 已提交
807 808
};

809 810 811
static struct clksrc_sources exynos4_clkset_mout_g2d0 = {
	.sources	= exynos4_clkset_mout_g2d0_list,
	.nr_sources	= ARRAY_SIZE(exynos4_clkset_mout_g2d0_list),
J
Jongpill Lee 已提交
812 813
};

814
static struct clksrc_clk exynos4_clk_mout_g2d0 = {
J
Jongpill Lee 已提交
815 816 817
	.clk	= {
		.name		= "mout_g2d0",
	},
818 819
	.sources = &exynos4_clkset_mout_g2d0,
	.reg_src = { .reg = EXYNOS4_CLKSRC_IMAGE, .shift = 0, .size = 1 },
J
Jongpill Lee 已提交
820 821
};

822 823 824
static struct clk *exynos4_clkset_mout_g2d1_list[] = {
	[0] = &exynos4_clk_mout_epll.clk,
	[1] = &exynos4_clk_sclk_vpll.clk,
J
Jongpill Lee 已提交
825 826
};

827 828 829
static struct clksrc_sources exynos4_clkset_mout_g2d1 = {
	.sources	= exynos4_clkset_mout_g2d1_list,
	.nr_sources	= ARRAY_SIZE(exynos4_clkset_mout_g2d1_list),
J
Jongpill Lee 已提交
830 831
};

832
static struct clksrc_clk exynos4_clk_mout_g2d1 = {
J
Jongpill Lee 已提交
833 834 835
	.clk	= {
		.name		= "mout_g2d1",
	},
836 837
	.sources = &exynos4_clkset_mout_g2d1,
	.reg_src = { .reg = EXYNOS4_CLKSRC_IMAGE, .shift = 4, .size = 1 },
J
Jongpill Lee 已提交
838 839
};

840 841 842
static struct clk *exynos4_clkset_mout_g2d_list[] = {
	[0] = &exynos4_clk_mout_g2d0.clk,
	[1] = &exynos4_clk_mout_g2d1.clk,
J
Jongpill Lee 已提交
843 844
};

845 846 847
static struct clksrc_sources exynos4_clkset_mout_g2d = {
	.sources	= exynos4_clkset_mout_g2d_list,
	.nr_sources	= ARRAY_SIZE(exynos4_clkset_mout_g2d_list),
J
Jongpill Lee 已提交
848 849
};

850 851 852
static struct clk *exynos4_clkset_mout_mfc0_list[] = {
	[0] = &exynos4_clk_mout_mpll.clk,
	[1] = &exynos4_clk_sclk_apll.clk,
853 854
};

855 856 857
static struct clksrc_sources exynos4_clkset_mout_mfc0 = {
	.sources	= exynos4_clkset_mout_mfc0_list,
	.nr_sources	= ARRAY_SIZE(exynos4_clkset_mout_mfc0_list),
858 859
};

860
static struct clksrc_clk exynos4_clk_mout_mfc0 = {
861 862 863
	.clk	= {
		.name		= "mout_mfc0",
	},
864 865
	.sources = &exynos4_clkset_mout_mfc0,
	.reg_src = { .reg = EXYNOS4_CLKSRC_MFC, .shift = 0, .size = 1 },
866 867
};

868 869 870
static struct clk *exynos4_clkset_mout_mfc1_list[] = {
	[0] = &exynos4_clk_mout_epll.clk,
	[1] = &exynos4_clk_sclk_vpll.clk,
871 872
};

873 874 875
static struct clksrc_sources exynos4_clkset_mout_mfc1 = {
	.sources	= exynos4_clkset_mout_mfc1_list,
	.nr_sources	= ARRAY_SIZE(exynos4_clkset_mout_mfc1_list),
876 877
};

878
static struct clksrc_clk exynos4_clk_mout_mfc1 = {
879 880 881
	.clk	= {
		.name		= "mout_mfc1",
	},
882 883
	.sources = &exynos4_clkset_mout_mfc1,
	.reg_src = { .reg = EXYNOS4_CLKSRC_MFC, .shift = 4, .size = 1 },
884 885
};

886 887 888
static struct clk *exynos4_clkset_mout_mfc_list[] = {
	[0] = &exynos4_clk_mout_mfc0.clk,
	[1] = &exynos4_clk_mout_mfc1.clk,
889 890
};

891 892 893
static struct clksrc_sources exynos4_clkset_mout_mfc = {
	.sources	= exynos4_clkset_mout_mfc_list,
	.nr_sources	= ARRAY_SIZE(exynos4_clkset_mout_mfc_list),
894 895
};

896 897 898
static struct clk *exynos4_clkset_sclk_dac_list[] = {
	[0] = &exynos4_clk_sclk_vpll.clk,
	[1] = &exynos4_clk_sclk_hdmiphy,
899 900
};

901 902 903
static struct clksrc_sources exynos4_clkset_sclk_dac = {
	.sources	= exynos4_clkset_sclk_dac_list,
	.nr_sources	= ARRAY_SIZE(exynos4_clkset_sclk_dac_list),
904 905
};

906
static struct clksrc_clk exynos4_clk_sclk_dac = {
907 908 909 910 911
	.clk		= {
		.name		= "sclk_dac",
		.enable		= exynos4_clksrc_mask_tv_ctrl,
		.ctrlbit	= (1 << 8),
	},
912 913
	.sources = &exynos4_clkset_sclk_dac,
	.reg_src = { .reg = EXYNOS4_CLKSRC_TV, .shift = 8, .size = 1 },
914 915
};

916
static struct clksrc_clk exynos4_clk_sclk_pixel = {
917 918
	.clk		= {
		.name		= "sclk_pixel",
919
		.parent		= &exynos4_clk_sclk_vpll.clk,
920
	},
921
	.reg_div = { .reg = EXYNOS4_CLKDIV_TV, .shift = 0, .size = 4 },
922 923
};

924 925 926
static struct clk *exynos4_clkset_sclk_hdmi_list[] = {
	[0] = &exynos4_clk_sclk_pixel.clk,
	[1] = &exynos4_clk_sclk_hdmiphy,
927 928
};

929 930 931
static struct clksrc_sources exynos4_clkset_sclk_hdmi = {
	.sources	= exynos4_clkset_sclk_hdmi_list,
	.nr_sources	= ARRAY_SIZE(exynos4_clkset_sclk_hdmi_list),
932 933
};

934
static struct clksrc_clk exynos4_clk_sclk_hdmi = {
935 936 937 938 939
	.clk		= {
		.name		= "sclk_hdmi",
		.enable		= exynos4_clksrc_mask_tv_ctrl,
		.ctrlbit	= (1 << 0),
	},
940 941
	.sources = &exynos4_clkset_sclk_hdmi,
	.reg_src = { .reg = EXYNOS4_CLKSRC_TV, .shift = 0, .size = 1 },
942 943
};

944 945 946
static struct clk *exynos4_clkset_sclk_mixer_list[] = {
	[0] = &exynos4_clk_sclk_dac.clk,
	[1] = &exynos4_clk_sclk_hdmi.clk,
947 948
};

949 950 951
static struct clksrc_sources exynos4_clkset_sclk_mixer = {
	.sources	= exynos4_clkset_sclk_mixer_list,
	.nr_sources	= ARRAY_SIZE(exynos4_clkset_sclk_mixer_list),
952 953
};

954
static struct clksrc_clk exynos4_clk_sclk_mixer = {
955
	.clk	= {
956 957 958 959
		.name		= "sclk_mixer",
		.enable		= exynos4_clksrc_mask_tv_ctrl,
		.ctrlbit	= (1 << 4),
	},
960 961
	.sources = &exynos4_clkset_sclk_mixer,
	.reg_src = { .reg = EXYNOS4_CLKSRC_TV, .shift = 4, .size = 1 },
962 963
};

964 965 966 967 968
static struct clksrc_clk *exynos4_sclk_tv[] = {
	&exynos4_clk_sclk_dac,
	&exynos4_clk_sclk_pixel,
	&exynos4_clk_sclk_hdmi,
	&exynos4_clk_sclk_mixer,
969 970
};

971
static struct clksrc_clk exynos4_clk_dout_mmc0 = {
972
	.clk	= {
973 974
		.name		= "dout_mmc0",
	},
975 976 977
	.sources = &exynos4_clkset_group,
	.reg_src = { .reg = EXYNOS4_CLKSRC_FSYS, .shift = 0, .size = 4 },
	.reg_div = { .reg = EXYNOS4_CLKDIV_FSYS1, .shift = 0, .size = 4 },
978 979
};

980
static struct clksrc_clk exynos4_clk_dout_mmc1 = {
981
	.clk	= {
982 983
		.name		= "dout_mmc1",
	},
984 985 986
	.sources = &exynos4_clkset_group,
	.reg_src = { .reg = EXYNOS4_CLKSRC_FSYS, .shift = 4, .size = 4 },
	.reg_div = { .reg = EXYNOS4_CLKDIV_FSYS1, .shift = 16, .size = 4 },
987 988
};

989
static struct clksrc_clk exynos4_clk_dout_mmc2 = {
990
	.clk	= {
991 992
		.name		= "dout_mmc2",
	},
993 994 995
	.sources = &exynos4_clkset_group,
	.reg_src = { .reg = EXYNOS4_CLKSRC_FSYS, .shift = 8, .size = 4 },
	.reg_div = { .reg = EXYNOS4_CLKDIV_FSYS2, .shift = 0, .size = 4 },
996 997
};

998
static struct clksrc_clk exynos4_clk_dout_mmc3 = {
999
	.clk	= {
1000 1001
		.name		= "dout_mmc3",
	},
1002 1003 1004
	.sources = &exynos4_clkset_group,
	.reg_src = { .reg = EXYNOS4_CLKSRC_FSYS, .shift = 12, .size = 4 },
	.reg_div = { .reg = EXYNOS4_CLKDIV_FSYS2, .shift = 16, .size = 4 },
1005 1006
};

1007
static struct clksrc_clk exynos4_clk_dout_mmc4 = {
1008 1009 1010
	.clk		= {
		.name		= "dout_mmc4",
	},
1011 1012 1013
	.sources = &exynos4_clkset_group,
	.reg_src = { .reg = EXYNOS4_CLKSRC_FSYS, .shift = 16, .size = 4 },
	.reg_div = { .reg = EXYNOS4_CLKDIV_FSYS3, .shift = 0, .size = 4 },
1014 1015
};

1016
static struct clksrc_clk exynos4_clksrcs[] = {
1017
	{
1018
		.clk	= {
1019
			.name		= "sclk_pwm",
K
Kukjin Kim 已提交
1020
			.enable		= exynos4_clksrc_mask_peril0_ctrl,
1021 1022
			.ctrlbit	= (1 << 24),
		},
1023 1024 1025
		.sources = &exynos4_clkset_group,
		.reg_src = { .reg = EXYNOS4_CLKSRC_PERIL0, .shift = 24, .size = 4 },
		.reg_div = { .reg = EXYNOS4_CLKDIV_PERIL3, .shift = 0, .size = 4 },
1026
	}, {
1027
		.clk	= {
1028
			.name		= "sclk_csis",
1029
			.devname	= "s5p-mipi-csis.0",
K
Kukjin Kim 已提交
1030
			.enable		= exynos4_clksrc_mask_cam_ctrl,
1031 1032
			.ctrlbit	= (1 << 24),
		},
1033 1034 1035
		.sources = &exynos4_clkset_group,
		.reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 24, .size = 4 },
		.reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 24, .size = 4 },
1036
	}, {
1037
		.clk	= {
1038
			.name		= "sclk_csis",
1039
			.devname	= "s5p-mipi-csis.1",
K
Kukjin Kim 已提交
1040
			.enable		= exynos4_clksrc_mask_cam_ctrl,
1041 1042
			.ctrlbit	= (1 << 28),
		},
1043 1044 1045
		.sources = &exynos4_clkset_group,
		.reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 28, .size = 4 },
		.reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 28, .size = 4 },
1046
	}, {
1047
		.clk	= {
1048
			.name		= "sclk_cam0",
K
Kukjin Kim 已提交
1049
			.enable		= exynos4_clksrc_mask_cam_ctrl,
1050 1051
			.ctrlbit	= (1 << 16),
		},
1052 1053 1054
		.sources = &exynos4_clkset_group,
		.reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 16, .size = 4 },
		.reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 16, .size = 4 },
1055
	}, {
1056
		.clk	= {
1057
			.name		= "sclk_cam1",
K
Kukjin Kim 已提交
1058
			.enable		= exynos4_clksrc_mask_cam_ctrl,
1059 1060
			.ctrlbit	= (1 << 20),
		},
1061 1062 1063
		.sources = &exynos4_clkset_group,
		.reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 20, .size = 4 },
		.reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 20, .size = 4 },
1064
	}, {
1065
		.clk	= {
1066
			.name		= "sclk_fimc",
1067
			.devname	= "exynos4-fimc.0",
K
Kukjin Kim 已提交
1068
			.enable		= exynos4_clksrc_mask_cam_ctrl,
1069 1070
			.ctrlbit	= (1 << 0),
		},
1071 1072 1073
		.sources = &exynos4_clkset_group,
		.reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 0, .size = 4 },
		.reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 0, .size = 4 },
1074
	}, {
1075
		.clk	= {
1076
			.name		= "sclk_fimc",
1077
			.devname	= "exynos4-fimc.1",
K
Kukjin Kim 已提交
1078
			.enable		= exynos4_clksrc_mask_cam_ctrl,
1079 1080
			.ctrlbit	= (1 << 4),
		},
1081 1082 1083
		.sources = &exynos4_clkset_group,
		.reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 4, .size = 4 },
		.reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 4, .size = 4 },
1084
	}, {
1085
		.clk	= {
1086
			.name		= "sclk_fimc",
1087
			.devname	= "exynos4-fimc.2",
K
Kukjin Kim 已提交
1088
			.enable		= exynos4_clksrc_mask_cam_ctrl,
1089 1090
			.ctrlbit	= (1 << 8),
		},
1091 1092 1093
		.sources = &exynos4_clkset_group,
		.reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 8, .size = 4 },
		.reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 8, .size = 4 },
1094
	}, {
1095
		.clk	= {
1096
			.name		= "sclk_fimc",
1097
			.devname	= "exynos4-fimc.3",
K
Kukjin Kim 已提交
1098
			.enable		= exynos4_clksrc_mask_cam_ctrl,
1099 1100
			.ctrlbit	= (1 << 12),
		},
1101 1102 1103
		.sources = &exynos4_clkset_group,
		.reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 12, .size = 4 },
		.reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 12, .size = 4 },
1104
	}, {
1105
		.clk	= {
1106
			.name		= "sclk_fimd",
1107
			.devname	= "exynos4-fb.0",
K
Kukjin Kim 已提交
1108
			.enable		= exynos4_clksrc_mask_lcd0_ctrl,
1109 1110
			.ctrlbit	= (1 << 0),
		},
1111 1112 1113
		.sources = &exynos4_clkset_group,
		.reg_src = { .reg = EXYNOS4_CLKSRC_LCD0, .shift = 0, .size = 4 },
		.reg_div = { .reg = EXYNOS4_CLKDIV_LCD0, .shift = 0, .size = 4 },
1114
	}, {
1115
		.clk	= {
1116 1117
			.name		= "sclk_fimg2d",
		},
1118 1119 1120
		.sources = &exynos4_clkset_mout_g2d,
		.reg_src = { .reg = EXYNOS4_CLKSRC_IMAGE, .shift = 8, .size = 1 },
		.reg_div = { .reg = EXYNOS4_CLKDIV_IMAGE, .shift = 0, .size = 4 },
1121
	}, {
1122
		.clk	= {
1123 1124 1125
			.name		= "sclk_mfc",
			.devname	= "s5p-mfc",
		},
1126 1127 1128
		.sources = &exynos4_clkset_mout_mfc,
		.reg_src = { .reg = EXYNOS4_CLKSRC_MFC, .shift = 8, .size = 1 },
		.reg_div = { .reg = EXYNOS4_CLKDIV_MFC, .shift = 0, .size = 4 },
1129
	}, {
1130
		.clk	= {
1131
			.name		= "sclk_dwmmc",
1132
			.parent		= &exynos4_clk_dout_mmc4.clk,
K
Kukjin Kim 已提交
1133
			.enable		= exynos4_clksrc_mask_fsys_ctrl,
1134 1135
			.ctrlbit	= (1 << 16),
		},
1136
		.reg_div = { .reg = EXYNOS4_CLKDIV_FSYS3, .shift = 8, .size = 8 },
1137
	}
1138 1139
};

1140
static struct clksrc_clk exynos4_clk_sclk_uart0 = {
1141 1142 1143 1144 1145 1146
	.clk	= {
		.name		= "uclk1",
		.devname	= "exynos4210-uart.0",
		.enable		= exynos4_clksrc_mask_peril0_ctrl,
		.ctrlbit	= (1 << 0),
	},
1147 1148 1149
	.sources = &exynos4_clkset_group,
	.reg_src = { .reg = EXYNOS4_CLKSRC_PERIL0, .shift = 0, .size = 4 },
	.reg_div = { .reg = EXYNOS4_CLKDIV_PERIL0, .shift = 0, .size = 4 },
1150 1151
};

1152
static struct clksrc_clk exynos4_clk_sclk_uart1 = {
1153
	.clk	= {
1154 1155 1156 1157 1158
		.name		= "uclk1",
		.devname	= "exynos4210-uart.1",
		.enable		= exynos4_clksrc_mask_peril0_ctrl,
		.ctrlbit	= (1 << 4),
	},
1159 1160 1161
	.sources = &exynos4_clkset_group,
	.reg_src = { .reg = EXYNOS4_CLKSRC_PERIL0, .shift = 4, .size = 4 },
	.reg_div = { .reg = EXYNOS4_CLKDIV_PERIL0, .shift = 4, .size = 4 },
1162 1163
};

1164
static struct clksrc_clk exynos4_clk_sclk_uart2 = {
1165
	.clk	= {
1166 1167 1168 1169 1170
		.name		= "uclk1",
		.devname	= "exynos4210-uart.2",
		.enable		= exynos4_clksrc_mask_peril0_ctrl,
		.ctrlbit	= (1 << 8),
	},
1171 1172 1173
	.sources = &exynos4_clkset_group,
	.reg_src = { .reg = EXYNOS4_CLKSRC_PERIL0, .shift = 8, .size = 4 },
	.reg_div = { .reg = EXYNOS4_CLKDIV_PERIL0, .shift = 8, .size = 4 },
1174 1175
};

1176
static struct clksrc_clk exynos4_clk_sclk_uart3 = {
1177
	.clk	= {
1178 1179 1180 1181 1182
		.name		= "uclk1",
		.devname	= "exynos4210-uart.3",
		.enable		= exynos4_clksrc_mask_peril0_ctrl,
		.ctrlbit	= (1 << 12),
	},
1183 1184 1185
	.sources = &exynos4_clkset_group,
	.reg_src = { .reg = EXYNOS4_CLKSRC_PERIL0, .shift = 12, .size = 4 },
	.reg_div = { .reg = EXYNOS4_CLKDIV_PERIL0, .shift = 12, .size = 4 },
1186 1187
};

1188
static struct clksrc_clk exynos4_clk_sclk_mmc0 = {
1189
	.clk	= {
1190 1191
		.name		= "sclk_mmc",
		.devname	= "s3c-sdhci.0",
1192
		.parent		= &exynos4_clk_dout_mmc0.clk,
1193 1194 1195
		.enable		= exynos4_clksrc_mask_fsys_ctrl,
		.ctrlbit	= (1 << 0),
	},
1196
	.reg_div = { .reg = EXYNOS4_CLKDIV_FSYS1, .shift = 8, .size = 8 },
1197 1198
};

1199
static struct clksrc_clk exynos4_clk_sclk_mmc1 = {
1200
	.clk	= {
1201 1202
		.name		= "sclk_mmc",
		.devname	= "s3c-sdhci.1",
1203
		.parent		= &exynos4_clk_dout_mmc1.clk,
1204 1205 1206
		.enable		= exynos4_clksrc_mask_fsys_ctrl,
		.ctrlbit	= (1 << 4),
	},
1207
	.reg_div = { .reg = EXYNOS4_CLKDIV_FSYS1, .shift = 24, .size = 8 },
1208 1209
};

1210
static struct clksrc_clk exynos4_clk_sclk_mmc2 = {
1211
	.clk	= {
1212 1213
		.name		= "sclk_mmc",
		.devname	= "s3c-sdhci.2",
1214
		.parent		= &exynos4_clk_dout_mmc2.clk,
1215 1216 1217
		.enable		= exynos4_clksrc_mask_fsys_ctrl,
		.ctrlbit	= (1 << 8),
	},
1218
	.reg_div = { .reg = EXYNOS4_CLKDIV_FSYS2, .shift = 8, .size = 8 },
1219 1220
};

1221
static struct clksrc_clk exynos4_clk_sclk_mmc3 = {
1222
	.clk	= {
1223 1224
		.name		= "sclk_mmc",
		.devname	= "s3c-sdhci.3",
1225
		.parent		= &exynos4_clk_dout_mmc3.clk,
1226 1227 1228
		.enable		= exynos4_clksrc_mask_fsys_ctrl,
		.ctrlbit	= (1 << 12),
	},
1229
	.reg_div = { .reg = EXYNOS4_CLKDIV_FSYS2, .shift = 24, .size = 8 },
1230 1231
};

1232
static struct clksrc_clk exynos4_clk_sclk_spi0 = {
1233
	.clk	= {
1234
		.name		= "sclk_spi",
1235
		.devname	= "s3c64xx-spi.0",
1236
		.enable		= exynos4_clksrc_mask_peril1_ctrl,
1237
		.ctrlbit	= (1 << 16),
1238
	},
1239 1240 1241
	.sources = &exynos4_clkset_group,
	.reg_src = { .reg = EXYNOS4_CLKSRC_PERIL1, .shift = 16, .size = 4 },
	.reg_div = { .reg = EXYNOS4_CLKDIV_PERIL1, .shift = 0, .size = 4 },
1242 1243
};

1244
static struct clksrc_clk exynos4_clk_sclk_spi1 = {
1245
	.clk	= {
1246
		.name		= "sclk_spi",
1247
		.devname	= "s3c64xx-spi.1",
1248
		.enable		= exynos4_clksrc_mask_peril1_ctrl,
1249
		.ctrlbit	= (1 << 20),
1250
	},
1251 1252 1253
	.sources = &exynos4_clkset_group,
	.reg_src = { .reg = EXYNOS4_CLKSRC_PERIL1, .shift = 20, .size = 4 },
	.reg_div = { .reg = EXYNOS4_CLKDIV_PERIL1, .shift = 16, .size = 4 },
1254 1255
};

1256
static struct clksrc_clk exynos4_clk_sclk_spi2 = {
1257
	.clk	= {
1258
		.name		= "sclk_spi",
1259
		.devname	= "s3c64xx-spi.2",
1260
		.enable		= exynos4_clksrc_mask_peril1_ctrl,
1261
		.ctrlbit	= (1 << 24),
1262
	},
1263 1264 1265
	.sources = &exynos4_clkset_group,
	.reg_src = { .reg = EXYNOS4_CLKSRC_PERIL1, .shift = 24, .size = 4 },
	.reg_div = { .reg = EXYNOS4_CLKDIV_PERIL2, .shift = 0, .size = 4 },
1266 1267
};

1268
/* Clock initialization code */
1269 1270 1271 1272 1273 1274 1275 1276 1277 1278 1279 1280 1281 1282 1283 1284 1285 1286 1287 1288 1289 1290 1291 1292 1293 1294 1295 1296 1297 1298 1299 1300 1301 1302 1303 1304 1305 1306 1307 1308 1309 1310 1311 1312 1313 1314 1315 1316 1317 1318
static struct clksrc_clk *exynos4_sysclks[] = {
	&exynos4_clk_mout_apll,
	&exynos4_clk_sclk_apll,
	&exynos4_clk_mout_epll,
	&exynos4_clk_mout_mpll,
	&exynos4_clk_moutcore,
	&exynos4_clk_coreclk,
	&exynos4_clk_armclk,
	&exynos4_clk_aclk_corem0,
	&exynos4_clk_aclk_cores,
	&exynos4_clk_aclk_corem1,
	&exynos4_clk_periphclk,
	&exynos4_clk_mout_corebus,
	&exynos4_clk_sclk_dmc,
	&exynos4_clk_aclk_cored,
	&exynos4_clk_aclk_corep,
	&exynos4_clk_aclk_acp,
	&exynos4_clk_pclk_acp,
	&exynos4_clk_vpllsrc,
	&exynos4_clk_sclk_vpll,
	&exynos4_clk_aclk_200,
	&exynos4_clk_aclk_100,
	&exynos4_clk_aclk_160,
	&exynos4_clk_aclk_133,
	&exynos4_clk_dout_mmc0,
	&exynos4_clk_dout_mmc1,
	&exynos4_clk_dout_mmc2,
	&exynos4_clk_dout_mmc3,
	&exynos4_clk_dout_mmc4,
	&exynos4_clk_mout_mfc0,
	&exynos4_clk_mout_mfc1,
};

static struct clk *exynos4_clk_cdev[] = {
	&exynos4_clk_pdma0,
	&exynos4_clk_pdma1,
};

static struct clksrc_clk *exynos4_clksrc_cdev[] = {
	&exynos4_clk_sclk_uart0,
	&exynos4_clk_sclk_uart1,
	&exynos4_clk_sclk_uart2,
	&exynos4_clk_sclk_uart3,
	&exynos4_clk_sclk_mmc0,
	&exynos4_clk_sclk_mmc1,
	&exynos4_clk_sclk_mmc2,
	&exynos4_clk_sclk_mmc3,
	&exynos4_clk_sclk_spi0,
	&exynos4_clk_sclk_spi1,
	&exynos4_clk_sclk_spi2,
1319

1320 1321 1322
};

static struct clk_lookup exynos4_clk_lookup[] = {
1323 1324 1325 1326 1327 1328 1329 1330 1331 1332 1333 1334 1335
	CLKDEV_INIT("exynos4210-uart.0", "clk_uart_baud0", &exynos4_clk_sclk_uart0.clk),
	CLKDEV_INIT("exynos4210-uart.1", "clk_uart_baud0", &exynos4_clk_sclk_uart1.clk),
	CLKDEV_INIT("exynos4210-uart.2", "clk_uart_baud0", &exynos4_clk_sclk_uart2.clk),
	CLKDEV_INIT("exynos4210-uart.3", "clk_uart_baud0", &exynos4_clk_sclk_uart3.clk),
	CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &exynos4_clk_sclk_mmc0.clk),
	CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &exynos4_clk_sclk_mmc1.clk),
	CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &exynos4_clk_sclk_mmc2.clk),
	CLKDEV_INIT("s3c-sdhci.3", "mmc_busclk.2", &exynos4_clk_sclk_mmc3.clk),
	CLKDEV_INIT("dma-pl330.0", "apb_pclk", &exynos4_clk_pdma0),
	CLKDEV_INIT("dma-pl330.1", "apb_pclk", &exynos4_clk_pdma1),
	CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk0", &exynos4_clk_sclk_spi0.clk),
	CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk0", &exynos4_clk_sclk_spi1.clk),
	CLKDEV_INIT("s3c64xx-spi.2", "spi_busclk0", &exynos4_clk_sclk_spi2.clk),
1336 1337
};

1338 1339
static int xtal_rate;

K
Kukjin Kim 已提交
1340
static unsigned long exynos4_fout_apll_get_rate(struct clk *clk)
1341
{
1342
	if (soc_is_exynos4210())
1343
		return s5p_get_pll45xx(xtal_rate, __raw_readl(EXYNOS4_APLL_CON0),
1344
					pll_4508);
1345
	else if (soc_is_exynos4212() || soc_is_exynos4412())
1346
		return s5p_get_pll35xx(xtal_rate, __raw_readl(EXYNOS4_APLL_CON0));
1347 1348
	else
		return 0;
1349 1350
}

K
Kukjin Kim 已提交
1351 1352
static struct clk_ops exynos4_fout_apll_ops = {
	.get_rate = exynos4_fout_apll_get_rate,
1353 1354
};

1355
static u32 exynos4_vpll_div[][8] = {
1356 1357 1358 1359 1360 1361 1362 1363 1364 1365 1366 1367 1368 1369 1370 1371 1372 1373
	{  54000000, 3, 53, 3, 1024, 0, 17, 0 },
	{ 108000000, 3, 53, 2, 1024, 0, 17, 0 },
};

static unsigned long exynos4_vpll_get_rate(struct clk *clk)
{
	return clk->rate;
}

static int exynos4_vpll_set_rate(struct clk *clk, unsigned long rate)
{
	unsigned int vpll_con0, vpll_con1 = 0;
	unsigned int i;

	/* Return if nothing changed */
	if (clk->rate == rate)
		return 0;

1374
	vpll_con0 = __raw_readl(EXYNOS4_VPLL_CON0);
1375 1376 1377 1378 1379
	vpll_con0 &= ~(0x1 << 27 |					\
			PLL90XX_MDIV_MASK << PLL46XX_MDIV_SHIFT |	\
			PLL90XX_PDIV_MASK << PLL46XX_PDIV_SHIFT |	\
			PLL90XX_SDIV_MASK << PLL46XX_SDIV_SHIFT);

1380
	vpll_con1 = __raw_readl(EXYNOS4_VPLL_CON1);
1381 1382 1383 1384
	vpll_con1 &= ~(PLL46XX_MRR_MASK << PLL46XX_MRR_SHIFT |	\
			PLL46XX_MFR_MASK << PLL46XX_MFR_SHIFT |	\
			PLL4650C_KDIV_MASK << PLL46XX_KDIV_SHIFT);

1385 1386 1387 1388 1389 1390 1391 1392 1393
	for (i = 0; i < ARRAY_SIZE(exynos4_vpll_div); i++) {
		if (exynos4_vpll_div[i][0] == rate) {
			vpll_con0 |= exynos4_vpll_div[i][1] << PLL46XX_PDIV_SHIFT;
			vpll_con0 |= exynos4_vpll_div[i][2] << PLL46XX_MDIV_SHIFT;
			vpll_con0 |= exynos4_vpll_div[i][3] << PLL46XX_SDIV_SHIFT;
			vpll_con1 |= exynos4_vpll_div[i][4] << PLL46XX_KDIV_SHIFT;
			vpll_con1 |= exynos4_vpll_div[i][5] << PLL46XX_MFR_SHIFT;
			vpll_con1 |= exynos4_vpll_div[i][6] << PLL46XX_MRR_SHIFT;
			vpll_con0 |= exynos4_vpll_div[i][7] << 27;
1394 1395 1396 1397
			break;
		}
	}

1398
	if (i == ARRAY_SIZE(exynos4_vpll_div)) {
1399 1400 1401 1402 1403
		printk(KERN_ERR "%s: Invalid Clock VPLL Frequency\n",
				__func__);
		return -EINVAL;
	}

1404 1405
	__raw_writel(vpll_con0, EXYNOS4_VPLL_CON0);
	__raw_writel(vpll_con1, EXYNOS4_VPLL_CON1);
1406 1407

	/* Wait for VPLL lock */
1408
	while (!(__raw_readl(EXYNOS4_VPLL_CON0) & (1 << PLL46XX_LOCKED_SHIFT)))
1409 1410 1411 1412 1413 1414 1415 1416 1417 1418 1419
		continue;

	clk->rate = rate;
	return 0;
}

static struct clk_ops exynos4_vpll_ops = {
	.get_rate = exynos4_vpll_get_rate,
	.set_rate = exynos4_vpll_set_rate,
};

K
Kukjin Kim 已提交
1420
void __init_or_cpufreq exynos4_setup_clocks(void)
1421 1422
{
	struct clk *xtal_clk;
1423 1424 1425 1426
	unsigned long apll = 0;
	unsigned long mpll = 0;
	unsigned long epll = 0;
	unsigned long vpll = 0;
1427 1428 1429 1430
	unsigned long vpllsrc;
	unsigned long xtal;
	unsigned long armclk;
	unsigned long sclk_dmc;
1431 1432 1433 1434
	unsigned long aclk_200;
	unsigned long aclk_100;
	unsigned long aclk_160;
	unsigned long aclk_133;
1435 1436 1437 1438 1439 1440 1441 1442
	unsigned int ptr;

	printk(KERN_DEBUG "%s: registering clocks\n", __func__);

	xtal_clk = clk_get(NULL, "xtal");
	BUG_ON(IS_ERR(xtal_clk));

	xtal = clk_get_rate(xtal_clk);
1443 1444 1445

	xtal_rate = xtal;

1446 1447 1448 1449
	clk_put(xtal_clk);

	printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal);

1450
	if (soc_is_exynos4210()) {
1451
		apll = s5p_get_pll45xx(xtal, __raw_readl(EXYNOS4_APLL_CON0),
1452
					pll_4508);
1453
		mpll = s5p_get_pll45xx(xtal, __raw_readl(EXYNOS4_MPLL_CON0),
1454
					pll_4508);
1455 1456
		epll = s5p_get_pll46xx(xtal, __raw_readl(EXYNOS4_EPLL_CON0),
					__raw_readl(EXYNOS4_EPLL_CON1), pll_4600);
1457

1458 1459 1460
		vpllsrc = clk_get_rate(&exynos4_clk_vpllsrc.clk);
		vpll = s5p_get_pll46xx(vpllsrc, __raw_readl(EXYNOS4_VPLL_CON0),
					__raw_readl(EXYNOS4_VPLL_CON1), pll_4650c);
1461
	} else if (soc_is_exynos4212() || soc_is_exynos4412()) {
1462 1463 1464 1465 1466 1467 1468 1469
		apll = s5p_get_pll35xx(xtal, __raw_readl(EXYNOS4_APLL_CON0));
		mpll = s5p_get_pll35xx(xtal, __raw_readl(EXYNOS4_MPLL_CON0));
		epll = s5p_get_pll36xx(xtal, __raw_readl(EXYNOS4_EPLL_CON0),
					__raw_readl(EXYNOS4_EPLL_CON1));

		vpllsrc = clk_get_rate(&exynos4_clk_vpllsrc.clk);
		vpll = s5p_get_pll36xx(vpllsrc, __raw_readl(EXYNOS4_VPLL_CON0),
					__raw_readl(EXYNOS4_VPLL_CON1));
1470 1471 1472
	} else {
		/* nothing */
	}
1473

K
Kukjin Kim 已提交
1474
	clk_fout_apll.ops = &exynos4_fout_apll_ops;
1475 1476
	clk_fout_mpll.rate = mpll;
	clk_fout_epll.rate = epll;
1477
	clk_fout_vpll.ops = &exynos4_vpll_ops;
1478 1479
	clk_fout_vpll.rate = vpll;

K
Kukjin Kim 已提交
1480
	printk(KERN_INFO "EXYNOS4: PLL settings, A=%ld, M=%ld, E=%ld V=%ld",
1481 1482
			apll, mpll, epll, vpll);

1483 1484
	armclk = clk_get_rate(&exynos4_clk_armclk.clk);
	sclk_dmc = clk_get_rate(&exynos4_clk_sclk_dmc.clk);
K
Kukjin Kim 已提交
1485

1486 1487 1488 1489
	aclk_200 = clk_get_rate(&exynos4_clk_aclk_200.clk);
	aclk_100 = clk_get_rate(&exynos4_clk_aclk_100.clk);
	aclk_160 = clk_get_rate(&exynos4_clk_aclk_160.clk);
	aclk_133 = clk_get_rate(&exynos4_clk_aclk_133.clk);
1490

K
Kukjin Kim 已提交
1491
	printk(KERN_INFO "EXYNOS4: ARMCLK=%ld, DMC=%ld, ACLK200=%ld\n"
1492 1493 1494
			 "ACLK100=%ld, ACLK160=%ld, ACLK133=%ld\n",
			armclk, sclk_dmc, aclk_200,
			aclk_100, aclk_160, aclk_133);
1495 1496 1497

	clk_f.rate = armclk;
	clk_h.rate = sclk_dmc;
1498
	clk_p.rate = aclk_100;
1499

1500 1501
	for (ptr = 0; ptr < ARRAY_SIZE(exynos4_clksrcs); ptr++)
		s3c_set_clksrc(&exynos4_clksrcs[ptr], true);
1502 1503
}

1504 1505 1506 1507 1508
static struct clk *exynos4_clks[] __initdata = {
	&exynos4_clk_sclk_hdmi27m,
	&exynos4_clk_sclk_hdmiphy,
	&exynos4_clk_sclk_usbphy0,
	&exynos4_clk_sclk_usbphy1,
1509 1510
};

1511 1512 1513 1514 1515 1516 1517 1518 1519 1520 1521 1522 1523 1524 1525 1526 1527
#ifdef CONFIG_PM_SLEEP
static int exynos4_clock_suspend(void)
{
	s3c_pm_do_save(exynos4_clock_save, ARRAY_SIZE(exynos4_clock_save));
	return 0;
}

static void exynos4_clock_resume(void)
{
	s3c_pm_do_restore_core(exynos4_clock_save, ARRAY_SIZE(exynos4_clock_save));
}

#else
#define exynos4_clock_suspend NULL
#define exynos4_clock_resume NULL
#endif

1528
static struct syscore_ops exynos4_clock_syscore_ops = {
1529 1530 1531 1532
	.suspend	= exynos4_clock_suspend,
	.resume		= exynos4_clock_resume,
};

K
Kukjin Kim 已提交
1533
void __init exynos4_register_clocks(void)
1534 1535 1536
{
	int ptr;

1537
	s3c24xx_register_clocks(exynos4_clks, ARRAY_SIZE(exynos4_clks));
1538

1539 1540
	for (ptr = 0; ptr < ARRAY_SIZE(exynos4_sysclks); ptr++)
		s3c_register_clksrc(exynos4_sysclks[ptr], 1);
1541

1542 1543
	for (ptr = 0; ptr < ARRAY_SIZE(exynos4_sclk_tv); ptr++)
		s3c_register_clksrc(exynos4_sclk_tv[ptr], 1);
1544

1545 1546
	for (ptr = 0; ptr < ARRAY_SIZE(exynos4_clksrc_cdev); ptr++)
		s3c_register_clksrc(exynos4_clksrc_cdev[ptr], 1);
1547

1548 1549
	s3c_register_clksrc(exynos4_clksrcs, ARRAY_SIZE(exynos4_clksrcs));
	s3c_register_clocks(exynos4_init_clocks_on, ARRAY_SIZE(exynos4_init_clocks_on));
1550

1551 1552 1553
	s3c24xx_register_clocks(exynos4_clk_cdev, ARRAY_SIZE(exynos4_clk_cdev));
	for (ptr = 0; ptr < ARRAY_SIZE(exynos4_clk_cdev); ptr++)
		s3c_disable_clocks(exynos4_clk_cdev[ptr], 1);
1554

1555 1556
	s3c_register_clocks(exynos4_init_clocks_off, ARRAY_SIZE(exynos4_init_clocks_off));
	s3c_disable_clocks(exynos4_init_clocks_off, ARRAY_SIZE(exynos4_init_clocks_off));
1557
	clkdev_add_table(exynos4_clk_lookup, ARRAY_SIZE(exynos4_clk_lookup));
1558

1559
	register_syscore_ops(&exynos4_clock_syscore_ops);
1560 1561
	s3c24xx_register_clock(&dummy_apb_pclk);

1562 1563
	s3c_pwmclk_init();
}