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“cdec5634492ed088e8c0792aafbbc43de91f6692”上不存在“paddle/operators/compare_op.cu”
提交 a855039e 编写于 作者: K Kukjin Kim
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ARM: EXYNOS: change the prefix S5P_ to EXYNOS4_ for clock 

This patch changes prefix of the clk register from S5P_ to
EXYNOS4_ for new EXYNOS SoCs such as EXYNOS5 and adds prefix
exynos4_ on clk declarations.
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>
上级 b1d6c5b2
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Showing with 766 addition and 762 deletion
arch/arm/mach-exynos/clock-exynos4.h
浏览文件 @ a855039e
/* /*
* * Copyright (c) 2011-2012 Samsung Electronics Co., Ltd.
* Copyright (c) 2011 Samsung Electronics Co., Ltd.
* http://www.samsung.com * http://www.samsung.com
* *
* Header file for exynos4 clock support * Header file for exynos4 clock support
...@@ -15,14 +14,14 @@ ...@@ -15,14 +14,14 @@
#include <linux/clk.h> #include <linux/clk.h>
extern struct clksrc_clk clk_mout_mpll; extern struct clksrc_clk exynos4_clk_aclk_133;
extern struct clksrc_clk clk_aclk_133; extern struct clksrc_clk exynos4_clk_mout_mpll;
extern struct clksrc_sources clkset_mout_corebus; extern struct clksrc_sources exynos4_clkset_mout_corebus;
extern struct clksrc_sources clkset_group; extern struct clksrc_sources exynos4_clkset_group;
extern struct clk *clkset_aclk_top_list[]; extern struct clk *exynos4_clkset_aclk_top_list[];
extern struct clk *clkset_group_list[]; extern struct clk *exynos4_clkset_group_list[];
extern int exynos4_clksrc_mask_fsys_ctrl(struct clk *clk, int enable); extern int exynos4_clksrc_mask_fsys_ctrl(struct clk *clk, int enable);
extern int exynos4_clk_ip_fsys_ctrl(struct clk *clk, int enable); extern int exynos4_clk_ip_fsys_ctrl(struct clk *clk, int enable);
......
arch/arm/mach-exynos/clock-exynos4210.c
浏览文件 @ a855039e
/* /*
* linux/arch/arm/mach-exynos4/clock-exynos4210.c * Copyright (c) 2011-2012 Samsung Electronics Co., Ltd.
*
* Copyright (c) 2011 Samsung Electronics Co., Ltd.
* http://www.samsung.com * http://www.samsung.com
* *
* EXYNOS4210 - Clock support * EXYNOS4210 - Clock support
...@@ -34,14 +32,14 @@ ...@@ -34,14 +32,14 @@
#ifdef CONFIG_PM_SLEEP #ifdef CONFIG_PM_SLEEP
static struct sleep_save exynos4210_clock_save[] = { static struct sleep_save exynos4210_clock_save[] = {
SAVE_ITEM(S5P_CLKSRC_IMAGE), SAVE_ITEM(EXYNOS4_CLKSRC_IMAGE),
SAVE_ITEM(S5P_CLKSRC_LCD1), SAVE_ITEM(EXYNOS4_CLKDIV_IMAGE),
SAVE_ITEM(S5P_CLKDIV_IMAGE), SAVE_ITEM(EXYNOS4210_CLKSRC_LCD1),
SAVE_ITEM(S5P_CLKDIV_LCD1), SAVE_ITEM(EXYNOS4210_CLKDIV_LCD1),
SAVE_ITEM(S5P_CLKSRC_MASK_LCD1), SAVE_ITEM(EXYNOS4210_CLKSRC_MASK_LCD1),
SAVE_ITEM(S5P_CLKGATE_IP_IMAGE_4210), SAVE_ITEM(EXYNOS4210_CLKGATE_IP_IMAGE),
SAVE_ITEM(S5P_CLKGATE_IP_LCD1), SAVE_ITEM(EXYNOS4210_CLKGATE_IP_LCD1),
SAVE_ITEM(S5P_CLKGATE_IP_PERIR_4210), SAVE_ITEM(EXYNOS4210_CLKGATE_IP_PERIR),
}; };
#endif #endif
...@@ -51,7 +49,7 @@ static struct clksrc_clk *sysclks[] = { ...@@ -51,7 +49,7 @@ static struct clksrc_clk *sysclks[] = {
static int exynos4_clksrc_mask_lcd1_ctrl(struct clk *clk, int enable) static int exynos4_clksrc_mask_lcd1_ctrl(struct clk *clk, int enable)
{ {
return s5p_gatectrl(S5P_CLKSRC_MASK_LCD1, clk, enable); return s5p_gatectrl(EXYNOS4210_CLKSRC_MASK_LCD1, clk, enable);
} }
static struct clksrc_clk clksrcs[] = { static struct clksrc_clk clksrcs[] = {
...@@ -62,9 +60,9 @@ static struct clksrc_clk clksrcs[] = { ...@@ -62,9 +60,9 @@ static struct clksrc_clk clksrcs[] = {
.enable = exynos4_clksrc_mask_fsys_ctrl, .enable = exynos4_clksrc_mask_fsys_ctrl,
.ctrlbit = (1 << 24), .ctrlbit = (1 << 24),
}, },
.sources = &clkset_mout_corebus, .sources = &exynos4_clkset_mout_corebus,
.reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 24, .size = 1 }, .reg_src = { .reg = EXYNOS4_CLKSRC_FSYS, .shift = 24, .size = 1 },
.reg_div = { .reg = S5P_CLKDIV_FSYS0, .shift = 20, .size = 4 }, .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS0, .shift = 20, .size = 4 },
}, { }, {
.clk = { .clk = {
.name = "sclk_fimd", .name = "sclk_fimd",
...@@ -72,9 +70,9 @@ static struct clksrc_clk clksrcs[] = { ...@@ -72,9 +70,9 @@ static struct clksrc_clk clksrcs[] = {
.enable = exynos4_clksrc_mask_lcd1_ctrl, .enable = exynos4_clksrc_mask_lcd1_ctrl,
.ctrlbit = (1 << 0), .ctrlbit = (1 << 0),
}, },
.sources = &clkset_group, .sources = &exynos4_clkset_group,
.reg_src = { .reg = S5P_CLKSRC_LCD1, .shift = 0, .size = 4 }, .reg_src = { .reg = EXYNOS4210_CLKSRC_LCD1, .shift = 0, .size = 4 },
.reg_div = { .reg = S5P_CLKDIV_LCD1, .shift = 0, .size = 4 }, .reg_div = { .reg = EXYNOS4210_CLKDIV_LCD1, .shift = 0, .size = 4 },
}, },
}; };
...@@ -82,13 +80,13 @@ static struct clk init_clocks_off[] = { ...@@ -82,13 +80,13 @@ static struct clk init_clocks_off[] = {
{ {
.name = "sataphy", .name = "sataphy",
.id = -1, .id = -1,
.parent = &clk_aclk_133.clk, .parent = &exynos4_clk_aclk_133.clk,
.enable = exynos4_clk_ip_fsys_ctrl, .enable = exynos4_clk_ip_fsys_ctrl,
.ctrlbit = (1 << 3), .ctrlbit = (1 << 3),
}, { }, {
.name = "sata", .name = "sata",
.id = -1, .id = -1,
.parent = &clk_aclk_133.clk, .parent = &exynos4_clk_aclk_133.clk,
.enable = exynos4_clk_ip_fsys_ctrl, .enable = exynos4_clk_ip_fsys_ctrl,
.ctrlbit = (1 << 10), .ctrlbit = (1 << 10),
}, { }, {
...@@ -126,9 +124,9 @@ void __init exynos4210_register_clocks(void) ...@@ -126,9 +124,9 @@ void __init exynos4210_register_clocks(void)
{ {
int ptr; int ptr;
clk_mout_mpll.reg_src.reg = S5P_CLKSRC_CPU; exynos4_clk_mout_mpll.reg_src.reg = EXYNOS4_CLKSRC_CPU;
clk_mout_mpll.reg_src.shift = 8; exynos4_clk_mout_mpll.reg_src.shift = 8;
clk_mout_mpll.reg_src.size = 1; exynos4_clk_mout_mpll.reg_src.size = 1;
for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++) for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
s3c_register_clksrc(sysclks[ptr], 1); s3c_register_clksrc(sysclks[ptr], 1);
......
arch/arm/mach-exynos/clock-exynos4212.c
浏览文件 @ a855039e
/* /*
* linux/arch/arm/mach-exynos4/clock-exynos4212.c * Copyright (c) 2011-2012 Samsung Electronics Co., Ltd.
*
* Copyright (c) 2011 Samsung Electronics Co., Ltd.
* http://www.samsung.com * http://www.samsung.com
* *
* EXYNOS4212 - Clock support * EXYNOS4212 - Clock support
...@@ -34,16 +32,16 @@ ...@@ -34,16 +32,16 @@
#ifdef CONFIG_PM_SLEEP #ifdef CONFIG_PM_SLEEP
static struct sleep_save exynos4212_clock_save[] = { static struct sleep_save exynos4212_clock_save[] = {
SAVE_ITEM(S5P_CLKSRC_IMAGE), SAVE_ITEM(EXYNOS4_CLKSRC_IMAGE),
SAVE_ITEM(S5P_CLKDIV_IMAGE), SAVE_ITEM(EXYNOS4_CLKDIV_IMAGE),
SAVE_ITEM(S5P_CLKGATE_IP_IMAGE_4212), SAVE_ITEM(EXYNOS4212_CLKGATE_IP_IMAGE),
SAVE_ITEM(S5P_CLKGATE_IP_PERIR_4212), SAVE_ITEM(EXYNOS4212_CLKGATE_IP_PERIR),
}; };
#endif #endif
static struct clk *clk_src_mpll_user_list[] = { static struct clk *clk_src_mpll_user_list[] = {
[0] = &clk_fin_mpll, [0] = &clk_fin_mpll,
[1] = &clk_mout_mpll.clk, [1] = &exynos4_clk_mout_mpll.clk,
}; };
static struct clksrc_sources clk_src_mpll_user = { static struct clksrc_sources clk_src_mpll_user = {
...@@ -56,7 +54,7 @@ static struct clksrc_clk clk_mout_mpll_user = { ...@@ -56,7 +54,7 @@ static struct clksrc_clk clk_mout_mpll_user = {
.name = "mout_mpll_user", .name = "mout_mpll_user",
}, },
.sources = &clk_src_mpll_user, .sources = &clk_src_mpll_user,
.reg_src = { .reg = S5P_CLKSRC_CPU, .shift = 24, .size = 1 }, .reg_src = { .reg = EXYNOS4_CLKSRC_CPU, .shift = 24, .size = 1 },
}; };
static struct clksrc_clk *sysclks[] = { static struct clksrc_clk *sysclks[] = {
...@@ -99,15 +97,15 @@ void __init exynos4212_register_clocks(void) ...@@ -99,15 +97,15 @@ void __init exynos4212_register_clocks(void)
int ptr; int ptr;
/* usbphy1 is removed */ /* usbphy1 is removed */
clkset_group_list[4] = NULL; exynos4_clkset_group_list[4] = NULL;
/* mout_mpll_user is used */ /* mout_mpll_user is used */
clkset_group_list[6] = &clk_mout_mpll_user.clk; exynos4_clkset_group_list[6] = &clk_mout_mpll_user.clk;
clkset_aclk_top_list[0] = &clk_mout_mpll_user.clk; exynos4_clkset_aclk_top_list[0] = &clk_mout_mpll_user.clk;
clk_mout_mpll.reg_src.reg = S5P_CLKSRC_DMC; exynos4_clk_mout_mpll.reg_src.reg = EXYNOS4_CLKSRC_DMC;
clk_mout_mpll.reg_src.shift = 12; exynos4_clk_mout_mpll.reg_src.shift = 12;
clk_mout_mpll.reg_src.size = 1; exynos4_clk_mout_mpll.reg_src.size = 1;
for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++) for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
s3c_register_clksrc(sysclks[ptr], 1); s3c_register_clksrc(sysclks[ptr], 1);
......
arch/arm/mach-exynos/common.h
浏览文件 @ a855039e
...@@ -15,12 +15,21 @@ ...@@ -15,12 +15,21 @@
void exynos_init_io(struct map_desc *mach_desc, int size); void exynos_init_io(struct map_desc *mach_desc, int size);
void exynos4_init_irq(void); void exynos4_init_irq(void);
#ifdef CONFIG_ARCH_EXYNOS4
void exynos4_register_clocks(void); void exynos4_register_clocks(void);
void exynos4_setup_clocks(void); void exynos4_setup_clocks(void);
void exynos4210_register_clocks(void); void exynos4210_register_clocks(void);
void exynos4212_register_clocks(void); void exynos4212_register_clocks(void);
#else
#define exynos4_register_clocks()
#define exynos4_setup_clocks()
#define exynos4210_register_clocks()
#define exynos4212_register_clocks()
#endif
void exynos4_restart(char mode, const char *cmd); void exynos4_restart(char mode, const char *cmd);
extern struct sys_timer exynos4_timer; extern struct sys_timer exynos4_timer;
......
arch/arm/mach-exynos/include/mach/regs-clock.h
浏览文件 @ a855039e
...@@ -16,195 +16,195 @@ ...@@ -16,195 +16,195 @@
#include <plat/cpu.h> #include <plat/cpu.h>
#include <mach/map.h> #include <mach/map.h>
#define S5P_CLKREG(x) (S5P_VA_CMU + (x)) #define EXYNOS_CLKREG(x) (S5P_VA_CMU + (x))
#define S5P_CLKDIV_LEFTBUS S5P_CLKREG(0x04500) #define EXYNOS4_CLKDIV_LEFTBUS EXYNOS_CLKREG(0x04500)
#define S5P_CLKDIV_STAT_LEFTBUS S5P_CLKREG(0x04600) #define EXYNOS4_CLKDIV_STAT_LEFTBUS EXYNOS_CLKREG(0x04600)
#define S5P_CLKGATE_IP_LEFTBUS S5P_CLKREG(0x04800) #define EXYNOS4_CLKGATE_IP_LEFTBUS EXYNOS_CLKREG(0x04800)
#define S5P_CLKDIV_RIGHTBUS S5P_CLKREG(0x08500) #define EXYNOS4_CLKDIV_RIGHTBUS EXYNOS_CLKREG(0x08500)
#define S5P_CLKDIV_STAT_RIGHTBUS S5P_CLKREG(0x08600) #define EXYNOS4_CLKDIV_STAT_RIGHTBUS EXYNOS_CLKREG(0x08600)
#define S5P_CLKGATE_IP_RIGHTBUS S5P_CLKREG(0x08800) #define EXYNOS4_CLKGATE_IP_RIGHTBUS EXYNOS_CLKREG(0x08800)
#define S5P_EPLL_LOCK S5P_CLKREG(0x0C010) #define EXYNOS4_EPLL_LOCK EXYNOS_CLKREG(0x0C010)
#define S5P_VPLL_LOCK S5P_CLKREG(0x0C020) #define EXYNOS4_VPLL_LOCK EXYNOS_CLKREG(0x0C020)
#define S5P_EPLL_CON0 S5P_CLKREG(0x0C110) #define EXYNOS4_EPLL_CON0 EXYNOS_CLKREG(0x0C110)
#define S5P_EPLL_CON1 S5P_CLKREG(0x0C114) #define EXYNOS4_EPLL_CON1 EXYNOS_CLKREG(0x0C114)
#define S5P_VPLL_CON0 S5P_CLKREG(0x0C120) #define EXYNOS4_VPLL_CON0 EXYNOS_CLKREG(0x0C120)
#define S5P_VPLL_CON1 S5P_CLKREG(0x0C124) #define EXYNOS4_VPLL_CON1 EXYNOS_CLKREG(0x0C124)
#define S5P_CLKSRC_TOP0 S5P_CLKREG(0x0C210) #define EXYNOS4_CLKSRC_TOP0 EXYNOS_CLKREG(0x0C210)
#define S5P_CLKSRC_TOP1 S5P_CLKREG(0x0C214) #define EXYNOS4_CLKSRC_TOP1 EXYNOS_CLKREG(0x0C214)
#define S5P_CLKSRC_CAM S5P_CLKREG(0x0C220) #define EXYNOS4_CLKSRC_CAM EXYNOS_CLKREG(0x0C220)
#define S5P_CLKSRC_TV S5P_CLKREG(0x0C224) #define EXYNOS4_CLKSRC_TV EXYNOS_CLKREG(0x0C224)
#define S5P_CLKSRC_MFC S5P_CLKREG(0x0C228) #define EXYNOS4_CLKSRC_MFC EXYNOS_CLKREG(0x0C228)
#define S5P_CLKSRC_G3D S5P_CLKREG(0x0C22C) #define EXYNOS4_CLKSRC_G3D EXYNOS_CLKREG(0x0C22C)
#define S5P_CLKSRC_IMAGE S5P_CLKREG(0x0C230) #define EXYNOS4_CLKSRC_IMAGE EXYNOS_CLKREG(0x0C230)
#define S5P_CLKSRC_LCD0 S5P_CLKREG(0x0C234) #define EXYNOS4_CLKSRC_LCD0 EXYNOS_CLKREG(0x0C234)
#define S5P_CLKSRC_MAUDIO S5P_CLKREG(0x0C23C) #define EXYNOS4_CLKSRC_MAUDIO EXYNOS_CLKREG(0x0C23C)
#define S5P_CLKSRC_FSYS S5P_CLKREG(0x0C240) #define EXYNOS4_CLKSRC_FSYS EXYNOS_CLKREG(0x0C240)
#define S5P_CLKSRC_PERIL0 S5P_CLKREG(0x0C250) #define EXYNOS4_CLKSRC_PERIL0 EXYNOS_CLKREG(0x0C250)
#define S5P_CLKSRC_PERIL1 S5P_CLKREG(0x0C254) #define EXYNOS4_CLKSRC_PERIL1 EXYNOS_CLKREG(0x0C254)
#define S5P_CLKSRC_MASK_TOP S5P_CLKREG(0x0C310) #define EXYNOS4_CLKSRC_MASK_TOP EXYNOS_CLKREG(0x0C310)
#define S5P_CLKSRC_MASK_CAM S5P_CLKREG(0x0C320) #define EXYNOS4_CLKSRC_MASK_CAM EXYNOS_CLKREG(0x0C320)
#define S5P_CLKSRC_MASK_TV S5P_CLKREG(0x0C324) #define EXYNOS4_CLKSRC_MASK_TV EXYNOS_CLKREG(0x0C324)
#define S5P_CLKSRC_MASK_LCD0 S5P_CLKREG(0x0C334) #define EXYNOS4_CLKSRC_MASK_LCD0 EXYNOS_CLKREG(0x0C334)
#define S5P_CLKSRC_MASK_MAUDIO S5P_CLKREG(0x0C33C) #define EXYNOS4_CLKSRC_MASK_MAUDIO EXYNOS_CLKREG(0x0C33C)
#define S5P_CLKSRC_MASK_FSYS S5P_CLKREG(0x0C340) #define EXYNOS4_CLKSRC_MASK_FSYS EXYNOS_CLKREG(0x0C340)
#define S5P_CLKSRC_MASK_PERIL0 S5P_CLKREG(0x0C350) #define EXYNOS4_CLKSRC_MASK_PERIL0 EXYNOS_CLKREG(0x0C350)
#define S5P_CLKSRC_MASK_PERIL1 S5P_CLKREG(0x0C354) #define EXYNOS4_CLKSRC_MASK_PERIL1 EXYNOS_CLKREG(0x0C354)
#define S5P_CLKDIV_TOP S5P_CLKREG(0x0C510) #define EXYNOS4_CLKDIV_TOP EXYNOS_CLKREG(0x0C510)
#define S5P_CLKDIV_CAM S5P_CLKREG(0x0C520) #define EXYNOS4_CLKDIV_CAM EXYNOS_CLKREG(0x0C520)
#define S5P_CLKDIV_TV S5P_CLKREG(0x0C524) #define EXYNOS4_CLKDIV_TV EXYNOS_CLKREG(0x0C524)
#define S5P_CLKDIV_MFC S5P_CLKREG(0x0C528) #define EXYNOS4_CLKDIV_MFC EXYNOS_CLKREG(0x0C528)
#define S5P_CLKDIV_G3D S5P_CLKREG(0x0C52C) #define EXYNOS4_CLKDIV_G3D EXYNOS_CLKREG(0x0C52C)
#define S5P_CLKDIV_IMAGE S5P_CLKREG(0x0C530) #define EXYNOS4_CLKDIV_IMAGE EXYNOS_CLKREG(0x0C530)
#define S5P_CLKDIV_LCD0 S5P_CLKREG(0x0C534) #define EXYNOS4_CLKDIV_LCD0 EXYNOS_CLKREG(0x0C534)
#define S5P_CLKDIV_MAUDIO S5P_CLKREG(0x0C53C) #define EXYNOS4_CLKDIV_MAUDIO EXYNOS_CLKREG(0x0C53C)
#define S5P_CLKDIV_FSYS0 S5P_CLKREG(0x0C540) #define EXYNOS4_CLKDIV_FSYS0 EXYNOS_CLKREG(0x0C540)
#define S5P_CLKDIV_FSYS1 S5P_CLKREG(0x0C544) #define EXYNOS4_CLKDIV_FSYS1 EXYNOS_CLKREG(0x0C544)
#define S5P_CLKDIV_FSYS2 S5P_CLKREG(0x0C548) #define EXYNOS4_CLKDIV_FSYS2 EXYNOS_CLKREG(0x0C548)
#define S5P_CLKDIV_FSYS3 S5P_CLKREG(0x0C54C) #define EXYNOS4_CLKDIV_FSYS3 EXYNOS_CLKREG(0x0C54C)
#define S5P_CLKDIV_PERIL0 S5P_CLKREG(0x0C550) #define EXYNOS4_CLKDIV_PERIL0 EXYNOS_CLKREG(0x0C550)
#define S5P_CLKDIV_PERIL1 S5P_CLKREG(0x0C554) #define EXYNOS4_CLKDIV_PERIL1 EXYNOS_CLKREG(0x0C554)
#define S5P_CLKDIV_PERIL2 S5P_CLKREG(0x0C558) #define EXYNOS4_CLKDIV_PERIL2 EXYNOS_CLKREG(0x0C558)
#define S5P_CLKDIV_PERIL3 S5P_CLKREG(0x0C55C) #define EXYNOS4_CLKDIV_PERIL3 EXYNOS_CLKREG(0x0C55C)
#define S5P_CLKDIV_PERIL4 S5P_CLKREG(0x0C560) #define EXYNOS4_CLKDIV_PERIL4 EXYNOS_CLKREG(0x0C560)
#define S5P_CLKDIV_PERIL5 S5P_CLKREG(0x0C564) #define EXYNOS4_CLKDIV_PERIL5 EXYNOS_CLKREG(0x0C564)
#define S5P_CLKDIV2_RATIO S5P_CLKREG(0x0C580) #define EXYNOS4_CLKDIV2_RATIO EXYNOS_CLKREG(0x0C580)
#define S5P_CLKDIV_STAT_TOP S5P_CLKREG(0x0C610) #define EXYNOS4_CLKDIV_STAT_TOP EXYNOS_CLKREG(0x0C610)
#define S5P_CLKGATE_SCLKCAM S5P_CLKREG(0x0C820) #define EXYNOS4_CLKGATE_SCLKCAM EXYNOS_CLKREG(0x0C820)
#define S5P_CLKGATE_IP_CAM S5P_CLKREG(0x0C920) #define EXYNOS4_CLKGATE_IP_CAM EXYNOS_CLKREG(0x0C920)
#define S5P_CLKGATE_IP_TV S5P_CLKREG(0x0C924) #define EXYNOS4_CLKGATE_IP_TV EXYNOS_CLKREG(0x0C924)
#define S5P_CLKGATE_IP_MFC S5P_CLKREG(0x0C928) #define EXYNOS4_CLKGATE_IP_MFC EXYNOS_CLKREG(0x0C928)
#define S5P_CLKGATE_IP_G3D S5P_CLKREG(0x0C92C) #define EXYNOS4_CLKGATE_IP_G3D EXYNOS_CLKREG(0x0C92C)
#define S5P_CLKGATE_IP_IMAGE (soc_is_exynos4210() ? \ #define EXYNOS4_CLKGATE_IP_IMAGE (soc_is_exynos4210() ? \
S5P_CLKREG(0x0C930) : \ EXYNOS_CLKREG(0x0C930) : \
S5P_CLKREG(0x04930)) EXYNOS_CLKREG(0x04930))
#define S5P_CLKGATE_IP_IMAGE_4210 S5P_CLKREG(0x0C930) #define EXYNOS4210_CLKGATE_IP_IMAGE EXYNOS_CLKREG(0x0C930)
#define S5P_CLKGATE_IP_IMAGE_4212 S5P_CLKREG(0x04930) #define EXYNOS4212_CLKGATE_IP_IMAGE EXYNOS_CLKREG(0x04930)
#define S5P_CLKGATE_IP_LCD0 S5P_CLKREG(0x0C934) #define EXYNOS4_CLKGATE_IP_LCD0 EXYNOS_CLKREG(0x0C934)
#define S5P_CLKGATE_IP_FSYS S5P_CLKREG(0x0C940) #define EXYNOS4_CLKGATE_IP_FSYS EXYNOS_CLKREG(0x0C940)
#define S5P_CLKGATE_IP_GPS S5P_CLKREG(0x0C94C) #define EXYNOS4_CLKGATE_IP_GPS EXYNOS_CLKREG(0x0C94C)
#define S5P_CLKGATE_IP_PERIL S5P_CLKREG(0x0C950) #define EXYNOS4_CLKGATE_IP_PERIL EXYNOS_CLKREG(0x0C950)
#define S5P_CLKGATE_IP_PERIR (soc_is_exynos4210() ? \ #define EXYNOS4_CLKGATE_IP_PERIR (soc_is_exynos4210() ? \
S5P_CLKREG(0x0C960) : \ EXYNOS_CLKREG(0x0C960) : \
S5P_CLKREG(0x08960)) EXYNOS_CLKREG(0x08960))
#define S5P_CLKGATE_IP_PERIR_4210 S5P_CLKREG(0x0C960) #define EXYNOS4210_CLKGATE_IP_PERIR EXYNOS_CLKREG(0x0C960)
#define S5P_CLKGATE_IP_PERIR_4212 S5P_CLKREG(0x08960) #define EXYNOS4212_CLKGATE_IP_PERIR EXYNOS_CLKREG(0x08960)
#define S5P_CLKGATE_BLOCK S5P_CLKREG(0x0C970) #define EXYNOS4_CLKGATE_BLOCK EXYNOS_CLKREG(0x0C970)
#define S5P_CLKSRC_MASK_DMC S5P_CLKREG(0x10300) #define EXYNOS4_CLKSRC_MASK_DMC EXYNOS_CLKREG(0x10300)
#define S5P_CLKSRC_DMC S5P_CLKREG(0x10200) #define EXYNOS4_CLKSRC_DMC EXYNOS_CLKREG(0x10200)
#define S5P_CLKDIV_DMC0 S5P_CLKREG(0x10500) #define EXYNOS4_CLKDIV_DMC0 EXYNOS_CLKREG(0x10500)
#define S5P_CLKDIV_DMC1 S5P_CLKREG(0x10504) #define EXYNOS4_CLKDIV_DMC1 EXYNOS_CLKREG(0x10504)
#define S5P_CLKDIV_STAT_DMC0 S5P_CLKREG(0x10600) #define EXYNOS4_CLKDIV_STAT_DMC0 EXYNOS_CLKREG(0x10600)
#define S5P_CLKGATE_IP_DMC S5P_CLKREG(0x10900) #define EXYNOS4_CLKGATE_IP_DMC EXYNOS_CLKREG(0x10900)
#define S5P_APLL_LOCK S5P_CLKREG(0x14000) #define EXYNOS4_APLL_LOCK EXYNOS_CLKREG(0x14000)
#define S5P_MPLL_LOCK (soc_is_exynos4210() ? \ #define EXYNOS4_MPLL_LOCK (soc_is_exynos4210() ? \
S5P_CLKREG(0x14004) : \ EXYNOS_CLKREG(0x14004) : \
S5P_CLKREG(0x10008)) EXYNOS_CLKREG(0x10008))
#define S5P_APLL_CON0 S5P_CLKREG(0x14100) #define EXYNOS4_APLL_CON0 EXYNOS_CLKREG(0x14100)
#define S5P_APLL_CON1 S5P_CLKREG(0x14104) #define EXYNOS4_APLL_CON1 EXYNOS_CLKREG(0x14104)
#define S5P_MPLL_CON0 (soc_is_exynos4210() ? \ #define EXYNOS4_MPLL_CON0 (soc_is_exynos4210() ? \
S5P_CLKREG(0x14108) : \ EXYNOS_CLKREG(0x14108) : \
S5P_CLKREG(0x10108)) EXYNOS_CLKREG(0x10108))
#define S5P_MPLL_CON1 (soc_is_exynos4210() ? \ #define EXYNOS4_MPLL_CON1 (soc_is_exynos4210() ? \
S5P_CLKREG(0x1410C) : \ EXYNOS_CLKREG(0x1410C) : \
S5P_CLKREG(0x1010C)) EXYNOS_CLKREG(0x1010C))
#define S5P_CLKSRC_CPU S5P_CLKREG(0x14200) #define EXYNOS4_CLKSRC_CPU EXYNOS_CLKREG(0x14200)
#define S5P_CLKMUX_STATCPU S5P_CLKREG(0x14400) #define EXYNOS4_CLKMUX_STATCPU EXYNOS_CLKREG(0x14400)
#define S5P_CLKDIV_CPU S5P_CLKREG(0x14500) #define EXYNOS4_CLKDIV_CPU EXYNOS_CLKREG(0x14500)
#define S5P_CLKDIV_CPU1 S5P_CLKREG(0x14504) #define EXYNOS4_CLKDIV_CPU1 EXYNOS_CLKREG(0x14504)
#define S5P_CLKDIV_STATCPU S5P_CLKREG(0x14600) #define EXYNOS4_CLKDIV_STATCPU EXYNOS_CLKREG(0x14600)
#define S5P_CLKDIV_STATCPU1 S5P_CLKREG(0x14604) #define EXYNOS4_CLKDIV_STATCPU1 EXYNOS_CLKREG(0x14604)
#define S5P_CLKGATE_SCLKCPU S5P_CLKREG(0x14800) #define EXYNOS4_CLKGATE_SCLKCPU EXYNOS_CLKREG(0x14800)
#define S5P_CLKGATE_IP_CPU S5P_CLKREG(0x14900) #define EXYNOS4_CLKGATE_IP_CPU EXYNOS_CLKREG(0x14900)
#define S5P_APLL_LOCKTIME (0x1C20) /* 300us */ #define EXYNOS4_APLL_LOCKTIME (0x1C20) /* 300us */
#define S5P_APLLCON0_ENABLE_SHIFT (31) #define EXYNOS4_APLLCON0_ENABLE_SHIFT (31)
#define S5P_APLLCON0_LOCKED_SHIFT (29) #define EXYNOS4_APLLCON0_LOCKED_SHIFT (29)
#define S5P_APLL_VAL_1000 ((250 << 16) | (6 << 8) | 1) #define EXYNOS4_APLL_VAL_1000 ((250 << 16) | (6 << 8) | 1)
#define S5P_APLL_VAL_800 ((200 << 16) | (6 << 8) | 1) #define EXYNOS4_APLL_VAL_800 ((200 << 16) | (6 << 8) | 1)
#define S5P_EPLLCON0_ENABLE_SHIFT (31) #define EXYNOS4_EPLLCON0_ENABLE_SHIFT (31)
#define S5P_EPLLCON0_LOCKED_SHIFT (29) #define EXYNOS4_EPLLCON0_LOCKED_SHIFT (29)
#define S5P_VPLLCON0_ENABLE_SHIFT (31) #define EXYNOS4_VPLLCON0_ENABLE_SHIFT (31)
#define S5P_VPLLCON0_LOCKED_SHIFT (29) #define EXYNOS4_VPLLCON0_LOCKED_SHIFT (29)
#define S5P_CLKSRC_CPU_MUXCORE_SHIFT (16) #define EXYNOS4_CLKSRC_CPU_MUXCORE_SHIFT (16)
#define S5P_CLKMUX_STATCPU_MUXCORE_MASK (0x7 << S5P_CLKSRC_CPU_MUXCORE_SHIFT) #define EXYNOS4_CLKMUX_STATCPU_MUXCORE_MASK (0x7 << EXYNOS4_CLKSRC_CPU_MUXCORE_SHIFT)
#define S5P_CLKDIV_CPU0_CORE_SHIFT (0) #define EXYNOS4_CLKDIV_CPU0_CORE_SHIFT (0)
#define S5P_CLKDIV_CPU0_CORE_MASK (0x7 << S5P_CLKDIV_CPU0_CORE_SHIFT) #define EXYNOS4_CLKDIV_CPU0_CORE_MASK (0x7 << EXYNOS4_CLKDIV_CPU0_CORE_SHIFT)
#define S5P_CLKDIV_CPU0_COREM0_SHIFT (4) #define EXYNOS4_CLKDIV_CPU0_COREM0_SHIFT (4)
#define S5P_CLKDIV_CPU0_COREM0_MASK (0x7 << S5P_CLKDIV_CPU0_COREM0_SHIFT) #define EXYNOS4_CLKDIV_CPU0_COREM0_MASK (0x7 << EXYNOS4_CLKDIV_CPU0_COREM0_SHIFT)
#define S5P_CLKDIV_CPU0_COREM1_SHIFT (8) #define EXYNOS4_CLKDIV_CPU0_COREM1_SHIFT (8)
#define S5P_CLKDIV_CPU0_COREM1_MASK (0x7 << S5P_CLKDIV_CPU0_COREM1_SHIFT) #define EXYNOS4_CLKDIV_CPU0_COREM1_MASK (0x7 << EXYNOS4_CLKDIV_CPU0_COREM1_SHIFT)
#define S5P_CLKDIV_CPU0_PERIPH_SHIFT (12) #define EXYNOS4_CLKDIV_CPU0_PERIPH_SHIFT (12)
#define S5P_CLKDIV_CPU0_PERIPH_MASK (0x7 << S5P_CLKDIV_CPU0_PERIPH_SHIFT) #define EXYNOS4_CLKDIV_CPU0_PERIPH_MASK (0x7 << EXYNOS4_CLKDIV_CPU0_PERIPH_SHIFT)
#define S5P_CLKDIV_CPU0_ATB_SHIFT (16) #define EXYNOS4_CLKDIV_CPU0_ATB_SHIFT (16)
#define S5P_CLKDIV_CPU0_ATB_MASK (0x7 << S5P_CLKDIV_CPU0_ATB_SHIFT) #define EXYNOS4_CLKDIV_CPU0_ATB_MASK (0x7 << EXYNOS4_CLKDIV_CPU0_ATB_SHIFT)
#define S5P_CLKDIV_CPU0_PCLKDBG_SHIFT (20) #define EXYNOS4_CLKDIV_CPU0_PCLKDBG_SHIFT (20)
#define S5P_CLKDIV_CPU0_PCLKDBG_MASK (0x7 << S5P_CLKDIV_CPU0_PCLKDBG_SHIFT) #define EXYNOS4_CLKDIV_CPU0_PCLKDBG_MASK (0x7 << EXYNOS4_CLKDIV_CPU0_PCLKDBG_SHIFT)
#define S5P_CLKDIV_CPU0_APLL_SHIFT (24) #define EXYNOS4_CLKDIV_CPU0_APLL_SHIFT (24)
#define S5P_CLKDIV_CPU0_APLL_MASK (0x7 << S5P_CLKDIV_CPU0_APLL_SHIFT) #define EXYNOS4_CLKDIV_CPU0_APLL_MASK (0x7 << EXYNOS4_CLKDIV_CPU0_APLL_SHIFT)
#define S5P_CLKDIV_DMC0_ACP_SHIFT (0) #define EXYNOS4_CLKDIV_DMC0_ACP_SHIFT (0)
#define S5P_CLKDIV_DMC0_ACP_MASK (0x7 << S5P_CLKDIV_DMC0_ACP_SHIFT) #define EXYNOS4_CLKDIV_DMC0_ACP_MASK (0x7 << EXYNOS4_CLKDIV_DMC0_ACP_SHIFT)
#define S5P_CLKDIV_DMC0_ACPPCLK_SHIFT (4) #define EXYNOS4_CLKDIV_DMC0_ACPPCLK_SHIFT (4)
#define S5P_CLKDIV_DMC0_ACPPCLK_MASK (0x7 << S5P_CLKDIV_DMC0_ACPPCLK_SHIFT) #define EXYNOS4_CLKDIV_DMC0_ACPPCLK_MASK (0x7 << EXYNOS4_CLKDIV_DMC0_ACPPCLK_SHIFT)
#define S5P_CLKDIV_DMC0_DPHY_SHIFT (8) #define EXYNOS4_CLKDIV_DMC0_DPHY_SHIFT (8)
#define S5P_CLKDIV_DMC0_DPHY_MASK (0x7 << S5P_CLKDIV_DMC0_DPHY_SHIFT) #define EXYNOS4_CLKDIV_DMC0_DPHY_MASK (0x7 << EXYNOS4_CLKDIV_DMC0_DPHY_SHIFT)
#define S5P_CLKDIV_DMC0_DMC_SHIFT (12) #define EXYNOS4_CLKDIV_DMC0_DMC_SHIFT (12)
#define S5P_CLKDIV_DMC0_DMC_MASK (0x7 << S5P_CLKDIV_DMC0_DMC_SHIFT) #define EXYNOS4_CLKDIV_DMC0_DMC_MASK (0x7 << EXYNOS4_CLKDIV_DMC0_DMC_SHIFT)
#define S5P_CLKDIV_DMC0_DMCD_SHIFT (16) #define EXYNOS4_CLKDIV_DMC0_DMCD_SHIFT (16)
#define S5P_CLKDIV_DMC0_DMCD_MASK (0x7 << S5P_CLKDIV_DMC0_DMCD_SHIFT) #define EXYNOS4_CLKDIV_DMC0_DMCD_MASK (0x7 << EXYNOS4_CLKDIV_DMC0_DMCD_SHIFT)
#define S5P_CLKDIV_DMC0_DMCP_SHIFT (20) #define EXYNOS4_CLKDIV_DMC0_DMCP_SHIFT (20)
#define S5P_CLKDIV_DMC0_DMCP_MASK (0x7 << S5P_CLKDIV_DMC0_DMCP_SHIFT) #define EXYNOS4_CLKDIV_DMC0_DMCP_MASK (0x7 << EXYNOS4_CLKDIV_DMC0_DMCP_SHIFT)
#define S5P_CLKDIV_DMC0_COPY2_SHIFT (24) #define EXYNOS4_CLKDIV_DMC0_COPY2_SHIFT (24)
#define S5P_CLKDIV_DMC0_COPY2_MASK (0x7 << S5P_CLKDIV_DMC0_COPY2_SHIFT) #define EXYNOS4_CLKDIV_DMC0_COPY2_MASK (0x7 << EXYNOS4_CLKDIV_DMC0_COPY2_SHIFT)
#define S5P_CLKDIV_DMC0_CORETI_SHIFT (28) #define EXYNOS4_CLKDIV_DMC0_CORETI_SHIFT (28)
#define S5P_CLKDIV_DMC0_CORETI_MASK (0x7 << S5P_CLKDIV_DMC0_CORETI_SHIFT) #define EXYNOS4_CLKDIV_DMC0_CORETI_MASK (0x7 << EXYNOS4_CLKDIV_DMC0_CORETI_SHIFT)
#define S5P_CLKDIV_TOP_ACLK200_SHIFT (0) #define EXYNOS4_CLKDIV_TOP_ACLK200_SHIFT (0)
#define S5P_CLKDIV_TOP_ACLK200_MASK (0x7 << S5P_CLKDIV_TOP_ACLK200_SHIFT) #define EXYNOS4_CLKDIV_TOP_ACLK200_MASK (0x7 << EXYNOS4_CLKDIV_TOP_ACLK200_SHIFT)
#define S5P_CLKDIV_TOP_ACLK100_SHIFT (4) #define EXYNOS4_CLKDIV_TOP_ACLK100_SHIFT (4)
#define S5P_CLKDIV_TOP_ACLK100_MASK (0xf << S5P_CLKDIV_TOP_ACLK100_SHIFT) #define EXYNOS4_CLKDIV_TOP_ACLK100_MASK (0xF << EXYNOS4_CLKDIV_TOP_ACLK100_SHIFT)
#define S5P_CLKDIV_TOP_ACLK160_SHIFT (8) #define EXYNOS4_CLKDIV_TOP_ACLK160_SHIFT (8)
#define S5P_CLKDIV_TOP_ACLK160_MASK (0x7 << S5P_CLKDIV_TOP_ACLK160_SHIFT) #define EXYNOS4_CLKDIV_TOP_ACLK160_MASK (0x7 << EXYNOS4_CLKDIV_TOP_ACLK160_SHIFT)
#define S5P_CLKDIV_TOP_ACLK133_SHIFT (12) #define EXYNOS4_CLKDIV_TOP_ACLK133_SHIFT (12)
#define S5P_CLKDIV_TOP_ACLK133_MASK (0x7 << S5P_CLKDIV_TOP_ACLK133_SHIFT) #define EXYNOS4_CLKDIV_TOP_ACLK133_MASK (0x7 << EXYNOS4_CLKDIV_TOP_ACLK133_SHIFT)
#define S5P_CLKDIV_TOP_ONENAND_SHIFT (16) #define EXYNOS4_CLKDIV_TOP_ONENAND_SHIFT (16)
#define S5P_CLKDIV_TOP_ONENAND_MASK (0x7 << S5P_CLKDIV_TOP_ONENAND_SHIFT) #define EXYNOS4_CLKDIV_TOP_ONENAND_MASK (0x7 << EXYNOS4_CLKDIV_TOP_ONENAND_SHIFT)
#define S5P_CLKDIV_BUS_GDLR_SHIFT (0) #define EXYNOS4_CLKDIV_BUS_GDLR_SHIFT (0)
#define S5P_CLKDIV_BUS_GDLR_MASK (0x7 << S5P_CLKDIV_BUS_GDLR_SHIFT) #define EXYNOS4_CLKDIV_BUS_GDLR_MASK (0x7 << EXYNOS4_CLKDIV_BUS_GDLR_SHIFT)
#define S5P_CLKDIV_BUS_GPLR_SHIFT (4) #define EXYNOS4_CLKDIV_BUS_GPLR_SHIFT (4)
#define S5P_CLKDIV_BUS_GPLR_MASK (0x7 << S5P_CLKDIV_BUS_GPLR_SHIFT) #define EXYNOS4_CLKDIV_BUS_GPLR_MASK (0x7 << EXYNOS4_CLKDIV_BUS_GPLR_SHIFT)
/* Only for EXYNOS4210 */ /* Only for EXYNOS4210 */
#define S5P_CLKSRC_LCD1 S5P_CLKREG(0x0C238) #define EXYNOS4210_CLKSRC_LCD1 EXYNOS_CLKREG(0x0C238)
#define S5P_CLKSRC_MASK_LCD1 S5P_CLKREG(0x0C338) #define EXYNOS4210_CLKSRC_MASK_LCD1 EXYNOS_CLKREG(0x0C338)
#define S5P_CLKDIV_LCD1 S5P_CLKREG(0x0C538) #define EXYNOS4210_CLKDIV_LCD1 EXYNOS_CLKREG(0x0C538)
#define S5P_CLKGATE_IP_LCD1 S5P_CLKREG(0x0C938) #define EXYNOS4210_CLKGATE_IP_LCD1 EXYNOS_CLKREG(0x0C938)
/* Compatibility defines and inclusion */ /* Compatibility defines and inclusion */
#include <mach/regs-pmu.h> #include <mach/regs-pmu.h>
#define S5P_EPLL_CON S5P_EPLL_CON0 #define S5P_EPLL_CON EXYNOS4_EPLL_CON0
#endif /* __ASM_ARCH_REGS_CLOCK_H */ #endif /* __ASM_ARCH_REGS_CLOCK_H */
arch/arm/mach-exynos/pm.c
浏览文件 @ a855039e
...@@ -38,29 +38,29 @@ ...@@ -38,29 +38,29 @@
#include <mach/pmu.h> #include <mach/pmu.h>
static struct sleep_save exynos4_set_clksrc[] = { static struct sleep_save exynos4_set_clksrc[] = {
{ .reg = S5P_CLKSRC_MASK_TOP , .val = 0x00000001, }, { .reg = EXYNOS4_CLKSRC_MASK_TOP , .val = 0x00000001, },
{ .reg = S5P_CLKSRC_MASK_CAM , .val = 0x11111111, }, { .reg = EXYNOS4_CLKSRC_MASK_CAM , .val = 0x11111111, },
{ .reg = S5P_CLKSRC_MASK_TV , .val = 0x00000111, }, { .reg = EXYNOS4_CLKSRC_MASK_TV , .val = 0x00000111, },
{ .reg = S5P_CLKSRC_MASK_LCD0 , .val = 0x00001111, }, { .reg = EXYNOS4_CLKSRC_MASK_LCD0 , .val = 0x00001111, },
{ .reg = S5P_CLKSRC_MASK_MAUDIO , .val = 0x00000001, }, { .reg = EXYNOS4_CLKSRC_MASK_MAUDIO , .val = 0x00000001, },
{ .reg = S5P_CLKSRC_MASK_FSYS , .val = 0x01011111, }, { .reg = EXYNOS4_CLKSRC_MASK_FSYS , .val = 0x01011111, },
{ .reg = S5P_CLKSRC_MASK_PERIL0 , .val = 0x01111111, }, { .reg = EXYNOS4_CLKSRC_MASK_PERIL0 , .val = 0x01111111, },
{ .reg = S5P_CLKSRC_MASK_PERIL1 , .val = 0x01110111, }, { .reg = EXYNOS4_CLKSRC_MASK_PERIL1 , .val = 0x01110111, },
{ .reg = S5P_CLKSRC_MASK_DMC , .val = 0x00010000, }, { .reg = EXYNOS4_CLKSRC_MASK_DMC , .val = 0x00010000, },
}; };
static struct sleep_save exynos4210_set_clksrc[] = { static struct sleep_save exynos4210_set_clksrc[] = {
{ .reg = S5P_CLKSRC_MASK_LCD1 , .val = 0x00001111, }, { .reg = EXYNOS4210_CLKSRC_MASK_LCD1 , .val = 0x00001111, },
}; };
static struct sleep_save exynos4_epll_save[] = { static struct sleep_save exynos4_epll_save[] = {
SAVE_ITEM(S5P_EPLL_CON0), SAVE_ITEM(EXYNOS4_EPLL_CON0),
SAVE_ITEM(S5P_EPLL_CON1), SAVE_ITEM(EXYNOS4_EPLL_CON1),
}; };
static struct sleep_save exynos4_vpll_save[] = { static struct sleep_save exynos4_vpll_save[] = {
SAVE_ITEM(S5P_VPLL_CON0), SAVE_ITEM(EXYNOS4_VPLL_CON0),
SAVE_ITEM(S5P_VPLL_CON1), SAVE_ITEM(EXYNOS4_VPLL_CON1),
}; };
static struct sleep_save exynos4_core_save[] = { static struct sleep_save exynos4_core_save[] = {
...@@ -239,7 +239,7 @@ static void exynos4_restore_pll(void) ...@@ -239,7 +239,7 @@ static void exynos4_restore_pll(void)
locktime = (3000 / pll_in_rate) * p_div; locktime = (3000 / pll_in_rate) * p_div;
lockcnt = locktime * 10000 / (10000 / pll_in_rate); lockcnt = locktime * 10000 / (10000 / pll_in_rate);
__raw_writel(lockcnt, S5P_EPLL_LOCK); __raw_writel(lockcnt, EXYNOS4_EPLL_LOCK);
s3c_pm_do_restore_core(exynos4_epll_save, s3c_pm_do_restore_core(exynos4_epll_save,
ARRAY_SIZE(exynos4_epll_save)); ARRAY_SIZE(exynos4_epll_save));
...@@ -257,7 +257,7 @@ static void exynos4_restore_pll(void) ...@@ -257,7 +257,7 @@ static void exynos4_restore_pll(void)
locktime = 750; locktime = 750;
lockcnt = locktime * 10000 / (10000 / pll_in_rate); lockcnt = locktime * 10000 / (10000 / pll_in_rate);
__raw_writel(lockcnt, S5P_VPLL_LOCK); __raw_writel(lockcnt, EXYNOS4_VPLL_LOCK);
s3c_pm_do_restore_core(exynos4_vpll_save, s3c_pm_do_restore_core(exynos4_vpll_save,
ARRAY_SIZE(exynos4_vpll_save)); ARRAY_SIZE(exynos4_vpll_save));
...@@ -268,14 +268,14 @@ static void exynos4_restore_pll(void) ...@@ -268,14 +268,14 @@ static void exynos4_restore_pll(void)
do { do {
if (epll_wait) { if (epll_wait) {
pll_con = __raw_readl(S5P_EPLL_CON0); pll_con = __raw_readl(EXYNOS4_EPLL_CON0);
if (pll_con & (1 << S5P_EPLLCON0_LOCKED_SHIFT)) if (pll_con & (1 << EXYNOS4_EPLLCON0_LOCKED_SHIFT))
epll_wait = 0; epll_wait = 0;
} }
if (vpll_wait) { if (vpll_wait) {
pll_con = __raw_readl(S5P_VPLL_CON0); pll_con = __raw_readl(EXYNOS4_VPLL_CON0);
if (pll_con & (1 << S5P_VPLLCON0_LOCKED_SHIFT)) if (pll_con & (1 << EXYNOS4_VPLLCON0_LOCKED_SHIFT))
vpll_wait = 0; vpll_wait = 0;
} }
} while (epll_wait || vpll_wait); } while (epll_wait || vpll_wait);
......
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