fsl-ls1028a.dtsi 12.9 KB
Newer Older
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Device Tree Include file for NXP Layerscape-1028A family SoC.
 *
 * Copyright 2018 NXP
 *
 * Harninder Rai <harninder.rai@nxp.com>
 *
 */

#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/thermal/thermal.h>

/ {
	compatible = "fsl,ls1028a";
	interrupt-parent = <&gic>;
	#address-cells = <2>;
	#size-cells = <2>;

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a72";
			reg = <0x0>;
			enable-method = "psci";
			clocks = <&clockgen 1 0>;
			next-level-cache = <&l2>;
			cpu-idle-states = <&CPU_PH20>;
		};

		cpu1: cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a72";
			reg = <0x1>;
			enable-method = "psci";
			clocks = <&clockgen 1 0>;
			next-level-cache = <&l2>;
			cpu-idle-states = <&CPU_PH20>;
		};

		l2: l2-cache {
			compatible = "cache";
		};
	};

	idle-states {
		/*
		 * PSCI node is not added default, U-boot will add missing
		 * parts if it determines to use PSCI.
		 */
		entry-method = "arm,psci";

		CPU_PH20: cpu-ph20 {
			compatible = "arm,idle-state";
			idle-state-name = "PH20";
			arm,psci-suspend-param = <0x00010000>;
			entry-latency-us = <1000>;
			exit-latency-us = <1000>;
			min-residency-us = <3000>;
		};
	};

	sysclk: clock-sysclk {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <100000000>;
		clock-output-names = "sysclk";
	};

	reboot {
		compatible ="syscon-reboot";
		regmap = <&dcfg>;
		offset = <0xb0>;
		mask = <0x02>;
	};

	timer {
		compatible = "arm,armv8-timer";
		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) |
					  IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) |
					  IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) |
					  IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) |
					  IRQ_TYPE_LEVEL_LOW)>;
	};

92 93 94 95 96
	pmu {
		compatible = "arm,cortex-a72-pmu";
		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
	};

97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242
	gic: interrupt-controller@6000000 {
		compatible= "arm,gic-v3";
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;
		reg= <0x0 0x06000000 0 0x10000>, /* GIC Dist */
			<0x0 0x06040000 0 0x40000>; /* GIC Redistributor */
		#interrupt-cells= <3>;
		interrupt-controller;
		interrupts = <GIC_PPI 9 (GIC_CPU_MASK_RAW(0xf) |
					 IRQ_TYPE_LEVEL_LOW)>;
		its: gic-its@6020000 {
			compatible = "arm,gic-v3-its";
			msi-controller;
			reg = <0x0 0x06020000 0 0x20000>;/* GIC Translater */
		};
	};

	soc: soc {
		compatible = "simple-bus";
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		ddr: memory-controller@1080000 {
			compatible = "fsl,qoriq-memory-controller";
			reg = <0x0 0x1080000 0x0 0x1000>;
			interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
			big-endian;
		};

		dcfg: syscon@1e00000 {
			compatible = "fsl,ls1028a-dcfg", "syscon";
			reg = <0x0 0x1e00000 0x0 0x10000>;
			big-endian;
		};

		scfg: syscon@1fc0000 {
			compatible = "fsl,ls1028a-scfg", "syscon";
			reg = <0x0 0x1fc0000 0x0 0x10000>;
			big-endian;
		};

		clockgen: clock-controller@1300000 {
			compatible = "fsl,ls1028a-clockgen";
			reg = <0x0 0x1300000 0x0 0xa0000>;
			#clock-cells = <2>;
			clocks = <&sysclk>;
		};

		i2c0: i2c@2000000 {
			compatible = "fsl,vf610-i2c";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x0 0x2000000 0x0 0x10000>;
			interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clockgen 4 1>;
			status = "disabled";
		};

		i2c1: i2c@2010000 {
			compatible = "fsl,vf610-i2c";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x0 0x2010000 0x0 0x10000>;
			interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clockgen 4 1>;
			status = "disabled";
		};

		i2c2: i2c@2020000 {
			compatible = "fsl,vf610-i2c";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x0 0x2020000 0x0 0x10000>;
			interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clockgen 4 1>;
			status = "disabled";
		};

		i2c3: i2c@2030000 {
			compatible = "fsl,vf610-i2c";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x0 0x2030000 0x0 0x10000>;
			interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clockgen 4 1>;
			status = "disabled";
		};

		i2c4: i2c@2040000 {
			compatible = "fsl,vf610-i2c";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x0 0x2040000 0x0 0x10000>;
			interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clockgen 4 1>;
			status = "disabled";
		};

		i2c5: i2c@2050000 {
			compatible = "fsl,vf610-i2c";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x0 0x2050000 0x0 0x10000>;
			interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clockgen 4 1>;
			status = "disabled";
		};

		i2c6: i2c@2060000 {
			compatible = "fsl,vf610-i2c";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x0 0x2060000 0x0 0x10000>;
			interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clockgen 4 1>;
			status = "disabled";
		};

		i2c7: i2c@2070000 {
			compatible = "fsl,vf610-i2c";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x0 0x2070000 0x0 0x10000>;
			interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clockgen 4 1>;
			status = "disabled";
		};

		duart0: serial@21c0500 {
			compatible = "fsl,ns16550", "ns16550a";
			reg = <0x00 0x21c0500 0x0 0x100>;
			interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clockgen 4 1>;
			status = "disabled";
		};

		duart1: serial@21c0600 {
			compatible = "fsl,ns16550", "ns16550a";
			reg = <0x00 0x21c0600 0x0 0x100>;
			interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clockgen 4 1>;
			status = "disabled";
		};

243 244 245 246 247 248 249 250 251 252 253 254 255 256 257
		edma0: dma-controller@22c0000 {
			#dma-cells = <2>;
			compatible = "fsl,vf610-edma";
			reg = <0x0 0x22c0000 0x0 0x10000>,
			      <0x0 0x22d0000 0x0 0x10000>,
			      <0x0 0x22e0000 0x0 0x10000>;
			interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "edma-tx", "edma-err";
			dma-channels = <32>;
			clock-names = "dmamux0", "dmamux1";
			clocks = <&clockgen 4 1>,
				 <&clockgen 4 1>;
		};

258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299
		gpio1: gpio@2300000 {
			compatible = "fsl,qoriq-gpio";
			reg = <0x0 0x2300000 0x0 0x10000>;
			interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
		};

		gpio2: gpio@2310000 {
			compatible = "fsl,qoriq-gpio";
			reg = <0x0 0x2310000 0x0 0x10000>;
			interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
		};

		gpio3: gpio@2320000 {
			compatible = "fsl,qoriq-gpio";
			reg = <0x0 0x2320000 0x0 0x10000>;
			interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
		};

		wdog0: watchdog@23c0000 {
			compatible = "fsl,ls1028a-wdt", "fsl,imx21-wdt";
			reg = <0x0 0x23c0000 0x0 0x10000>;
			interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clockgen 4 1>;
			big-endian;
			status = "disabled";
		};

		sata: sata@3200000 {
			compatible = "fsl,ls1028a-ahci";
			reg = <0x0 0x3200000 0x0 0x10000>,
300
				<0x7 0x100520 0x0 0x4>;
301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357
			reg-names = "ahci", "sata-ecc";
			interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clockgen 4 1>;
			status = "disabled";
		};

		smmu: iommu@5000000 {
			compatible = "arm,mmu-500";
			reg = <0 0x5000000 0 0x800000>;
			#global-interrupts = <8>;
			#iommu-cells = <1>;
			stream-match-mask = <0x7c00>;
			/* global secure fault */
			interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
			/* combined secure interrupt */
				     <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
			/* global non-secure fault */
				     <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
			/* combined non-secure interrupt */
				     <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
			/* performance counter interrupts 0-7 */
				     <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
			/* per context interrupt, 64 interrupts */
				     <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
		};
358

359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400
		sai1: audio-controller@f100000 {
			#sound-dai-cells = <0>;
			compatible = "fsl,vf610-sai";
			reg = <0x0 0xf100000 0x0 0x10000>;
			interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clockgen 4 1>, <&clockgen 4 1>,
				 <&clockgen 4 1>, <&clockgen 4 1>;
			clock-names = "bus", "mclk1", "mclk2", "mclk3";
			dma-names = "tx", "rx";
			dmas = <&edma0 1 4>,
			       <&edma0 1 3>;
			status = "disabled";
		};

		sai2: audio-controller@f110000 {
			#sound-dai-cells = <0>;
			compatible = "fsl,vf610-sai";
			reg = <0x0 0xf110000 0x0 0x10000>;
			interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clockgen 4 1>, <&clockgen 4 1>,
				 <&clockgen 4 1>, <&clockgen 4 1>;
			clock-names = "bus", "mclk1", "mclk2", "mclk3";
			dma-names = "tx", "rx";
			dmas = <&edma0 1 6>,
			       <&edma0 1 5>;
			status = "disabled";
		};

		sai4: audio-controller@f130000 {
			#sound-dai-cells = <0>;
			compatible = "fsl,vf610-sai";
			reg = <0x0 0xf130000 0x0 0x10000>;
			interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clockgen 4 1>, <&clockgen 4 1>,
				 <&clockgen 4 1>, <&clockgen 4 1>;
			clock-names = "bus", "mclk1", "mclk2", "mclk3";
			dma-names = "tx", "rx";
			dmas = <&edma0 1 10>,
			       <&edma0 1 9>;
			status = "disabled";
		};

401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 419 420 421 422 423 424 425 426 427 428 429 430 431 432 433 434
		pcie@1f0000000 { /* Integrated Endpoint Root Complex */
			compatible = "pci-host-ecam-generic";
			reg = <0x01 0xf0000000 0x0 0x100000>;
			#address-cells = <3>;
			#size-cells = <2>;
			#interrupt-cells = <1>;
			msi-parent = <&its>;
			device_type = "pci";
			bus-range = <0x0 0x0>;
			dma-coherent;
			msi-map = <0 &its 0x17 0xe>;
			iommu-map = <0 &smmu 0x17 0xe>;
				  /* PF0-6 BAR0 - non-prefetchable memory */
			ranges = <0x82000000 0x0 0x00000000  0x1 0xf8000000  0x0 0x160000
				  /* PF0-6 BAR2 - prefetchable memory */
				  0xc2000000 0x0 0x00000000  0x1 0xf8160000  0x0 0x070000
				  /* PF0: VF0-1 BAR0 - non-prefetchable memory */
				  0x82000000 0x0 0x00000000  0x1 0xf81d0000  0x0 0x020000
				  /* PF0: VF0-1 BAR2 - prefetchable memory */
				  0xc2000000 0x0 0x00000000  0x1 0xf81f0000  0x0 0x020000
				  /* PF1: VF0-1 BAR0 - non-prefetchable memory */
				  0x82000000 0x0 0x00000000  0x1 0xf8210000  0x0 0x020000
				  /* PF1: VF0-1 BAR2 - prefetchable memory */
				  0xc2000000 0x0 0x00000000  0x1 0xf8230000  0x0 0x020000>;

			enetc_port0: ethernet@0,0 {
				compatible = "fsl,enetc";
				reg = <0x000000 0 0 0 0>;
			};
			enetc_port1: ethernet@0,1 {
				compatible = "fsl,enetc";
				reg = <0x000100 0 0 0 0>;
			};
		};
435 436
	};
};
新手
引导
客服 返回
顶部