i915_drv.c 47.4 KB
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/* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
 */
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/*
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 *
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 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
 * All Rights Reserved.
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 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the
 * "Software"), to deal in the Software without restriction, including
 * without limitation the rights to use, copy, modify, merge, publish,
 * distribute, sub license, and/or sell copies of the Software, and to
 * permit persons to whom the Software is furnished to do so, subject to
 * the following conditions:
 *
 * The above copyright notice and this permission notice (including the
 * next paragraph) shall be included in all copies or substantial portions
 * of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 *
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 */
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#include <linux/device.h>
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#include <linux/acpi.h>
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#include <drm/drmP.h>
#include <drm/i915_drm.h>
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#include "i915_drv.h"
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#include "i915_trace.h"
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#include "intel_drv.h"
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#include <linux/console.h>
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#include <linux/module.h>
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#include <linux/pm_runtime.h>
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#include <drm/drm_crtc_helper.h>
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static struct drm_driver driver;

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#define GEN_DEFAULT_PIPEOFFSETS \
	.pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \
			  PIPE_C_OFFSET, PIPE_EDP_OFFSET }, \
	.trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \
			   TRANSCODER_C_OFFSET, TRANSCODER_EDP_OFFSET }, \
	.palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET }

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#define GEN_CHV_PIPEOFFSETS \
	.pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \
			  CHV_PIPE_C_OFFSET }, \
	.trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \
			   CHV_TRANSCODER_C_OFFSET, }, \
	.palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET, \
			     CHV_PALETTE_C_OFFSET }
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#define CURSOR_OFFSETS \
	.cursor_offsets = { CURSOR_A_OFFSET, CURSOR_B_OFFSET, CHV_CURSOR_C_OFFSET }

#define IVB_CURSOR_OFFSETS \
	.cursor_offsets = { CURSOR_A_OFFSET, IVB_CURSOR_B_OFFSET, IVB_CURSOR_C_OFFSET }

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static const struct intel_device_info intel_i830_info = {
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	.gen = 2, .is_mobile = 1, .cursor_needs_physical = 1, .num_pipes = 2,
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	.has_overlay = 1, .overlay_needs_physical = 1,
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	.ring_mask = RENDER_RING,
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	GEN_DEFAULT_PIPEOFFSETS,
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	CURSOR_OFFSETS,
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};

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static const struct intel_device_info intel_845g_info = {
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	.gen = 2, .num_pipes = 1,
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	.has_overlay = 1, .overlay_needs_physical = 1,
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	.ring_mask = RENDER_RING,
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	GEN_DEFAULT_PIPEOFFSETS,
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	CURSOR_OFFSETS,
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};

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static const struct intel_device_info intel_i85x_info = {
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	.gen = 2, .is_i85x = 1, .is_mobile = 1, .num_pipes = 2,
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	.cursor_needs_physical = 1,
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	.has_overlay = 1, .overlay_needs_physical = 1,
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	.has_fbc = 1,
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	.ring_mask = RENDER_RING,
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	GEN_DEFAULT_PIPEOFFSETS,
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	CURSOR_OFFSETS,
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};

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static const struct intel_device_info intel_i865g_info = {
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	.gen = 2, .num_pipes = 1,
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	.has_overlay = 1, .overlay_needs_physical = 1,
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	.ring_mask = RENDER_RING,
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	GEN_DEFAULT_PIPEOFFSETS,
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	CURSOR_OFFSETS,
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};

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static const struct intel_device_info intel_i915g_info = {
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	.gen = 3, .is_i915g = 1, .cursor_needs_physical = 1, .num_pipes = 2,
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	.has_overlay = 1, .overlay_needs_physical = 1,
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	.ring_mask = RENDER_RING,
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	GEN_DEFAULT_PIPEOFFSETS,
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	CURSOR_OFFSETS,
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};
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static const struct intel_device_info intel_i915gm_info = {
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	.gen = 3, .is_mobile = 1, .num_pipes = 2,
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	.cursor_needs_physical = 1,
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	.has_overlay = 1, .overlay_needs_physical = 1,
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	.supports_tv = 1,
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	.has_fbc = 1,
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	.ring_mask = RENDER_RING,
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	GEN_DEFAULT_PIPEOFFSETS,
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	CURSOR_OFFSETS,
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};
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static const struct intel_device_info intel_i945g_info = {
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	.gen = 3, .has_hotplug = 1, .cursor_needs_physical = 1, .num_pipes = 2,
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	.has_overlay = 1, .overlay_needs_physical = 1,
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	.ring_mask = RENDER_RING,
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	GEN_DEFAULT_PIPEOFFSETS,
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	CURSOR_OFFSETS,
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};
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static const struct intel_device_info intel_i945gm_info = {
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	.gen = 3, .is_i945gm = 1, .is_mobile = 1, .num_pipes = 2,
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	.has_hotplug = 1, .cursor_needs_physical = 1,
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	.has_overlay = 1, .overlay_needs_physical = 1,
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	.supports_tv = 1,
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	.has_fbc = 1,
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	.ring_mask = RENDER_RING,
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	GEN_DEFAULT_PIPEOFFSETS,
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	CURSOR_OFFSETS,
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};

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static const struct intel_device_info intel_i965g_info = {
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	.gen = 4, .is_broadwater = 1, .num_pipes = 2,
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	.has_hotplug = 1,
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	.has_overlay = 1,
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	.ring_mask = RENDER_RING,
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	GEN_DEFAULT_PIPEOFFSETS,
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	CURSOR_OFFSETS,
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};

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static const struct intel_device_info intel_i965gm_info = {
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	.gen = 4, .is_crestline = 1, .num_pipes = 2,
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	.is_mobile = 1, .has_fbc = 1, .has_hotplug = 1,
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	.has_overlay = 1,
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	.supports_tv = 1,
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	.ring_mask = RENDER_RING,
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	GEN_DEFAULT_PIPEOFFSETS,
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	CURSOR_OFFSETS,
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};

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static const struct intel_device_info intel_g33_info = {
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	.gen = 3, .is_g33 = 1, .num_pipes = 2,
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	.need_gfx_hws = 1, .has_hotplug = 1,
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	.has_overlay = 1,
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	.ring_mask = RENDER_RING,
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	GEN_DEFAULT_PIPEOFFSETS,
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	CURSOR_OFFSETS,
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};

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static const struct intel_device_info intel_g45_info = {
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	.gen = 4, .is_g4x = 1, .need_gfx_hws = 1, .num_pipes = 2,
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	.has_pipe_cxsr = 1, .has_hotplug = 1,
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	.ring_mask = RENDER_RING | BSD_RING,
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	GEN_DEFAULT_PIPEOFFSETS,
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	CURSOR_OFFSETS,
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};

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static const struct intel_device_info intel_gm45_info = {
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	.gen = 4, .is_g4x = 1, .num_pipes = 2,
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	.is_mobile = 1, .need_gfx_hws = 1, .has_fbc = 1,
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	.has_pipe_cxsr = 1, .has_hotplug = 1,
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	.supports_tv = 1,
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	.ring_mask = RENDER_RING | BSD_RING,
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	GEN_DEFAULT_PIPEOFFSETS,
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	CURSOR_OFFSETS,
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};

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static const struct intel_device_info intel_pineview_info = {
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	.gen = 3, .is_g33 = 1, .is_pineview = 1, .is_mobile = 1, .num_pipes = 2,
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	.need_gfx_hws = 1, .has_hotplug = 1,
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	.has_overlay = 1,
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	GEN_DEFAULT_PIPEOFFSETS,
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	CURSOR_OFFSETS,
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};

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static const struct intel_device_info intel_ironlake_d_info = {
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	.gen = 5, .num_pipes = 2,
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	.need_gfx_hws = 1, .has_hotplug = 1,
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	.ring_mask = RENDER_RING | BSD_RING,
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	GEN_DEFAULT_PIPEOFFSETS,
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	CURSOR_OFFSETS,
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};

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static const struct intel_device_info intel_ironlake_m_info = {
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	.gen = 5, .is_mobile = 1, .num_pipes = 2,
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	.need_gfx_hws = 1, .has_hotplug = 1,
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	.has_fbc = 1,
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	.ring_mask = RENDER_RING | BSD_RING,
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	GEN_DEFAULT_PIPEOFFSETS,
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	CURSOR_OFFSETS,
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};

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static const struct intel_device_info intel_sandybridge_d_info = {
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	.gen = 6, .num_pipes = 2,
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	.need_gfx_hws = 1, .has_hotplug = 1,
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	.has_fbc = 1,
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	.ring_mask = RENDER_RING | BSD_RING | BLT_RING,
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	.has_llc = 1,
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	GEN_DEFAULT_PIPEOFFSETS,
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	CURSOR_OFFSETS,
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};

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static const struct intel_device_info intel_sandybridge_m_info = {
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	.gen = 6, .is_mobile = 1, .num_pipes = 2,
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	.need_gfx_hws = 1, .has_hotplug = 1,
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	.has_fbc = 1,
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	.ring_mask = RENDER_RING | BSD_RING | BLT_RING,
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	.has_llc = 1,
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	GEN_DEFAULT_PIPEOFFSETS,
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	CURSOR_OFFSETS,
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};

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#define GEN7_FEATURES  \
	.gen = 7, .num_pipes = 3, \
	.need_gfx_hws = 1, .has_hotplug = 1, \
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	.has_fbc = 1, \
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	.ring_mask = RENDER_RING | BSD_RING | BLT_RING, \
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	.has_llc = 1
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static const struct intel_device_info intel_ivybridge_d_info = {
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	GEN7_FEATURES,
	.is_ivybridge = 1,
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	GEN_DEFAULT_PIPEOFFSETS,
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	IVB_CURSOR_OFFSETS,
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};

static const struct intel_device_info intel_ivybridge_m_info = {
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	GEN7_FEATURES,
	.is_ivybridge = 1,
	.is_mobile = 1,
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	GEN_DEFAULT_PIPEOFFSETS,
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	IVB_CURSOR_OFFSETS,
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};

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static const struct intel_device_info intel_ivybridge_q_info = {
	GEN7_FEATURES,
	.is_ivybridge = 1,
	.num_pipes = 0, /* legal, last one wins */
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	GEN_DEFAULT_PIPEOFFSETS,
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	IVB_CURSOR_OFFSETS,
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};

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static const struct intel_device_info intel_valleyview_m_info = {
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	GEN7_FEATURES,
	.is_mobile = 1,
	.num_pipes = 2,
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	.is_valleyview = 1,
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	.display_mmio_offset = VLV_DISPLAY_BASE,
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	.has_fbc = 0, /* legal, last one wins */
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	.has_llc = 0, /* legal, last one wins */
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	GEN_DEFAULT_PIPEOFFSETS,
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	CURSOR_OFFSETS,
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};

static const struct intel_device_info intel_valleyview_d_info = {
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	GEN7_FEATURES,
	.num_pipes = 2,
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	.is_valleyview = 1,
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	.display_mmio_offset = VLV_DISPLAY_BASE,
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	.has_fbc = 0, /* legal, last one wins */
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	.has_llc = 0, /* legal, last one wins */
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	GEN_DEFAULT_PIPEOFFSETS,
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	CURSOR_OFFSETS,
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};

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static const struct intel_device_info intel_haswell_d_info = {
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	GEN7_FEATURES,
	.is_haswell = 1,
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	.has_ddi = 1,
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	.has_fpga_dbg = 1,
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	.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
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	GEN_DEFAULT_PIPEOFFSETS,
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	IVB_CURSOR_OFFSETS,
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};

static const struct intel_device_info intel_haswell_m_info = {
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	GEN7_FEATURES,
	.is_haswell = 1,
	.is_mobile = 1,
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	.has_ddi = 1,
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	.has_fpga_dbg = 1,
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	.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
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	GEN_DEFAULT_PIPEOFFSETS,
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	IVB_CURSOR_OFFSETS,
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};

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static const struct intel_device_info intel_broadwell_d_info = {
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	.gen = 8, .num_pipes = 3,
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	.need_gfx_hws = 1, .has_hotplug = 1,
	.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
	.has_llc = 1,
	.has_ddi = 1,
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	.has_fpga_dbg = 1,
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	.has_fbc = 1,
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	GEN_DEFAULT_PIPEOFFSETS,
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	IVB_CURSOR_OFFSETS,
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};

static const struct intel_device_info intel_broadwell_m_info = {
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	.gen = 8, .is_mobile = 1, .num_pipes = 3,
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	.need_gfx_hws = 1, .has_hotplug = 1,
	.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
	.has_llc = 1,
	.has_ddi = 1,
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	.has_fpga_dbg = 1,
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	.has_fbc = 1,
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	GEN_DEFAULT_PIPEOFFSETS,
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	IVB_CURSOR_OFFSETS,
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};

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static const struct intel_device_info intel_broadwell_gt3d_info = {
	.gen = 8, .num_pipes = 3,
	.need_gfx_hws = 1, .has_hotplug = 1,
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	.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
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	.has_llc = 1,
	.has_ddi = 1,
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	.has_fpga_dbg = 1,
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	.has_fbc = 1,
	GEN_DEFAULT_PIPEOFFSETS,
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	IVB_CURSOR_OFFSETS,
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};

static const struct intel_device_info intel_broadwell_gt3m_info = {
	.gen = 8, .is_mobile = 1, .num_pipes = 3,
	.need_gfx_hws = 1, .has_hotplug = 1,
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	.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
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	.has_llc = 1,
	.has_ddi = 1,
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	.has_fpga_dbg = 1,
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	.has_fbc = 1,
	GEN_DEFAULT_PIPEOFFSETS,
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	IVB_CURSOR_OFFSETS,
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};

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static const struct intel_device_info intel_cherryview_info = {
	.is_preliminary = 1,
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	.gen = 8, .num_pipes = 3,
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	.need_gfx_hws = 1, .has_hotplug = 1,
	.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
	.is_valleyview = 1,
	.display_mmio_offset = VLV_DISPLAY_BASE,
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	GEN_CHV_PIPEOFFSETS,
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	CURSOR_OFFSETS,
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};

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static const struct intel_device_info intel_skylake_info = {
	.is_preliminary = 1,
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	.is_skylake = 1,
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	.gen = 9, .num_pipes = 3,
	.need_gfx_hws = 1, .has_hotplug = 1,
	.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
	.has_llc = 1,
	.has_ddi = 1,
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	.has_fbc = 1,
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	GEN_DEFAULT_PIPEOFFSETS,
	IVB_CURSOR_OFFSETS,
};

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/*
 * Make sure any device matches here are from most specific to most
 * general.  For example, since the Quanta match is based on the subsystem
 * and subvendor IDs, we need it to come before the more general IVB
 * PCI ID matches, otherwise we'll use the wrong info struct above.
 */
#define INTEL_PCI_IDS \
	INTEL_I830_IDS(&intel_i830_info),	\
	INTEL_I845G_IDS(&intel_845g_info),	\
	INTEL_I85X_IDS(&intel_i85x_info),	\
	INTEL_I865G_IDS(&intel_i865g_info),	\
	INTEL_I915G_IDS(&intel_i915g_info),	\
	INTEL_I915GM_IDS(&intel_i915gm_info),	\
	INTEL_I945G_IDS(&intel_i945g_info),	\
	INTEL_I945GM_IDS(&intel_i945gm_info),	\
	INTEL_I965G_IDS(&intel_i965g_info),	\
	INTEL_G33_IDS(&intel_g33_info),		\
	INTEL_I965GM_IDS(&intel_i965gm_info),	\
	INTEL_GM45_IDS(&intel_gm45_info), 	\
	INTEL_G45_IDS(&intel_g45_info), 	\
	INTEL_PINEVIEW_IDS(&intel_pineview_info),	\
	INTEL_IRONLAKE_D_IDS(&intel_ironlake_d_info),	\
	INTEL_IRONLAKE_M_IDS(&intel_ironlake_m_info),	\
	INTEL_SNB_D_IDS(&intel_sandybridge_d_info),	\
	INTEL_SNB_M_IDS(&intel_sandybridge_m_info),	\
	INTEL_IVB_Q_IDS(&intel_ivybridge_q_info), /* must be first IVB */ \
	INTEL_IVB_M_IDS(&intel_ivybridge_m_info),	\
	INTEL_IVB_D_IDS(&intel_ivybridge_d_info),	\
	INTEL_HSW_D_IDS(&intel_haswell_d_info), \
	INTEL_HSW_M_IDS(&intel_haswell_m_info), \
	INTEL_VLV_M_IDS(&intel_valleyview_m_info),	\
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	INTEL_VLV_D_IDS(&intel_valleyview_d_info),	\
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	INTEL_BDW_GT12M_IDS(&intel_broadwell_m_info),	\
	INTEL_BDW_GT12D_IDS(&intel_broadwell_d_info),	\
	INTEL_BDW_GT3M_IDS(&intel_broadwell_gt3m_info),	\
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	INTEL_BDW_GT3D_IDS(&intel_broadwell_gt3d_info), \
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	INTEL_CHV_IDS(&intel_cherryview_info),	\
	INTEL_SKL_IDS(&intel_skylake_info)
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static const struct pci_device_id pciidlist[] = {		/* aka */
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	INTEL_PCI_IDS,
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	{0, 0, 0}
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};

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#if defined(CONFIG_DRM_I915_KMS)
MODULE_DEVICE_TABLE(pci, pciidlist);
#endif

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void intel_detect_pch(struct drm_device *dev)
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{
	struct drm_i915_private *dev_priv = dev->dev_private;
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	struct pci_dev *pch = NULL;
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	/* In all current cases, num_pipes is equivalent to the PCH_NOP setting
	 * (which really amounts to a PCH but no South Display).
	 */
	if (INTEL_INFO(dev)->num_pipes == 0) {
		dev_priv->pch_type = PCH_NOP;
		return;
	}

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	/*
	 * The reason to probe ISA bridge instead of Dev31:Fun0 is to
	 * make graphics device passthrough work easy for VMM, that only
	 * need to expose ISA bridge to let driver know the real hardware
	 * underneath. This is a requirement from virtualization team.
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	 *
	 * In some virtualized environments (e.g. XEN), there is irrelevant
	 * ISA bridge in the system. To work reliably, we should scan trhough
	 * all the ISA bridge devices and check for the first match, instead
	 * of only checking the first one.
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	 */
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	while ((pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, pch))) {
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		if (pch->vendor == PCI_VENDOR_ID_INTEL) {
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			unsigned short id = pch->device & INTEL_PCH_DEVICE_ID_MASK;
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			dev_priv->pch_id = id;
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			if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) {
				dev_priv->pch_type = PCH_IBX;
				DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
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				WARN_ON(!IS_GEN5(dev));
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			} else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) {
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				dev_priv->pch_type = PCH_CPT;
				DRM_DEBUG_KMS("Found CougarPoint PCH\n");
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				WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev)));
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			} else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) {
				/* PantherPoint is CPT compatible */
				dev_priv->pch_type = PCH_CPT;
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				DRM_DEBUG_KMS("Found PantherPoint PCH\n");
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				WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev)));
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			} else if (id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
				dev_priv->pch_type = PCH_LPT;
				DRM_DEBUG_KMS("Found LynxPoint PCH\n");
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				WARN_ON(!IS_HASWELL(dev));
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				WARN_ON(IS_HSW_ULT(dev));
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			} else if (IS_BROADWELL(dev)) {
				dev_priv->pch_type = PCH_LPT;
				dev_priv->pch_id =
					INTEL_PCH_LPT_LP_DEVICE_ID_TYPE;
				DRM_DEBUG_KMS("This is Broadwell, assuming "
					      "LynxPoint LP PCH\n");
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			} else if (id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
				dev_priv->pch_type = PCH_LPT;
				DRM_DEBUG_KMS("Found LynxPoint LP PCH\n");
				WARN_ON(!IS_HASWELL(dev));
477
				WARN_ON(!IS_HSW_ULT(dev));
478 479 480 481 482 483 484 485
			} else if (id == INTEL_PCH_SPT_DEVICE_ID_TYPE) {
				dev_priv->pch_type = PCH_SPT;
				DRM_DEBUG_KMS("Found SunrisePoint PCH\n");
				WARN_ON(!IS_SKYLAKE(dev));
			} else if (id == INTEL_PCH_SPT_LP_DEVICE_ID_TYPE) {
				dev_priv->pch_type = PCH_SPT;
				DRM_DEBUG_KMS("Found SunrisePoint LP PCH\n");
				WARN_ON(!IS_SKYLAKE(dev));
486 487 488
			} else
				continue;

489
			break;
490 491
		}
	}
492
	if (!pch)
493 494 495
		DRM_DEBUG_KMS("No PCH found.\n");

	pci_dev_put(pch);
496 497
}

498 499 500
bool i915_semaphore_is_enabled(struct drm_device *dev)
{
	if (INTEL_INFO(dev)->gen < 6)
501
		return false;
502

503 504
	if (i915.semaphores >= 0)
		return i915.semaphores;
505

506 507 508 509
	/* TODO: make semaphores and Execlists play nicely together */
	if (i915.enable_execlists)
		return false;

510 511 512 513
	/* Until we get further testing... */
	if (IS_GEN8(dev))
		return false;

514
#ifdef CONFIG_INTEL_IOMMU
515
	/* Enable semaphores on SNB when IO remapping is off */
516 517 518
	if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped)
		return false;
#endif
519

520
	return true;
521 522
}

523 524 525 526 527 528 529 530 531 532 533 534 535 536 537
void intel_hpd_cancel_work(struct drm_i915_private *dev_priv)
{
	spin_lock_irq(&dev_priv->irq_lock);

	dev_priv->long_hpd_port_mask = 0;
	dev_priv->short_hpd_port_mask = 0;
	dev_priv->hpd_event_bits = 0;

	spin_unlock_irq(&dev_priv->irq_lock);

	cancel_work_sync(&dev_priv->dig_port_work);
	cancel_work_sync(&dev_priv->hotplug_work);
	cancel_delayed_work_sync(&dev_priv->hotplug_reenable_work);
}

538 539 540 541 542 543 544 545 546 547 548 549 550 551 552
static void intel_suspend_encoders(struct drm_i915_private *dev_priv)
{
	struct drm_device *dev = dev_priv->dev;
	struct drm_encoder *encoder;

	drm_modeset_lock_all(dev);
	list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
		struct intel_encoder *intel_encoder = to_intel_encoder(encoder);

		if (intel_encoder->suspend)
			intel_encoder->suspend(intel_encoder);
	}
	drm_modeset_unlock_all(dev);
}

553
static int intel_suspend_complete(struct drm_i915_private *dev_priv);
554 555
static int intel_resume_prepare(struct drm_i915_private *dev_priv,
				bool rpm_resume);
556

557
static int i915_drm_freeze(struct drm_device *dev)
J
Jesse Barnes 已提交
558
{
559
	struct drm_i915_private *dev_priv = dev->dev_private;
560
	struct drm_crtc *crtc;
561
	pci_power_t opregion_target_state;
562

563 564 565 566 567
	/* ignore lid events during suspend */
	mutex_lock(&dev_priv->modeset_restore_lock);
	dev_priv->modeset_restore = MODESET_SUSPENDED;
	mutex_unlock(&dev_priv->modeset_restore_lock);

568 569
	/* We do a lot of poking in a lot of registers, make sure they work
	 * properly. */
570
	intel_display_set_init_power(dev_priv, true);
571

572 573
	drm_kms_helper_poll_disable(dev);

J
Jesse Barnes 已提交
574 575
	pci_save_state(dev->pdev);

576
	/* If KMS is active, we do the leavevt stuff here */
577
	if (drm_core_check_feature(dev, DRIVER_MODESET)) {
578 579
		int error;

580
		error = i915_gem_suspend(dev);
581
		if (error) {
582
			dev_err(&dev->pdev->dev,
583 584 585
				"GEM idle failed, resume might fail\n");
			return error;
		}
586

587 588
		/*
		 * Disable CRTCs directly since we want to preserve sw state
589
		 * for _thaw. Also, power gate the CRTC power wells.
590
		 */
591
		drm_modeset_lock_all(dev);
592 593
		for_each_crtc(dev, crtc)
			intel_crtc_control(crtc, false);
594
		drm_modeset_unlock_all(dev);
595

596
		intel_dp_mst_suspend(dev);
597 598 599

		flush_delayed_work(&dev_priv->rps.delayed_resume_work);

600
		intel_runtime_pm_disable_interrupts(dev_priv);
601
		intel_hpd_cancel_work(dev_priv);
602

603 604
		intel_suspend_encoders(dev_priv);

605 606
		intel_suspend_gt_powersave(dev);

607
		intel_suspend_hw(dev);
608 609
	}

610 611
	i915_gem_suspend_gtt_mappings(dev);

612 613
	i915_save_state(dev);

614 615 616
	opregion_target_state = PCI_D3cold;
#if IS_ENABLED(CONFIG_ACPI_SLEEP)
	if (acpi_target_system_state() < ACPI_STATE_S3)
617
		opregion_target_state = PCI_D1;
618
#endif
619 620
	intel_opregion_notify_adapter(dev, opregion_target_state);

621
	intel_uncore_forcewake_reset(dev, false);
622
	intel_opregion_fini(dev);
623

624
	intel_fbdev_set_suspend(dev, FBINFO_STATE_SUSPENDED, true);
625

626 627
	dev_priv->suspend_count++;

628 629
	intel_display_set_init_power(dev_priv, false);

630
	return 0;
631 632
}

633
int i915_suspend(struct drm_device *dev, pm_message_t state)
634 635 636 637 638 639 640 641 642
{
	int error;

	if (!dev || !dev->dev_private) {
		DRM_ERROR("dev: %p\n", dev);
		DRM_ERROR("DRM not initialized, aborting suspend.\n");
		return -ENODEV;
	}

643 644 645
	if (WARN_ON_ONCE(state.event != PM_EVENT_SUSPEND &&
			 state.event != PM_EVENT_FREEZE))
		return -EINVAL;
646 647 648

	if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
		return 0;
649

650 651 652 653
	error = i915_drm_freeze(dev);
	if (error)
		return error;

654 655 656 657 658
	if (state.event == PM_EVENT_SUSPEND) {
		/* Shut down the device */
		pci_disable_device(dev->pdev);
		pci_set_power_state(dev->pdev, PCI_D3hot);
	}
J
Jesse Barnes 已提交
659 660 661 662

	return 0;
}

663
static int i915_drm_thaw_early(struct drm_device *dev)
J
Jesse Barnes 已提交
664
{
665
	struct drm_i915_private *dev_priv = dev->dev_private;
666
	int ret;
667

668 669 670
	ret = intel_resume_prepare(dev_priv, false);
	if (ret)
		DRM_ERROR("Resume prepare failed: %d,Continuing resume\n", ret);
671

672
	intel_uncore_early_sanitize(dev, true);
673
	intel_uncore_sanitize(dev);
674 675
	intel_power_domains_init_hw(dev_priv);

676
	return ret;
677 678 679 680 681
}

static int __i915_drm_thaw(struct drm_device *dev, bool restore_gtt_mappings)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
682 683 684 685 686 687 688 689

	if (drm_core_check_feature(dev, DRIVER_MODESET) &&
	    restore_gtt_mappings) {
		mutex_lock(&dev->struct_mutex);
		i915_gem_restore_gtt_mappings(dev);
		mutex_unlock(&dev->struct_mutex);
	}

690
	i915_restore_state(dev);
691
	intel_opregion_setup(dev);
692

693 694
	/* KMS EnterVT equivalent */
	if (drm_core_check_feature(dev, DRIVER_MODESET)) {
P
Paulo Zanoni 已提交
695
		intel_init_pch_refclk(dev);
696
		drm_mode_config_reset(dev);
697

698
		mutex_lock(&dev->struct_mutex);
699 700 701 702
		if (i915_gem_init_hw(dev)) {
			DRM_ERROR("failed to re-initialize GPU, declaring wedged!\n");
			atomic_set_mask(I915_WEDGED, &dev_priv->gpu_error.reset_counter);
		}
703
		mutex_unlock(&dev->struct_mutex);
704

705
		/* We need working interrupts for modeset enabling ... */
706
		intel_runtime_pm_enable_interrupts(dev_priv);
707

708
		intel_modeset_init_hw(dev);
709

710
		{
711
			spin_lock_irq(&dev_priv->irq_lock);
712 713
			if (dev_priv->display.hpd_irq_setup)
				dev_priv->display.hpd_irq_setup(dev);
714
			spin_unlock_irq(&dev_priv->irq_lock);
715 716 717
		}

		intel_dp_mst_resume(dev);
718 719 720
		drm_modeset_lock_all(dev);
		intel_modeset_setup_hw_state(dev, true);
		drm_modeset_unlock_all(dev);
721 722 723 724 725 726 727

		/*
		 * ... but also need to make sure that hotplug processing
		 * doesn't cause havoc. Like in the driver load code we don't
		 * bother with the tiny race here where we might loose hotplug
		 * notifications.
		 * */
728
		intel_hpd_init(dev_priv);
729
		/* Config may have changed between suspend and resume */
730
		drm_helper_hpd_irq_event(dev);
J
Jesse Barnes 已提交
731
	}
732

733 734
	intel_opregion_init(dev);

735
	intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING, false);
736

737 738 739
	mutex_lock(&dev_priv->modeset_restore_lock);
	dev_priv->modeset_restore = MODESET_DONE;
	mutex_unlock(&dev_priv->modeset_restore_lock);
740

741 742
	intel_opregion_notify_adapter(dev, PCI_D0);

743
	return 0;
744 745
}

746 747
static int i915_drm_thaw(struct drm_device *dev)
{
748
	if (drm_core_check_feature(dev, DRIVER_MODESET))
749
		i915_check_and_clear_faults(dev);
750

751
	return __i915_drm_thaw(dev, true);
752 753
}

754
static int i915_resume_early(struct drm_device *dev)
755
{
756 757 758
	if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
		return 0;

759 760 761 762 763 764 765 766 767
	/*
	 * We have a resume ordering issue with the snd-hda driver also
	 * requiring our device to be power up. Due to the lack of a
	 * parent/child relationship we currently solve this with an early
	 * resume hook.
	 *
	 * FIXME: This should be solved with a special hdmi sink device or
	 * similar so that power domains can be employed.
	 */
768 769 770 771 772
	if (pci_enable_device(dev->pdev))
		return -EIO;

	pci_set_master(dev->pdev);

773 774 775 776 777 778 779 780
	return i915_drm_thaw_early(dev);
}

int i915_resume(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	int ret;

781 782
	/*
	 * Platforms with opregion should have sane BIOS, older ones (gen3 and
783 784
	 * earlier) need to restore the GTT mappings since the BIOS might clear
	 * all our scratch PTEs.
785
	 */
786
	ret = __i915_drm_thaw(dev, !dev_priv->opregion.header);
787 788 789 790 791
	if (ret)
		return ret;

	drm_kms_helper_poll_enable(dev);
	return 0;
J
Jesse Barnes 已提交
792 793
}

794 795 796 797 798 799 800 801
static int i915_resume_legacy(struct drm_device *dev)
{
	i915_resume_early(dev);
	i915_resume(dev);

	return 0;
}

802
/**
803
 * i915_reset - reset chip after a hang
804 805 806 807 808 809 810 811 812 813 814 815 816
 * @dev: drm device to reset
 *
 * Reset the chip.  Useful if a hang is detected. Returns zero on successful
 * reset or otherwise an error code.
 *
 * Procedure is fairly simple:
 *   - reset the chip using the reset reg
 *   - re-init context state
 *   - re-init hardware status page
 *   - re-init ring buffer
 *   - re-init interrupt state
 *   - re-init display
 */
817
int i915_reset(struct drm_device *dev)
818
{
819
	struct drm_i915_private *dev_priv = dev->dev_private;
820
	bool simulated;
821
	int ret;
822

823
	if (!i915.reset)
C
Chris Wilson 已提交
824 825
		return 0;

826
	mutex_lock(&dev->struct_mutex);
827

828
	i915_gem_reset(dev);
829

830 831
	simulated = dev_priv->gpu_error.stop_rings != 0;

832 833 834 835 836 837 838
	ret = intel_gpu_reset(dev);

	/* Also reset the gpu hangman. */
	if (simulated) {
		DRM_INFO("Simulated gpu hang, resetting stop_rings\n");
		dev_priv->gpu_error.stop_rings = 0;
		if (ret == -ENODEV) {
839 840
			DRM_INFO("Reset not implemented, but ignoring "
				 "error for simulated gpu hangs\n");
841 842
			ret = 0;
		}
843
	}
844

845 846 847
	if (i915_stop_ring_allow_warn(dev_priv))
		pr_notice("drm/i915: Resetting chip after gpu hang\n");

848
	if (ret) {
849
		DRM_ERROR("Failed to reset chip: %i\n", ret);
850
		mutex_unlock(&dev->struct_mutex);
851
		return ret;
852 853 854 855 856 857 858 859 860 861 862 863 864 865 866 867 868
	}

	/* Ok, now get things going again... */

	/*
	 * Everything depends on having the GTT running, so we need to start
	 * there.  Fortunately we don't need to do this unless we reset the
	 * chip at a PCI level.
	 *
	 * Next we need to restore the context, but we don't use those
	 * yet either...
	 *
	 * Ring buffer needs to be re-initialized in the KMS case, or if X
	 * was running at the time of the reset (i.e. we weren't VT
	 * switched away).
	 */
	if (drm_core_check_feature(dev, DRIVER_MODESET) ||
869 870
			!dev_priv->ums.mm_suspended) {
		dev_priv->ums.mm_suspended = 0;
871

872 873 874
		/* Used to prevent gem_check_wedged returning -EAGAIN during gpu reset */
		dev_priv->gpu_error.reload_in_reset = true;

875
		ret = i915_gem_init_hw(dev);
876 877 878

		dev_priv->gpu_error.reload_in_reset = false;

879
		mutex_unlock(&dev->struct_mutex);
880 881 882 883
		if (ret) {
			DRM_ERROR("Failed hw init on reset %d\n", ret);
			return ret;
		}
884

885
		/*
886 887 888
		 * FIXME: This races pretty badly against concurrent holders of
		 * ring interrupts. This is possible since we've started to drop
		 * dev->struct_mutex in select places when waiting for the gpu.
889
		 */
J
Jeff McGee 已提交
890

891 892 893
		/*
		 * rps/rc6 re-init is necessary to restore state lost after the
		 * reset and the re-install of gt irqs. Skip for ironlake per
J
Jeff McGee 已提交
894
		 * previous concerns that it doesn't respond well to some forms
895 896
		 * of re-init after reset.
		 */
897
		if (INTEL_INFO(dev)->gen > 5)
898
			intel_reset_gt_powersave(dev);
899 900
	} else {
		mutex_unlock(&dev->struct_mutex);
901 902 903 904 905
	}

	return 0;
}

906
static int i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
907
{
908 909 910
	struct intel_device_info *intel_info =
		(struct intel_device_info *) ent->driver_data;

911
	if (IS_PRELIMINARY_HW(intel_info) && !i915.preliminary_hw_support) {
912 913 914 915 916
		DRM_INFO("This hardware requires preliminary hardware support.\n"
			 "See CONFIG_DRM_I915_PRELIMINARY_HW_SUPPORT, and/or modparam preliminary_hw_support\n");
		return -ENODEV;
	}

917 918 919 920 921 922 923 924
	/* Only bind to function 0 of the device. Early generations
	 * used function 1 as a placeholder for multi-head. This causes
	 * us confusion instead, especially on the systems where both
	 * functions have the same PCI-ID!
	 */
	if (PCI_FUNC(pdev->devfn))
		return -ENODEV;

D
Daniel Vetter 已提交
925
	driver.driver_features &= ~(DRIVER_USE_AGP);
926

927
	return drm_get_pci_dev(pdev, ent, &driver);
928 929 930 931 932 933 934 935 936 937
}

static void
i915_pci_remove(struct pci_dev *pdev)
{
	struct drm_device *dev = pci_get_drvdata(pdev);

	drm_put_dev(dev);
}

938
static int i915_pm_suspend(struct device *dev)
939
{
940 941
	struct pci_dev *pdev = to_pci_dev(dev);
	struct drm_device *drm_dev = pci_get_drvdata(pdev);
942

943 944 945 946
	if (!drm_dev || !drm_dev->dev_private) {
		dev_err(dev, "DRM not initialized, aborting suspend.\n");
		return -ENODEV;
	}
947

948 949 950
	if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
		return 0;

951 952 953 954 955 956 957
	return i915_drm_freeze(drm_dev);
}

static int i915_pm_suspend_late(struct device *dev)
{
	struct pci_dev *pdev = to_pci_dev(dev);
	struct drm_device *drm_dev = pci_get_drvdata(pdev);
958
	struct drm_i915_private *dev_priv = drm_dev->dev_private;
959
	int ret;
960 961 962 963 964 965 966 967 968 969 970 971

	/*
	 * We have a suspedn ordering issue with the snd-hda driver also
	 * requiring our device to be power up. Due to the lack of a
	 * parent/child relationship we currently solve this with an late
	 * suspend hook.
	 *
	 * FIXME: This should be solved with a special hdmi sink device or
	 * similar so that power domains can be employed.
	 */
	if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
		return 0;
972

973
	ret = intel_suspend_complete(dev_priv);
974

975 976 977 978 979 980
	if (ret)
		DRM_ERROR("Suspend complete failed: %d\n", ret);
	else {
		pci_disable_device(pdev);
		pci_set_power_state(pdev, PCI_D3hot);
	}
981

982
	return ret;
983 984
}

985 986 987 988 989 990 991 992
static int i915_pm_resume_early(struct device *dev)
{
	struct pci_dev *pdev = to_pci_dev(dev);
	struct drm_device *drm_dev = pci_get_drvdata(pdev);

	return i915_resume_early(drm_dev);
}

993
static int i915_pm_resume(struct device *dev)
994
{
995 996 997 998
	struct pci_dev *pdev = to_pci_dev(dev);
	struct drm_device *drm_dev = pci_get_drvdata(pdev);

	return i915_resume(drm_dev);
999 1000
}

1001
static int i915_pm_freeze(struct device *dev)
1002
{
1003 1004 1005 1006 1007 1008 1009 1010 1011
	struct pci_dev *pdev = to_pci_dev(dev);
	struct drm_device *drm_dev = pci_get_drvdata(pdev);

	if (!drm_dev || !drm_dev->dev_private) {
		dev_err(dev, "DRM not initialized, aborting suspend.\n");
		return -ENODEV;
	}

	return i915_drm_freeze(drm_dev);
1012 1013
}

1014 1015 1016 1017 1018 1019 1020 1021
static int i915_pm_thaw_early(struct device *dev)
{
	struct pci_dev *pdev = to_pci_dev(dev);
	struct drm_device *drm_dev = pci_get_drvdata(pdev);

	return i915_drm_thaw_early(drm_dev);
}

1022
static int i915_pm_thaw(struct device *dev)
1023
{
1024 1025 1026 1027
	struct pci_dev *pdev = to_pci_dev(dev);
	struct drm_device *drm_dev = pci_get_drvdata(pdev);

	return i915_drm_thaw(drm_dev);
1028 1029
}

1030
static int i915_pm_poweroff(struct device *dev)
1031
{
1032 1033 1034
	struct pci_dev *pdev = to_pci_dev(dev);
	struct drm_device *drm_dev = pci_get_drvdata(pdev);

1035
	return i915_drm_freeze(drm_dev);
1036 1037
}

1038
static int hsw_suspend_complete(struct drm_i915_private *dev_priv)
1039
{
P
Paulo Zanoni 已提交
1040
	hsw_enable_pc8(dev_priv);
1041 1042

	return 0;
1043 1044
}

1045 1046
static int snb_resume_prepare(struct drm_i915_private *dev_priv,
				bool rpm_resume)
1047 1048 1049
{
	struct drm_device *dev = dev_priv->dev;

1050 1051
	if (rpm_resume)
		intel_init_pch_refclk(dev);
1052 1053

	return 0;
1054 1055
}

1056 1057
static int hsw_resume_prepare(struct drm_i915_private *dev_priv,
				bool rpm_resume)
1058
{
P
Paulo Zanoni 已提交
1059
	hsw_disable_pc8(dev_priv);
1060 1061

	return 0;
1062 1063
}

1064 1065 1066 1067 1068 1069 1070 1071 1072 1073 1074 1075 1076 1077 1078 1079 1080 1081 1082 1083 1084 1085 1086 1087 1088 1089 1090 1091 1092 1093 1094 1095 1096 1097 1098 1099 1100 1101 1102 1103 1104 1105 1106 1107 1108 1109 1110 1111 1112 1113 1114 1115 1116 1117 1118 1119 1120 1121 1122 1123 1124 1125 1126 1127 1128 1129 1130 1131 1132 1133 1134 1135 1136 1137 1138 1139 1140 1141 1142 1143 1144 1145 1146 1147 1148 1149 1150 1151 1152 1153 1154 1155 1156 1157 1158 1159 1160 1161 1162 1163 1164 1165 1166 1167 1168 1169 1170 1171 1172 1173 1174 1175 1176 1177 1178 1179 1180 1181 1182 1183 1184 1185 1186 1187 1188 1189 1190 1191 1192 1193 1194 1195 1196 1197 1198 1199 1200 1201 1202 1203 1204 1205 1206 1207 1208 1209 1210 1211 1212 1213 1214 1215 1216 1217 1218 1219 1220 1221 1222 1223 1224 1225 1226 1227 1228 1229 1230 1231 1232 1233 1234 1235 1236 1237 1238 1239 1240 1241 1242 1243 1244 1245 1246 1247 1248 1249 1250 1251 1252 1253 1254 1255
/*
 * Save all Gunit registers that may be lost after a D3 and a subsequent
 * S0i[R123] transition. The list of registers needing a save/restore is
 * defined in the VLV2_S0IXRegs document. This documents marks all Gunit
 * registers in the following way:
 * - Driver: saved/restored by the driver
 * - Punit : saved/restored by the Punit firmware
 * - No, w/o marking: no need to save/restore, since the register is R/O or
 *                    used internally by the HW in a way that doesn't depend
 *                    keeping the content across a suspend/resume.
 * - Debug : used for debugging
 *
 * We save/restore all registers marked with 'Driver', with the following
 * exceptions:
 * - Registers out of use, including also registers marked with 'Debug'.
 *   These have no effect on the driver's operation, so we don't save/restore
 *   them to reduce the overhead.
 * - Registers that are fully setup by an initialization function called from
 *   the resume path. For example many clock gating and RPS/RC6 registers.
 * - Registers that provide the right functionality with their reset defaults.
 *
 * TODO: Except for registers that based on the above 3 criteria can be safely
 * ignored, we save/restore all others, practically treating the HW context as
 * a black-box for the driver. Further investigation is needed to reduce the
 * saved/restored registers even further, by following the same 3 criteria.
 */
static void vlv_save_gunit_s0ix_state(struct drm_i915_private *dev_priv)
{
	struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state;
	int i;

	/* GAM 0x4000-0x4770 */
	s->wr_watermark		= I915_READ(GEN7_WR_WATERMARK);
	s->gfx_prio_ctrl	= I915_READ(GEN7_GFX_PRIO_CTRL);
	s->arb_mode		= I915_READ(ARB_MODE);
	s->gfx_pend_tlb0	= I915_READ(GEN7_GFX_PEND_TLB0);
	s->gfx_pend_tlb1	= I915_READ(GEN7_GFX_PEND_TLB1);

	for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
		s->lra_limits[i] = I915_READ(GEN7_LRA_LIMITS_BASE + i * 4);

	s->media_max_req_count	= I915_READ(GEN7_MEDIA_MAX_REQ_COUNT);
	s->gfx_max_req_count	= I915_READ(GEN7_MEDIA_MAX_REQ_COUNT);

	s->render_hwsp		= I915_READ(RENDER_HWS_PGA_GEN7);
	s->ecochk		= I915_READ(GAM_ECOCHK);
	s->bsd_hwsp		= I915_READ(BSD_HWS_PGA_GEN7);
	s->blt_hwsp		= I915_READ(BLT_HWS_PGA_GEN7);

	s->tlb_rd_addr		= I915_READ(GEN7_TLB_RD_ADDR);

	/* MBC 0x9024-0x91D0, 0x8500 */
	s->g3dctl		= I915_READ(VLV_G3DCTL);
	s->gsckgctl		= I915_READ(VLV_GSCKGCTL);
	s->mbctl		= I915_READ(GEN6_MBCTL);

	/* GCP 0x9400-0x9424, 0x8100-0x810C */
	s->ucgctl1		= I915_READ(GEN6_UCGCTL1);
	s->ucgctl3		= I915_READ(GEN6_UCGCTL3);
	s->rcgctl1		= I915_READ(GEN6_RCGCTL1);
	s->rcgctl2		= I915_READ(GEN6_RCGCTL2);
	s->rstctl		= I915_READ(GEN6_RSTCTL);
	s->misccpctl		= I915_READ(GEN7_MISCCPCTL);

	/* GPM 0xA000-0xAA84, 0x8000-0x80FC */
	s->gfxpause		= I915_READ(GEN6_GFXPAUSE);
	s->rpdeuhwtc		= I915_READ(GEN6_RPDEUHWTC);
	s->rpdeuc		= I915_READ(GEN6_RPDEUC);
	s->ecobus		= I915_READ(ECOBUS);
	s->pwrdwnupctl		= I915_READ(VLV_PWRDWNUPCTL);
	s->rp_down_timeout	= I915_READ(GEN6_RP_DOWN_TIMEOUT);
	s->rp_deucsw		= I915_READ(GEN6_RPDEUCSW);
	s->rcubmabdtmr		= I915_READ(GEN6_RCUBMABDTMR);
	s->rcedata		= I915_READ(VLV_RCEDATA);
	s->spare2gh		= I915_READ(VLV_SPAREG2H);

	/* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
	s->gt_imr		= I915_READ(GTIMR);
	s->gt_ier		= I915_READ(GTIER);
	s->pm_imr		= I915_READ(GEN6_PMIMR);
	s->pm_ier		= I915_READ(GEN6_PMIER);

	for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
		s->gt_scratch[i] = I915_READ(GEN7_GT_SCRATCH_BASE + i * 4);

	/* GT SA CZ domain, 0x100000-0x138124 */
	s->tilectl		= I915_READ(TILECTL);
	s->gt_fifoctl		= I915_READ(GTFIFOCTL);
	s->gtlc_wake_ctrl	= I915_READ(VLV_GTLC_WAKE_CTRL);
	s->gtlc_survive		= I915_READ(VLV_GTLC_SURVIVABILITY_REG);
	s->pmwgicz		= I915_READ(VLV_PMWGICZ);

	/* Gunit-Display CZ domain, 0x182028-0x1821CF */
	s->gu_ctl0		= I915_READ(VLV_GU_CTL0);
	s->gu_ctl1		= I915_READ(VLV_GU_CTL1);
	s->clock_gate_dis2	= I915_READ(VLV_GUNIT_CLOCK_GATE2);

	/*
	 * Not saving any of:
	 * DFT,		0x9800-0x9EC0
	 * SARB,	0xB000-0xB1FC
	 * GAC,		0x5208-0x524C, 0x14000-0x14C000
	 * PCI CFG
	 */
}

static void vlv_restore_gunit_s0ix_state(struct drm_i915_private *dev_priv)
{
	struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state;
	u32 val;
	int i;

	/* GAM 0x4000-0x4770 */
	I915_WRITE(GEN7_WR_WATERMARK,	s->wr_watermark);
	I915_WRITE(GEN7_GFX_PRIO_CTRL,	s->gfx_prio_ctrl);
	I915_WRITE(ARB_MODE,		s->arb_mode | (0xffff << 16));
	I915_WRITE(GEN7_GFX_PEND_TLB0,	s->gfx_pend_tlb0);
	I915_WRITE(GEN7_GFX_PEND_TLB1,	s->gfx_pend_tlb1);

	for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
		I915_WRITE(GEN7_LRA_LIMITS_BASE + i * 4, s->lra_limits[i]);

	I915_WRITE(GEN7_MEDIA_MAX_REQ_COUNT, s->media_max_req_count);
	I915_WRITE(GEN7_MEDIA_MAX_REQ_COUNT, s->gfx_max_req_count);

	I915_WRITE(RENDER_HWS_PGA_GEN7,	s->render_hwsp);
	I915_WRITE(GAM_ECOCHK,		s->ecochk);
	I915_WRITE(BSD_HWS_PGA_GEN7,	s->bsd_hwsp);
	I915_WRITE(BLT_HWS_PGA_GEN7,	s->blt_hwsp);

	I915_WRITE(GEN7_TLB_RD_ADDR,	s->tlb_rd_addr);

	/* MBC 0x9024-0x91D0, 0x8500 */
	I915_WRITE(VLV_G3DCTL,		s->g3dctl);
	I915_WRITE(VLV_GSCKGCTL,	s->gsckgctl);
	I915_WRITE(GEN6_MBCTL,		s->mbctl);

	/* GCP 0x9400-0x9424, 0x8100-0x810C */
	I915_WRITE(GEN6_UCGCTL1,	s->ucgctl1);
	I915_WRITE(GEN6_UCGCTL3,	s->ucgctl3);
	I915_WRITE(GEN6_RCGCTL1,	s->rcgctl1);
	I915_WRITE(GEN6_RCGCTL2,	s->rcgctl2);
	I915_WRITE(GEN6_RSTCTL,		s->rstctl);
	I915_WRITE(GEN7_MISCCPCTL,	s->misccpctl);

	/* GPM 0xA000-0xAA84, 0x8000-0x80FC */
	I915_WRITE(GEN6_GFXPAUSE,	s->gfxpause);
	I915_WRITE(GEN6_RPDEUHWTC,	s->rpdeuhwtc);
	I915_WRITE(GEN6_RPDEUC,		s->rpdeuc);
	I915_WRITE(ECOBUS,		s->ecobus);
	I915_WRITE(VLV_PWRDWNUPCTL,	s->pwrdwnupctl);
	I915_WRITE(GEN6_RP_DOWN_TIMEOUT,s->rp_down_timeout);
	I915_WRITE(GEN6_RPDEUCSW,	s->rp_deucsw);
	I915_WRITE(GEN6_RCUBMABDTMR,	s->rcubmabdtmr);
	I915_WRITE(VLV_RCEDATA,		s->rcedata);
	I915_WRITE(VLV_SPAREG2H,	s->spare2gh);

	/* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
	I915_WRITE(GTIMR,		s->gt_imr);
	I915_WRITE(GTIER,		s->gt_ier);
	I915_WRITE(GEN6_PMIMR,		s->pm_imr);
	I915_WRITE(GEN6_PMIER,		s->pm_ier);

	for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
		I915_WRITE(GEN7_GT_SCRATCH_BASE + i * 4, s->gt_scratch[i]);

	/* GT SA CZ domain, 0x100000-0x138124 */
	I915_WRITE(TILECTL,			s->tilectl);
	I915_WRITE(GTFIFOCTL,			s->gt_fifoctl);
	/*
	 * Preserve the GT allow wake and GFX force clock bit, they are not
	 * be restored, as they are used to control the s0ix suspend/resume
	 * sequence by the caller.
	 */
	val = I915_READ(VLV_GTLC_WAKE_CTRL);
	val &= VLV_GTLC_ALLOWWAKEREQ;
	val |= s->gtlc_wake_ctrl & ~VLV_GTLC_ALLOWWAKEREQ;
	I915_WRITE(VLV_GTLC_WAKE_CTRL, val);

	val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
	val &= VLV_GFX_CLK_FORCE_ON_BIT;
	val |= s->gtlc_survive & ~VLV_GFX_CLK_FORCE_ON_BIT;
	I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val);

	I915_WRITE(VLV_PMWGICZ,			s->pmwgicz);

	/* Gunit-Display CZ domain, 0x182028-0x1821CF */
	I915_WRITE(VLV_GU_CTL0,			s->gu_ctl0);
	I915_WRITE(VLV_GU_CTL1,			s->gu_ctl1);
	I915_WRITE(VLV_GUNIT_CLOCK_GATE2,	s->clock_gate_dis2);
}

1256 1257 1258 1259 1260 1261 1262 1263 1264 1265 1266
int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool force_on)
{
	u32 val;
	int err;

	val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
	WARN_ON(!!(val & VLV_GFX_CLK_FORCE_ON_BIT) == force_on);

#define COND (I915_READ(VLV_GTLC_SURVIVABILITY_REG) & VLV_GFX_CLK_STATUS_BIT)
	/* Wait for a previous force-off to settle */
	if (force_on) {
1267
		err = wait_for(!COND, 20);
1268 1269 1270 1271 1272 1273 1274 1275 1276 1277 1278 1279 1280 1281 1282 1283
		if (err) {
			DRM_ERROR("timeout waiting for GFX clock force-off (%08x)\n",
				  I915_READ(VLV_GTLC_SURVIVABILITY_REG));
			return err;
		}
	}

	val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
	val &= ~VLV_GFX_CLK_FORCE_ON_BIT;
	if (force_on)
		val |= VLV_GFX_CLK_FORCE_ON_BIT;
	I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val);

	if (!force_on)
		return 0;

1284
	err = wait_for(COND, 20);
1285 1286 1287 1288 1289 1290 1291 1292
	if (err)
		DRM_ERROR("timeout waiting for GFX clock force-on (%08x)\n",
			  I915_READ(VLV_GTLC_SURVIVABILITY_REG));

	return err;
#undef COND
}

1293 1294 1295 1296 1297 1298 1299 1300 1301 1302 1303 1304 1305 1306 1307 1308 1309 1310 1311 1312 1313 1314 1315 1316 1317 1318 1319 1320 1321 1322 1323 1324 1325 1326 1327 1328 1329 1330 1331 1332 1333 1334 1335 1336 1337 1338 1339 1340 1341 1342 1343 1344 1345 1346 1347 1348 1349 1350 1351 1352
static int vlv_allow_gt_wake(struct drm_i915_private *dev_priv, bool allow)
{
	u32 val;
	int err = 0;

	val = I915_READ(VLV_GTLC_WAKE_CTRL);
	val &= ~VLV_GTLC_ALLOWWAKEREQ;
	if (allow)
		val |= VLV_GTLC_ALLOWWAKEREQ;
	I915_WRITE(VLV_GTLC_WAKE_CTRL, val);
	POSTING_READ(VLV_GTLC_WAKE_CTRL);

#define COND (!!(I915_READ(VLV_GTLC_PW_STATUS) & VLV_GTLC_ALLOWWAKEACK) == \
	      allow)
	err = wait_for(COND, 1);
	if (err)
		DRM_ERROR("timeout disabling GT waking\n");
	return err;
#undef COND
}

static int vlv_wait_for_gt_wells(struct drm_i915_private *dev_priv,
				 bool wait_for_on)
{
	u32 mask;
	u32 val;
	int err;

	mask = VLV_GTLC_PW_MEDIA_STATUS_MASK | VLV_GTLC_PW_RENDER_STATUS_MASK;
	val = wait_for_on ? mask : 0;
#define COND ((I915_READ(VLV_GTLC_PW_STATUS) & mask) == val)
	if (COND)
		return 0;

	DRM_DEBUG_KMS("waiting for GT wells to go %s (%08x)\n",
			wait_for_on ? "on" : "off",
			I915_READ(VLV_GTLC_PW_STATUS));

	/*
	 * RC6 transitioning can be delayed up to 2 msec (see
	 * valleyview_enable_rps), use 3 msec for safety.
	 */
	err = wait_for(COND, 3);
	if (err)
		DRM_ERROR("timeout waiting for GT wells to go %s\n",
			  wait_for_on ? "on" : "off");

	return err;
#undef COND
}

static void vlv_check_no_gt_access(struct drm_i915_private *dev_priv)
{
	if (!(I915_READ(VLV_GTLC_PW_STATUS) & VLV_GTLC_ALLOWWAKEERR))
		return;

	DRM_ERROR("GT register access while GT waking disabled\n");
	I915_WRITE(VLV_GTLC_PW_STATUS, VLV_GTLC_ALLOWWAKEERR);
}

1353
static int vlv_suspend_complete(struct drm_i915_private *dev_priv)
1354 1355 1356 1357 1358 1359 1360 1361 1362 1363 1364 1365 1366 1367 1368 1369 1370 1371 1372 1373 1374 1375 1376 1377 1378 1379 1380 1381 1382 1383 1384 1385 1386 1387 1388 1389 1390 1391 1392
{
	u32 mask;
	int err;

	/*
	 * Bspec defines the following GT well on flags as debug only, so
	 * don't treat them as hard failures.
	 */
	(void)vlv_wait_for_gt_wells(dev_priv, false);

	mask = VLV_GTLC_RENDER_CTX_EXISTS | VLV_GTLC_MEDIA_CTX_EXISTS;
	WARN_ON((I915_READ(VLV_GTLC_WAKE_CTRL) & mask) != mask);

	vlv_check_no_gt_access(dev_priv);

	err = vlv_force_gfx_clock(dev_priv, true);
	if (err)
		goto err1;

	err = vlv_allow_gt_wake(dev_priv, false);
	if (err)
		goto err2;
	vlv_save_gunit_s0ix_state(dev_priv);

	err = vlv_force_gfx_clock(dev_priv, false);
	if (err)
		goto err2;

	return 0;

err2:
	/* For safety always re-enable waking and disable gfx clock forcing */
	vlv_allow_gt_wake(dev_priv, true);
err1:
	vlv_force_gfx_clock(dev_priv, false);

	return err;
}

1393 1394
static int vlv_resume_prepare(struct drm_i915_private *dev_priv,
				bool rpm_resume)
1395 1396 1397 1398 1399 1400 1401 1402 1403 1404 1405 1406 1407 1408 1409 1410 1411 1412 1413 1414 1415 1416 1417 1418
{
	struct drm_device *dev = dev_priv->dev;
	int err;
	int ret;

	/*
	 * If any of the steps fail just try to continue, that's the best we
	 * can do at this point. Return the first error code (which will also
	 * leave RPM permanently disabled).
	 */
	ret = vlv_force_gfx_clock(dev_priv, true);

	vlv_restore_gunit_s0ix_state(dev_priv);

	err = vlv_allow_gt_wake(dev_priv, true);
	if (!ret)
		ret = err;

	err = vlv_force_gfx_clock(dev_priv, false);
	if (!ret)
		ret = err;

	vlv_check_no_gt_access(dev_priv);

1419 1420 1421 1422
	if (rpm_resume) {
		intel_init_clock_gating(dev);
		i915_gem_restore_fences(dev);
	}
1423 1424 1425 1426

	return ret;
}

1427
static int intel_runtime_suspend(struct device *device)
1428 1429 1430 1431
{
	struct pci_dev *pdev = to_pci_dev(device);
	struct drm_device *dev = pci_get_drvdata(pdev);
	struct drm_i915_private *dev_priv = dev->dev_private;
1432
	int ret;
1433

1434
	if (WARN_ON_ONCE(!(dev_priv->rps.enabled && intel_enable_rc6(dev))))
1435 1436
		return -ENODEV;

1437 1438 1439
	if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev)))
		return -ENODEV;

1440
	assert_force_wake_inactive(dev_priv);
1441 1442 1443

	DRM_DEBUG_KMS("Suspending device\n");

1444 1445 1446 1447 1448 1449 1450 1451 1452 1453 1454 1455 1456 1457 1458 1459 1460 1461 1462 1463 1464 1465 1466 1467
	/*
	 * We could deadlock here in case another thread holding struct_mutex
	 * calls RPM suspend concurrently, since the RPM suspend will wait
	 * first for this RPM suspend to finish. In this case the concurrent
	 * RPM resume will be followed by its RPM suspend counterpart. Still
	 * for consistency return -EAGAIN, which will reschedule this suspend.
	 */
	if (!mutex_trylock(&dev->struct_mutex)) {
		DRM_DEBUG_KMS("device lock contention, deffering suspend\n");
		/*
		 * Bump the expiration timestamp, otherwise the suspend won't
		 * be rescheduled.
		 */
		pm_runtime_mark_last_busy(device);

		return -EAGAIN;
	}
	/*
	 * We are safe here against re-faults, since the fault handler takes
	 * an RPM reference.
	 */
	i915_gem_release_all_mmaps(dev_priv);
	mutex_unlock(&dev->struct_mutex);

1468 1469 1470 1471 1472 1473
	/*
	 * rps.work can't be rearmed here, since we get here only after making
	 * sure the GPU is idle and the RPS freq is set to the minimum. See
	 * intel_mark_idle().
	 */
	cancel_work_sync(&dev_priv->rps.work);
1474
	intel_runtime_pm_disable_interrupts(dev_priv);
1475

1476
	ret = intel_suspend_complete(dev_priv);
1477 1478
	if (ret) {
		DRM_ERROR("Runtime suspend failed, disabling it (%d)\n", ret);
1479
		intel_runtime_pm_enable_interrupts(dev_priv);
1480 1481 1482

		return ret;
	}
1483

1484
	del_timer_sync(&dev_priv->gpu_error.hangcheck_timer);
1485
	dev_priv->pm.suspended = true;
1486 1487

	/*
1488 1489
	 * FIXME: We really should find a document that references the arguments
	 * used below!
1490
	 */
1491 1492 1493 1494 1495 1496 1497 1498 1499 1500 1501 1502 1503 1504 1505 1506 1507 1508 1509 1510
	if (IS_HASWELL(dev)) {
		/*
		 * current versions of firmware which depend on this opregion
		 * notification have repurposed the D1 definition to mean
		 * "runtime suspended" vs. what you would normally expect (D3)
		 * to distinguish it from notifications that might be sent via
		 * the suspend path.
		 */
		intel_opregion_notify_adapter(dev, PCI_D1);
	} else {
		/*
		 * On Broadwell, if we use PCI_D1 the PCH DDI ports will stop
		 * being detected, and the call we do at intel_runtime_resume()
		 * won't be able to restore them. Since PCI_D3hot matches the
		 * actual specification and appears to be working, use it. Let's
		 * assume the other non-Haswell platforms will stay the same as
		 * Broadwell.
		 */
		intel_opregion_notify_adapter(dev, PCI_D3hot);
	}
1511

1512
	DRM_DEBUG_KMS("Device suspended\n");
1513 1514 1515
	return 0;
}

1516
static int intel_runtime_resume(struct device *device)
1517 1518 1519 1520
{
	struct pci_dev *pdev = to_pci_dev(device);
	struct drm_device *dev = pci_get_drvdata(pdev);
	struct drm_i915_private *dev_priv = dev->dev_private;
1521
	int ret;
1522

1523 1524
	if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev)))
		return -ENODEV;
1525 1526 1527

	DRM_DEBUG_KMS("Resuming device\n");

1528
	intel_opregion_notify_adapter(dev, PCI_D0);
1529 1530
	dev_priv->pm.suspended = false;

1531
	ret = intel_resume_prepare(dev_priv, true);
1532 1533 1534 1535
	/*
	 * No point of rolling back things in case of an error, as the best
	 * we can do is to hope that things will still work (and disable RPM).
	 */
1536 1537 1538
	i915_gem_init_swizzling(dev);
	gen6_update_ring_freq(dev);

1539
	intel_runtime_pm_enable_interrupts(dev_priv);
1540
	intel_reset_gt_powersave(dev);
1541

1542 1543 1544 1545 1546 1547
	if (ret)
		DRM_ERROR("Runtime resume failed, disabling it (%d)\n", ret);
	else
		DRM_DEBUG_KMS("Device resumed\n");

	return ret;
1548 1549
}

1550 1551 1552 1553
/*
 * This function implements common functionality of runtime and system
 * suspend sequence.
 */
1554 1555 1556 1557 1558
static int intel_suspend_complete(struct drm_i915_private *dev_priv)
{
	struct drm_device *dev = dev_priv->dev;
	int ret;

1559
	if (IS_HASWELL(dev) || IS_BROADWELL(dev))
1560
		ret = hsw_suspend_complete(dev_priv);
1561
	else if (IS_VALLEYVIEW(dev))
1562
		ret = vlv_suspend_complete(dev_priv);
1563 1564
	else
		ret = 0;
1565 1566 1567 1568

	return ret;
}

1569 1570 1571 1572 1573 1574 1575
/*
 * This function implements common functionality of runtime and system
 * resume sequence. Variable rpm_resume used for implementing different
 * code paths.
 */
static int intel_resume_prepare(struct drm_i915_private *dev_priv,
				bool rpm_resume)
1576 1577 1578 1579
{
	struct drm_device *dev = dev_priv->dev;
	int ret;

1580
	if (IS_GEN6(dev))
1581
		ret = snb_resume_prepare(dev_priv, rpm_resume);
1582
	else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
1583
		ret = hsw_resume_prepare(dev_priv, rpm_resume);
1584
	else if (IS_VALLEYVIEW(dev))
1585
		ret = vlv_resume_prepare(dev_priv, rpm_resume);
1586 1587
	else
		ret = 0;
1588 1589 1590 1591

	return ret;
}

1592
static const struct dev_pm_ops i915_pm_ops = {
1593
	.suspend = i915_pm_suspend,
1594 1595
	.suspend_late = i915_pm_suspend_late,
	.resume_early = i915_pm_resume_early,
1596 1597
	.resume = i915_pm_resume,
	.freeze = i915_pm_freeze,
1598
	.thaw_early = i915_pm_thaw_early,
1599 1600
	.thaw = i915_pm_thaw,
	.poweroff = i915_pm_poweroff,
1601
	.restore_early = i915_pm_resume_early,
1602
	.restore = i915_pm_resume,
1603 1604
	.runtime_suspend = intel_runtime_suspend,
	.runtime_resume = intel_runtime_resume,
1605 1606
};

1607
static const struct vm_operations_struct i915_gem_vm_ops = {
1608
	.fault = i915_gem_fault,
1609 1610
	.open = drm_gem_vm_open,
	.close = drm_gem_vm_close,
1611 1612
};

1613 1614 1615 1616 1617 1618 1619 1620 1621 1622 1623 1624 1625 1626
static const struct file_operations i915_driver_fops = {
	.owner = THIS_MODULE,
	.open = drm_open,
	.release = drm_release,
	.unlocked_ioctl = drm_ioctl,
	.mmap = drm_gem_mmap,
	.poll = drm_poll,
	.read = drm_read,
#ifdef CONFIG_COMPAT
	.compat_ioctl = i915_compat_ioctl,
#endif
	.llseek = noop_llseek,
};

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static struct drm_driver driver = {
1628 1629
	/* Don't use MTRRs here; the Xserver or userspace app should
	 * deal with them for Intel hardware.
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	 */
1631
	.driver_features =
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	    DRIVER_USE_AGP |
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	    DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM | DRIVER_PRIME |
	    DRIVER_RENDER,
1635
	.load = i915_driver_load,
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	.unload = i915_driver_unload,
1637
	.open = i915_driver_open,
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	.lastclose = i915_driver_lastclose,
	.preclose = i915_driver_preclose,
1640
	.postclose = i915_driver_postclose,
1641
	.set_busid = drm_pci_set_busid,
1642 1643 1644

	/* Used in place of i915_pm_ops for non-DRIVER_MODESET */
	.suspend = i915_suspend,
1645
	.resume = i915_resume_legacy,
1646

1647
	.device_is_agp = i915_driver_device_is_agp,
1648 1649
	.master_create = i915_master_create,
	.master_destroy = i915_master_destroy,
1650
#if defined(CONFIG_DEBUG_FS)
1651 1652
	.debugfs_init = i915_debugfs_init,
	.debugfs_cleanup = i915_debugfs_cleanup,
1653
#endif
1654
	.gem_free_object = i915_gem_free_object,
1655
	.gem_vm_ops = &i915_gem_vm_ops,
1656 1657 1658 1659 1660 1661

	.prime_handle_to_fd = drm_gem_prime_handle_to_fd,
	.prime_fd_to_handle = drm_gem_prime_fd_to_handle,
	.gem_prime_export = i915_gem_prime_export,
	.gem_prime_import = i915_gem_prime_import,

1662 1663
	.dumb_create = i915_gem_dumb_create,
	.dumb_map_offset = i915_gem_mmap_gtt,
1664
	.dumb_destroy = drm_gem_dumb_destroy,
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	.ioctls = i915_ioctls,
1666
	.fops = &i915_driver_fops,
1667 1668 1669 1670 1671 1672
	.name = DRIVER_NAME,
	.desc = DRIVER_DESC,
	.date = DRIVER_DATE,
	.major = DRIVER_MAJOR,
	.minor = DRIVER_MINOR,
	.patchlevel = DRIVER_PATCHLEVEL,
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};

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static struct pci_driver i915_pci_driver = {
	.name = DRIVER_NAME,
	.id_table = pciidlist,
	.probe = i915_pci_probe,
	.remove = i915_pci_remove,
	.driver.pm = &i915_pm_ops,
};

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static int __init i915_init(void)
{
	driver.num_ioctls = i915_max_ioctl;
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	/*
	 * If CONFIG_DRM_I915_KMS is set, default to KMS unless
	 * explicitly disabled with the module pararmeter.
	 *
	 * Otherwise, just follow the parameter (defaulting to off).
	 *
	 * Allow optional vga_text_mode_force boot option to override
	 * the default behavior.
	 */
#if defined(CONFIG_DRM_I915_KMS)
1697
	if (i915.modeset != 0)
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		driver.driver_features |= DRIVER_MODESET;
#endif
1700
	if (i915.modeset == 1)
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		driver.driver_features |= DRIVER_MODESET;

#ifdef CONFIG_VGA_CONSOLE
1704
	if (vgacon_text_force() && i915.modeset == -1)
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		driver.driver_features &= ~DRIVER_MODESET;
#endif

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	if (!(driver.driver_features & DRIVER_MODESET)) {
1709
		driver.get_vblank_timestamp = NULL;
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#ifndef CONFIG_DRM_I915_UMS
		/* Silently fail loading to not upset userspace. */
1712
		DRM_DEBUG_DRIVER("KMS and UMS disabled.\n");
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		return 0;
#endif
	}
1716

1717
	return drm_pci_init(&driver, &i915_pci_driver);
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}

static void __exit i915_exit(void)
{
1722 1723 1724 1725 1726
#ifndef CONFIG_DRM_I915_UMS
	if (!(driver.driver_features & DRIVER_MODESET))
		return; /* Never loaded a driver. */
#endif

1727
	drm_pci_exit(&driver, &i915_pci_driver);
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}

module_init(i915_init);
module_exit(i915_exit);

1733
MODULE_AUTHOR("Tungsten Graphics, Inc.");
1734
MODULE_AUTHOR("Intel Corporation");
1735

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MODULE_DESCRIPTION(DRIVER_DESC);
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MODULE_LICENSE("GPL and additional rights");