pci-ioda.c 95.0 KB
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/*
 * Support PCI/PCIe on PowerNV platforms
 *
 * Copyright 2011 Benjamin Herrenschmidt, IBM Corp.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version
 * 2 of the License, or (at your option) any later version.
 */

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#undef DEBUG
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#include <linux/kernel.h>
#include <linux/pci.h>
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#include <linux/crash_dump.h>
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#include <linux/debugfs.h>
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#include <linux/delay.h>
#include <linux/string.h>
#include <linux/init.h>
#include <linux/bootmem.h>
#include <linux/irq.h>
#include <linux/io.h>
#include <linux/msi.h>
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#include <linux/memblock.h>
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#include <linux/iommu.h>
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#include <linux/rculist.h>
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#include <linux/sizes.h>
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#include <asm/sections.h>
#include <asm/io.h>
#include <asm/prom.h>
#include <asm/pci-bridge.h>
#include <asm/machdep.h>
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#include <asm/msi_bitmap.h>
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#include <asm/ppc-pci.h>
#include <asm/opal.h>
#include <asm/iommu.h>
#include <asm/tce.h>
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#include <asm/xics.h>
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#include <asm/debug.h>
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#include <asm/firmware.h>
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#include <asm/pnv-pci.h>
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#include <asm/mmzone.h>
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#include <misc/cxl-base.h>
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#include "powernv.h"
#include "pci.h"

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#define PNV_IODA1_M64_NUM	16	/* Number of M64 BARs	*/
#define PNV_IODA1_M64_SEGS	8	/* Segments per M64 BAR	*/
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#define PNV_IODA1_DMA32_SEGSIZE	0x10000000
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#define POWERNV_IOMMU_DEFAULT_LEVELS	1
#define POWERNV_IOMMU_MAX_LEVELS	5

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static void pnv_pci_ioda2_table_free_pages(struct iommu_table *tbl);

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static void pe_level_printk(const struct pnv_ioda_pe *pe, const char *level,
			    const char *fmt, ...)
{
	struct va_format vaf;
	va_list args;
	char pfix[32];

	va_start(args, fmt);

	vaf.fmt = fmt;
	vaf.va = &args;

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	if (pe->flags & PNV_IODA_PE_DEV)
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		strlcpy(pfix, dev_name(&pe->pdev->dev), sizeof(pfix));
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	else if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL))
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		sprintf(pfix, "%04x:%02x     ",
			pci_domain_nr(pe->pbus), pe->pbus->number);
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#ifdef CONFIG_PCI_IOV
	else if (pe->flags & PNV_IODA_PE_VF)
		sprintf(pfix, "%04x:%02x:%2x.%d",
			pci_domain_nr(pe->parent_dev->bus),
			(pe->rid & 0xff00) >> 8,
			PCI_SLOT(pe->rid), PCI_FUNC(pe->rid));
#endif /* CONFIG_PCI_IOV*/
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	printk("%spci %s: [PE# %.3d] %pV",
	       level, pfix, pe->pe_number, &vaf);

	va_end(args);
}
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#define pe_err(pe, fmt, ...)					\
	pe_level_printk(pe, KERN_ERR, fmt, ##__VA_ARGS__)
#define pe_warn(pe, fmt, ...)					\
	pe_level_printk(pe, KERN_WARNING, fmt, ##__VA_ARGS__)
#define pe_info(pe, fmt, ...)					\
	pe_level_printk(pe, KERN_INFO, fmt, ##__VA_ARGS__)
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static bool pnv_iommu_bypass_disabled __read_mostly;

static int __init iommu_setup(char *str)
{
	if (!str)
		return -EINVAL;

	while (*str) {
		if (!strncmp(str, "nobypass", 8)) {
			pnv_iommu_bypass_disabled = true;
			pr_info("PowerNV: IOMMU bypass window disabled.\n");
			break;
		}
		str += strcspn(str, ",");
		if (*str == ',')
			str++;
	}

	return 0;
}
early_param("iommu", iommu_setup);

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static inline bool pnv_pci_is_mem_pref_64(unsigned long flags)
{
	return ((flags & (IORESOURCE_MEM_64 | IORESOURCE_PREFETCH)) ==
		(IORESOURCE_MEM_64 | IORESOURCE_PREFETCH));
}

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static void pnv_ioda_reserve_pe(struct pnv_phb *phb, int pe_no)
{
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	if (!(pe_no >= 0 && pe_no < phb->ioda.total_pe_num)) {
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		pr_warn("%s: Invalid PE %d on PHB#%x\n",
			__func__, pe_no, phb->hose->global_number);
		return;
	}

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	if (test_and_set_bit(pe_no, phb->ioda.pe_alloc))
		pr_debug("%s: PE %d was reserved on PHB#%x\n",
			 __func__, pe_no, phb->hose->global_number);
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	phb->ioda.pe_array[pe_no].phb = phb;
	phb->ioda.pe_array[pe_no].pe_number = pe_no;
}

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static unsigned int pnv_ioda_alloc_pe(struct pnv_phb *phb)
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{
	unsigned long pe;

	do {
		pe = find_next_zero_bit(phb->ioda.pe_alloc,
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					phb->ioda.total_pe_num, 0);
		if (pe >= phb->ioda.total_pe_num)
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			return IODA_INVALID_PE;
	} while(test_and_set_bit(pe, phb->ioda.pe_alloc));

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	phb->ioda.pe_array[pe].phb = phb;
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	phb->ioda.pe_array[pe].pe_number = pe;
	return pe;
}

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static void pnv_ioda_free_pe(struct pnv_phb *phb, int pe)
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{
	WARN_ON(phb->ioda.pe_array[pe].pdev);

	memset(&phb->ioda.pe_array[pe], 0, sizeof(struct pnv_ioda_pe));
	clear_bit(pe, phb->ioda.pe_alloc);
}

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/* The default M64 BAR is shared by all PEs */
static int pnv_ioda2_init_m64(struct pnv_phb *phb)
{
	const char *desc;
	struct resource *r;
	s64 rc;

	/* Configure the default M64 BAR */
	rc = opal_pci_set_phb_mem_window(phb->opal_id,
					 OPAL_M64_WINDOW_TYPE,
					 phb->ioda.m64_bar_idx,
					 phb->ioda.m64_base,
					 0, /* unused */
					 phb->ioda.m64_size);
	if (rc != OPAL_SUCCESS) {
		desc = "configuring";
		goto fail;
	}

	/* Enable the default M64 BAR */
	rc = opal_pci_phb_mmio_enable(phb->opal_id,
				      OPAL_M64_WINDOW_TYPE,
				      phb->ioda.m64_bar_idx,
				      OPAL_ENABLE_M64_SPLIT);
	if (rc != OPAL_SUCCESS) {
		desc = "enabling";
		goto fail;
	}

	/* Mark the M64 BAR assigned */
	set_bit(phb->ioda.m64_bar_idx, &phb->ioda.m64_bar_alloc);

	/*
	 * Strip off the segment used by the reserved PE, which is
	 * expected to be 0 or last one of PE capabicity.
	 */
	r = &phb->hose->mem_resources[1];
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	if (phb->ioda.reserved_pe_idx == 0)
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		r->start += phb->ioda.m64_segsize;
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	else if (phb->ioda.reserved_pe_idx == (phb->ioda.total_pe_num - 1))
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		r->end -= phb->ioda.m64_segsize;
	else
		pr_warn("  Cannot strip M64 segment for reserved PE#%d\n",
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			phb->ioda.reserved_pe_idx);
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	return 0;

fail:
	pr_warn("  Failure %lld %s M64 BAR#%d\n",
		rc, desc, phb->ioda.m64_bar_idx);
	opal_pci_phb_mmio_enable(phb->opal_id,
				 OPAL_M64_WINDOW_TYPE,
				 phb->ioda.m64_bar_idx,
				 OPAL_DISABLE_M64);
	return -EIO;
}

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static void pnv_ioda_reserve_dev_m64_pe(struct pci_dev *pdev,
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					 unsigned long *pe_bitmap)
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{
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	struct pci_controller *hose = pci_bus_to_host(pdev->bus);
	struct pnv_phb *phb = hose->private_data;
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	struct resource *r;
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	resource_size_t base, sgsz, start, end;
	int segno, i;

	base = phb->ioda.m64_base;
	sgsz = phb->ioda.m64_segsize;
	for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
		r = &pdev->resource[i];
		if (!r->parent || !pnv_pci_is_mem_pref_64(r->flags))
			continue;
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		start = _ALIGN_DOWN(r->start - base, sgsz);
		end = _ALIGN_UP(r->end - base, sgsz);
		for (segno = start / sgsz; segno < end / sgsz; segno++) {
			if (pe_bitmap)
				set_bit(segno, pe_bitmap);
			else
				pnv_ioda_reserve_pe(phb, segno);
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		}
	}
}

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static int pnv_ioda1_init_m64(struct pnv_phb *phb)
{
	struct resource *r;
	int index;

	/*
	 * There are 16 M64 BARs, each of which has 8 segments. So
	 * there are as many M64 segments as the maximum number of
	 * PEs, which is 128.
	 */
	for (index = 0; index < PNV_IODA1_M64_NUM; index++) {
		unsigned long base, segsz = phb->ioda.m64_segsize;
		int64_t rc;

		base = phb->ioda.m64_base +
		       index * PNV_IODA1_M64_SEGS * segsz;
		rc = opal_pci_set_phb_mem_window(phb->opal_id,
				OPAL_M64_WINDOW_TYPE, index, base, 0,
				PNV_IODA1_M64_SEGS * segsz);
		if (rc != OPAL_SUCCESS) {
			pr_warn("  Error %lld setting M64 PHB#%d-BAR#%d\n",
				rc, phb->hose->global_number, index);
			goto fail;
		}

		rc = opal_pci_phb_mmio_enable(phb->opal_id,
				OPAL_M64_WINDOW_TYPE, index,
				OPAL_ENABLE_M64_SPLIT);
		if (rc != OPAL_SUCCESS) {
			pr_warn("  Error %lld enabling M64 PHB#%d-BAR#%d\n",
				rc, phb->hose->global_number, index);
			goto fail;
		}
	}

	/*
	 * Exclude the segment used by the reserved PE, which
	 * is expected to be 0 or last supported PE#.
	 */
	r = &phb->hose->mem_resources[1];
	if (phb->ioda.reserved_pe_idx == 0)
		r->start += phb->ioda.m64_segsize;
	else if (phb->ioda.reserved_pe_idx == (phb->ioda.total_pe_num - 1))
		r->end -= phb->ioda.m64_segsize;
	else
		WARN(1, "Wrong reserved PE#%d on PHB#%d\n",
		     phb->ioda.reserved_pe_idx, phb->hose->global_number);

	return 0;

fail:
	for ( ; index >= 0; index--)
		opal_pci_phb_mmio_enable(phb->opal_id,
			OPAL_M64_WINDOW_TYPE, index, OPAL_DISABLE_M64);

	return -EIO;
}

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static void pnv_ioda_reserve_m64_pe(struct pci_bus *bus,
				    unsigned long *pe_bitmap,
				    bool all)
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{
	struct pci_dev *pdev;
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	list_for_each_entry(pdev, &bus->devices, bus_list) {
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		pnv_ioda_reserve_dev_m64_pe(pdev, pe_bitmap);
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		if (all && pdev->subordinate)
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			pnv_ioda_reserve_m64_pe(pdev->subordinate,
						pe_bitmap, all);
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	}
}

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static unsigned int pnv_ioda_pick_m64_pe(struct pci_bus *bus, bool all)
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{
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	struct pci_controller *hose = pci_bus_to_host(bus);
	struct pnv_phb *phb = hose->private_data;
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	struct pnv_ioda_pe *master_pe, *pe;
	unsigned long size, *pe_alloc;
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	int i;
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	/* Root bus shouldn't use M64 */
	if (pci_is_root_bus(bus))
		return IODA_INVALID_PE;

	/* Allocate bitmap */
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	size = _ALIGN_UP(phb->ioda.total_pe_num / 8, sizeof(unsigned long));
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	pe_alloc = kzalloc(size, GFP_KERNEL);
	if (!pe_alloc) {
		pr_warn("%s: Out of memory !\n",
			__func__);
		return IODA_INVALID_PE;
	}

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	/* Figure out reserved PE numbers by the PE */
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	pnv_ioda_reserve_m64_pe(bus, pe_alloc, all);
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	/*
	 * the current bus might not own M64 window and that's all
	 * contributed by its child buses. For the case, we needn't
	 * pick M64 dependent PE#.
	 */
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	if (bitmap_empty(pe_alloc, phb->ioda.total_pe_num)) {
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		kfree(pe_alloc);
		return IODA_INVALID_PE;
	}

	/*
	 * Figure out the master PE and put all slave PEs to master
	 * PE's list to form compound PE.
	 */
	master_pe = NULL;
	i = -1;
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	while ((i = find_next_bit(pe_alloc, phb->ioda.total_pe_num, i + 1)) <
		phb->ioda.total_pe_num) {
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		pe = &phb->ioda.pe_array[i];

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		phb->ioda.m64_segmap[pe->pe_number] = pe->pe_number;
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		if (!master_pe) {
			pe->flags |= PNV_IODA_PE_MASTER;
			INIT_LIST_HEAD(&pe->slaves);
			master_pe = pe;
		} else {
			pe->flags |= PNV_IODA_PE_SLAVE;
			pe->master = master_pe;
			list_add_tail(&pe->list, &master_pe->slaves);
		}
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		/*
		 * P7IOC supports M64DT, which helps mapping M64 segment
		 * to one particular PE#. However, PHB3 has fixed mapping
		 * between M64 segment and PE#. In order to have same logic
		 * for P7IOC and PHB3, we enforce fixed mapping between M64
		 * segment and PE# on P7IOC.
		 */
		if (phb->type == PNV_PHB_IODA1) {
			int64_t rc;

			rc = opal_pci_map_pe_mmio_window(phb->opal_id,
					pe->pe_number, OPAL_M64_WINDOW_TYPE,
					pe->pe_number / PNV_IODA1_M64_SEGS,
					pe->pe_number % PNV_IODA1_M64_SEGS);
			if (rc != OPAL_SUCCESS)
				pr_warn("%s: Error %lld mapping M64 for PHB#%d-PE#%d\n",
					__func__, rc, phb->hose->global_number,
					pe->pe_number);
		}
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	}

	kfree(pe_alloc);
	return master_pe->pe_number;
}

static void __init pnv_ioda_parse_m64_window(struct pnv_phb *phb)
{
	struct pci_controller *hose = phb->hose;
	struct device_node *dn = hose->dn;
	struct resource *res;
	const u32 *r;
	u64 pci_addr;

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	if (phb->type != PNV_PHB_IODA1 && phb->type != PNV_PHB_IODA2) {
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		pr_info("  Not support M64 window\n");
		return;
	}

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	if (!firmware_has_feature(FW_FEATURE_OPAL)) {
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		pr_info("  Firmware too old to support M64 window\n");
		return;
	}

	r = of_get_property(dn, "ibm,opal-m64-window", NULL);
	if (!r) {
		pr_info("  No <ibm,opal-m64-window> on %s\n",
			dn->full_name);
		return;
	}

	res = &hose->mem_resources[1];
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	res->name = dn->full_name;
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	res->start = of_translate_address(dn, r + 2);
	res->end = res->start + of_read_number(r + 4, 2) - 1;
	res->flags = (IORESOURCE_MEM | IORESOURCE_MEM_64 | IORESOURCE_PREFETCH);
	pci_addr = of_read_number(r, 2);
	hose->mem_offset[1] = res->start - pci_addr;

	phb->ioda.m64_size = resource_size(res);
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	phb->ioda.m64_segsize = phb->ioda.m64_size / phb->ioda.total_pe_num;
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	phb->ioda.m64_base = pci_addr;

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	pr_info(" MEM64 0x%016llx..0x%016llx -> 0x%016llx\n",
			res->start, res->end, pci_addr);

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	/* Use last M64 BAR to cover M64 window */
	phb->ioda.m64_bar_idx = 15;
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	if (phb->type == PNV_PHB_IODA1)
		phb->init_m64 = pnv_ioda1_init_m64;
	else
		phb->init_m64 = pnv_ioda2_init_m64;
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	phb->reserve_m64_pe = pnv_ioda_reserve_m64_pe;
	phb->pick_m64_pe = pnv_ioda_pick_m64_pe;
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}

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static void pnv_ioda_freeze_pe(struct pnv_phb *phb, int pe_no)
{
	struct pnv_ioda_pe *pe = &phb->ioda.pe_array[pe_no];
	struct pnv_ioda_pe *slave;
	s64 rc;

	/* Fetch master PE */
	if (pe->flags & PNV_IODA_PE_SLAVE) {
		pe = pe->master;
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		if (WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER)))
			return;

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		pe_no = pe->pe_number;
	}

	/* Freeze master PE */
	rc = opal_pci_eeh_freeze_set(phb->opal_id,
				     pe_no,
				     OPAL_EEH_ACTION_SET_FREEZE_ALL);
	if (rc != OPAL_SUCCESS) {
		pr_warn("%s: Failure %lld freezing PHB#%x-PE#%x\n",
			__func__, rc, phb->hose->global_number, pe_no);
		return;
	}

	/* Freeze slave PEs */
	if (!(pe->flags & PNV_IODA_PE_MASTER))
		return;

	list_for_each_entry(slave, &pe->slaves, list) {
		rc = opal_pci_eeh_freeze_set(phb->opal_id,
					     slave->pe_number,
					     OPAL_EEH_ACTION_SET_FREEZE_ALL);
		if (rc != OPAL_SUCCESS)
			pr_warn("%s: Failure %lld freezing PHB#%x-PE#%x\n",
				__func__, rc, phb->hose->global_number,
				slave->pe_number);
	}
}

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static int pnv_ioda_unfreeze_pe(struct pnv_phb *phb, int pe_no, int opt)
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{
	struct pnv_ioda_pe *pe, *slave;
	s64 rc;

	/* Find master PE */
	pe = &phb->ioda.pe_array[pe_no];
	if (pe->flags & PNV_IODA_PE_SLAVE) {
		pe = pe->master;
		WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER));
		pe_no = pe->pe_number;
	}

	/* Clear frozen state for master PE */
	rc = opal_pci_eeh_freeze_clear(phb->opal_id, pe_no, opt);
	if (rc != OPAL_SUCCESS) {
		pr_warn("%s: Failure %lld clear %d on PHB#%x-PE#%x\n",
			__func__, rc, opt, phb->hose->global_number, pe_no);
		return -EIO;
	}

	if (!(pe->flags & PNV_IODA_PE_MASTER))
		return 0;

	/* Clear frozen state for slave PEs */
	list_for_each_entry(slave, &pe->slaves, list) {
		rc = opal_pci_eeh_freeze_clear(phb->opal_id,
					     slave->pe_number,
					     opt);
		if (rc != OPAL_SUCCESS) {
			pr_warn("%s: Failure %lld clear %d on PHB#%x-PE#%x\n",
				__func__, rc, opt, phb->hose->global_number,
				slave->pe_number);
			return -EIO;
		}
	}

	return 0;
}

static int pnv_ioda_get_pe_state(struct pnv_phb *phb, int pe_no)
{
	struct pnv_ioda_pe *slave, *pe;
	u8 fstate, state;
	__be16 pcierr;
	s64 rc;

	/* Sanity check on PE number */
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	if (pe_no < 0 || pe_no >= phb->ioda.total_pe_num)
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		return OPAL_EEH_STOPPED_PERM_UNAVAIL;

	/*
	 * Fetch the master PE and the PE instance might be
	 * not initialized yet.
	 */
	pe = &phb->ioda.pe_array[pe_no];
	if (pe->flags & PNV_IODA_PE_SLAVE) {
		pe = pe->master;
		WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER));
		pe_no = pe->pe_number;
	}

	/* Check the master PE */
	rc = opal_pci_eeh_freeze_status(phb->opal_id, pe_no,
					&state, &pcierr, NULL);
	if (rc != OPAL_SUCCESS) {
		pr_warn("%s: Failure %lld getting "
			"PHB#%x-PE#%x state\n",
			__func__, rc,
			phb->hose->global_number, pe_no);
		return OPAL_EEH_STOPPED_TEMP_UNAVAIL;
	}

	/* Check the slave PE */
	if (!(pe->flags & PNV_IODA_PE_MASTER))
		return state;

	list_for_each_entry(slave, &pe->slaves, list) {
		rc = opal_pci_eeh_freeze_status(phb->opal_id,
						slave->pe_number,
						&fstate,
						&pcierr,
						NULL);
		if (rc != OPAL_SUCCESS) {
			pr_warn("%s: Failure %lld getting "
				"PHB#%x-PE#%x state\n",
				__func__, rc,
				phb->hose->global_number, slave->pe_number);
			return OPAL_EEH_STOPPED_TEMP_UNAVAIL;
		}

		/*
		 * Override the result based on the ascending
		 * priority.
		 */
		if (fstate > state)
			state = fstate;
	}

	return state;
}

595 596 597 598
/* Currently those 2 are only used when MSIs are enabled, this will change
 * but in the meantime, we need to protect them to avoid warnings
 */
#ifdef CONFIG_PCI_MSI
599
static struct pnv_ioda_pe *pnv_ioda_get_pe(struct pci_dev *dev)
600 601 602
{
	struct pci_controller *hose = pci_bus_to_host(dev->bus);
	struct pnv_phb *phb = hose->private_data;
603
	struct pci_dn *pdn = pci_get_pdn(dev);
604 605 606 607 608 609 610 611 612

	if (!pdn)
		return NULL;
	if (pdn->pe_number == IODA_INVALID_PE)
		return NULL;
	return &phb->ioda.pe_array[pdn->pe_number];
}
#endif /* CONFIG_PCI_MSI */

613 614 615 616 617 618 619 620 621 622 623 624 625 626 627 628 629 630 631 632 633 634 635 636 637 638 639 640 641 642 643 644 645 646 647 648 649 650 651 652 653 654
static int pnv_ioda_set_one_peltv(struct pnv_phb *phb,
				  struct pnv_ioda_pe *parent,
				  struct pnv_ioda_pe *child,
				  bool is_add)
{
	const char *desc = is_add ? "adding" : "removing";
	uint8_t op = is_add ? OPAL_ADD_PE_TO_DOMAIN :
			      OPAL_REMOVE_PE_FROM_DOMAIN;
	struct pnv_ioda_pe *slave;
	long rc;

	/* Parent PE affects child PE */
	rc = opal_pci_set_peltv(phb->opal_id, parent->pe_number,
				child->pe_number, op);
	if (rc != OPAL_SUCCESS) {
		pe_warn(child, "OPAL error %ld %s to parent PELTV\n",
			rc, desc);
		return -ENXIO;
	}

	if (!(child->flags & PNV_IODA_PE_MASTER))
		return 0;

	/* Compound case: parent PE affects slave PEs */
	list_for_each_entry(slave, &child->slaves, list) {
		rc = opal_pci_set_peltv(phb->opal_id, parent->pe_number,
					slave->pe_number, op);
		if (rc != OPAL_SUCCESS) {
			pe_warn(slave, "OPAL error %ld %s to parent PELTV\n",
				rc, desc);
			return -ENXIO;
		}
	}

	return 0;
}

static int pnv_ioda_set_peltv(struct pnv_phb *phb,
			      struct pnv_ioda_pe *pe,
			      bool is_add)
{
	struct pnv_ioda_pe *slave;
655
	struct pci_dev *pdev = NULL;
656 657 658 659 660 661 662 663 664 665 666 667 668 669 670 671 672 673 674 675 676 677 678 679 680 681 682 683 684 685 686 687 688 689 690 691 692 693
	int ret;

	/*
	 * Clear PE frozen state. If it's master PE, we need
	 * clear slave PE frozen state as well.
	 */
	if (is_add) {
		opal_pci_eeh_freeze_clear(phb->opal_id, pe->pe_number,
					  OPAL_EEH_ACTION_CLEAR_FREEZE_ALL);
		if (pe->flags & PNV_IODA_PE_MASTER) {
			list_for_each_entry(slave, &pe->slaves, list)
				opal_pci_eeh_freeze_clear(phb->opal_id,
							  slave->pe_number,
							  OPAL_EEH_ACTION_CLEAR_FREEZE_ALL);
		}
	}

	/*
	 * Associate PE in PELT. We need add the PE into the
	 * corresponding PELT-V as well. Otherwise, the error
	 * originated from the PE might contribute to other
	 * PEs.
	 */
	ret = pnv_ioda_set_one_peltv(phb, pe, pe, is_add);
	if (ret)
		return ret;

	/* For compound PEs, any one affects all of them */
	if (pe->flags & PNV_IODA_PE_MASTER) {
		list_for_each_entry(slave, &pe->slaves, list) {
			ret = pnv_ioda_set_one_peltv(phb, slave, pe, is_add);
			if (ret)
				return ret;
		}
	}

	if (pe->flags & (PNV_IODA_PE_BUS_ALL | PNV_IODA_PE_BUS))
		pdev = pe->pbus->self;
694
	else if (pe->flags & PNV_IODA_PE_DEV)
695
		pdev = pe->pdev->bus->self;
696 697
#ifdef CONFIG_PCI_IOV
	else if (pe->flags & PNV_IODA_PE_VF)
698
		pdev = pe->parent_dev;
699
#endif /* CONFIG_PCI_IOV */
700 701 702 703 704 705 706 707 708 709 710 711 712 713 714 715 716
	while (pdev) {
		struct pci_dn *pdn = pci_get_pdn(pdev);
		struct pnv_ioda_pe *parent;

		if (pdn && pdn->pe_number != IODA_INVALID_PE) {
			parent = &phb->ioda.pe_array[pdn->pe_number];
			ret = pnv_ioda_set_one_peltv(phb, parent, pe, is_add);
			if (ret)
				return ret;
		}

		pdev = pdev->bus->self;
	}

	return 0;
}

717 718 719 720 721 722 723 724 725 726 727 728 729 730 731 732 733 734 735 736 737 738 739 740 741 742 743 744 745 746 747 748 749 750 751 752 753 754 755 756 757 758 759 760 761 762 763 764 765 766 767 768 769 770 771 772 773 774 775 776
#ifdef CONFIG_PCI_IOV
static int pnv_ioda_deconfigure_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe)
{
	struct pci_dev *parent;
	uint8_t bcomp, dcomp, fcomp;
	int64_t rc;
	long rid_end, rid;

	/* Currently, we just deconfigure VF PE. Bus PE will always there.*/
	if (pe->pbus) {
		int count;

		dcomp = OPAL_IGNORE_RID_DEVICE_NUMBER;
		fcomp = OPAL_IGNORE_RID_FUNCTION_NUMBER;
		parent = pe->pbus->self;
		if (pe->flags & PNV_IODA_PE_BUS_ALL)
			count = pe->pbus->busn_res.end - pe->pbus->busn_res.start + 1;
		else
			count = 1;

		switch(count) {
		case  1: bcomp = OpalPciBusAll;         break;
		case  2: bcomp = OpalPciBus7Bits;       break;
		case  4: bcomp = OpalPciBus6Bits;       break;
		case  8: bcomp = OpalPciBus5Bits;       break;
		case 16: bcomp = OpalPciBus4Bits;       break;
		case 32: bcomp = OpalPciBus3Bits;       break;
		default:
			dev_err(&pe->pbus->dev, "Number of subordinate buses %d unsupported\n",
			        count);
			/* Do an exact match only */
			bcomp = OpalPciBusAll;
		}
		rid_end = pe->rid + (count << 8);
	} else {
		if (pe->flags & PNV_IODA_PE_VF)
			parent = pe->parent_dev;
		else
			parent = pe->pdev->bus->self;
		bcomp = OpalPciBusAll;
		dcomp = OPAL_COMPARE_RID_DEVICE_NUMBER;
		fcomp = OPAL_COMPARE_RID_FUNCTION_NUMBER;
		rid_end = pe->rid + 1;
	}

	/* Clear the reverse map */
	for (rid = pe->rid; rid < rid_end; rid++)
		phb->ioda.pe_rmap[rid] = 0;

	/* Release from all parents PELT-V */
	while (parent) {
		struct pci_dn *pdn = pci_get_pdn(parent);
		if (pdn && pdn->pe_number != IODA_INVALID_PE) {
			rc = opal_pci_set_peltv(phb->opal_id, pdn->pe_number,
						pe->pe_number, OPAL_REMOVE_PE_FROM_DOMAIN);
			/* XXX What to do in case of error ? */
		}
		parent = parent->bus->self;
	}

777
	opal_pci_eeh_freeze_clear(phb->opal_id, pe->pe_number,
778 779 780 781 782 783 784 785 786 787 788 789 790 791 792 793 794 795 796 797
				  OPAL_EEH_ACTION_CLEAR_FREEZE_ALL);

	/* Disassociate PE in PELT */
	rc = opal_pci_set_peltv(phb->opal_id, pe->pe_number,
				pe->pe_number, OPAL_REMOVE_PE_FROM_DOMAIN);
	if (rc)
		pe_warn(pe, "OPAL error %ld remove self from PELTV\n", rc);
	rc = opal_pci_set_pe(phb->opal_id, pe->pe_number, pe->rid,
			     bcomp, dcomp, fcomp, OPAL_UNMAP_PE);
	if (rc)
		pe_err(pe, "OPAL error %ld trying to setup PELT table\n", rc);

	pe->pbus = NULL;
	pe->pdev = NULL;
	pe->parent_dev = NULL;

	return 0;
}
#endif /* CONFIG_PCI_IOV */

798
static int pnv_ioda_configure_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe)
799 800 801 802 803 804 805 806 807 808 809 810
{
	struct pci_dev *parent;
	uint8_t bcomp, dcomp, fcomp;
	long rc, rid_end, rid;

	/* Bus validation ? */
	if (pe->pbus) {
		int count;

		dcomp = OPAL_IGNORE_RID_DEVICE_NUMBER;
		fcomp = OPAL_IGNORE_RID_FUNCTION_NUMBER;
		parent = pe->pbus->self;
811 812 813 814 815
		if (pe->flags & PNV_IODA_PE_BUS_ALL)
			count = pe->pbus->busn_res.end - pe->pbus->busn_res.start + 1;
		else
			count = 1;

816 817 818 819 820 821 822 823
		switch(count) {
		case  1: bcomp = OpalPciBusAll;		break;
		case  2: bcomp = OpalPciBus7Bits;	break;
		case  4: bcomp = OpalPciBus6Bits;	break;
		case  8: bcomp = OpalPciBus5Bits;	break;
		case 16: bcomp = OpalPciBus4Bits;	break;
		case 32: bcomp = OpalPciBus3Bits;	break;
		default:
824 825
			dev_err(&pe->pbus->dev, "Number of subordinate buses %d unsupported\n",
			        count);
826 827 828 829 830
			/* Do an exact match only */
			bcomp = OpalPciBusAll;
		}
		rid_end = pe->rid + (count << 8);
	} else {
831 832 833 834 835 836
#ifdef CONFIG_PCI_IOV
		if (pe->flags & PNV_IODA_PE_VF)
			parent = pe->parent_dev;
		else
#endif /* CONFIG_PCI_IOV */
			parent = pe->pdev->bus->self;
837 838 839 840 841 842
		bcomp = OpalPciBusAll;
		dcomp = OPAL_COMPARE_RID_DEVICE_NUMBER;
		fcomp = OPAL_COMPARE_RID_FUNCTION_NUMBER;
		rid_end = pe->rid + 1;
	}

843 844 845 846 847 848
	/*
	 * Associate PE in PELT. We need add the PE into the
	 * corresponding PELT-V as well. Otherwise, the error
	 * originated from the PE might contribute to other
	 * PEs.
	 */
849 850 851 852 853 854
	rc = opal_pci_set_pe(phb->opal_id, pe->pe_number, pe->rid,
			     bcomp, dcomp, fcomp, OPAL_MAP_PE);
	if (rc) {
		pe_err(pe, "OPAL error %ld trying to setup PELT table\n", rc);
		return -ENXIO;
	}
855

856 857 858 859 860 861
	/*
	 * Configure PELTV. NPUs don't have a PELTV table so skip
	 * configuration on them.
	 */
	if (phb->type != PNV_PHB_NPU)
		pnv_ioda_set_peltv(phb, pe, true);
862 863 864 865 866 867

	/* Setup reverse map */
	for (rid = pe->rid; rid < rid_end; rid++)
		phb->ioda.pe_rmap[rid] = pe->pe_number;

	/* Setup one MVTs on IODA1 */
868 869 870 871 872 873 874 875 876 877 878 879 880 881
	if (phb->type != PNV_PHB_IODA1) {
		pe->mve_number = 0;
		goto out;
	}

	pe->mve_number = pe->pe_number;
	rc = opal_pci_set_mve(phb->opal_id, pe->mve_number, pe->pe_number);
	if (rc != OPAL_SUCCESS) {
		pe_err(pe, "OPAL error %ld setting up MVE %d\n",
		       rc, pe->mve_number);
		pe->mve_number = -1;
	} else {
		rc = opal_pci_set_mve_enable(phb->opal_id,
					     pe->mve_number, OPAL_ENABLE_MVE);
882
		if (rc) {
883
			pe_err(pe, "OPAL error %ld enabling MVE %d\n",
884 885 886
			       rc, pe->mve_number);
			pe->mve_number = -1;
		}
887
	}
888

889
out:
890 891 892
	return 0;
}

893 894 895 896 897 898 899 900 901 902 903 904 905 906 907 908 909 910 911 912 913 914 915 916 917 918 919 920 921 922 923 924 925 926 927 928 929 930 931 932 933 934 935 936 937 938 939 940 941 942 943 944 945 946 947 948 949 950
#ifdef CONFIG_PCI_IOV
static int pnv_pci_vf_resource_shift(struct pci_dev *dev, int offset)
{
	struct pci_dn *pdn = pci_get_pdn(dev);
	int i;
	struct resource *res, res2;
	resource_size_t size;
	u16 num_vfs;

	if (!dev->is_physfn)
		return -EINVAL;

	/*
	 * "offset" is in VFs.  The M64 windows are sized so that when they
	 * are segmented, each segment is the same size as the IOV BAR.
	 * Each segment is in a separate PE, and the high order bits of the
	 * address are the PE number.  Therefore, each VF's BAR is in a
	 * separate PE, and changing the IOV BAR start address changes the
	 * range of PEs the VFs are in.
	 */
	num_vfs = pdn->num_vfs;
	for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
		res = &dev->resource[i + PCI_IOV_RESOURCES];
		if (!res->flags || !res->parent)
			continue;

		/*
		 * The actual IOV BAR range is determined by the start address
		 * and the actual size for num_vfs VFs BAR.  This check is to
		 * make sure that after shifting, the range will not overlap
		 * with another device.
		 */
		size = pci_iov_resource_size(dev, i + PCI_IOV_RESOURCES);
		res2.flags = res->flags;
		res2.start = res->start + (size * offset);
		res2.end = res2.start + (size * num_vfs) - 1;

		if (res2.end > res->end) {
			dev_err(&dev->dev, "VF BAR%d: %pR would extend past %pR (trying to enable %d VFs shifted by %d)\n",
				i, &res2, res, num_vfs, offset);
			return -EBUSY;
		}
	}

	/*
	 * After doing so, there would be a "hole" in the /proc/iomem when
	 * offset is a positive value. It looks like the device return some
	 * mmio back to the system, which actually no one could use it.
	 */
	for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
		res = &dev->resource[i + PCI_IOV_RESOURCES];
		if (!res->flags || !res->parent)
			continue;

		size = pci_iov_resource_size(dev, i + PCI_IOV_RESOURCES);
		res2 = *res;
		res->start += size * offset;

951 952 953
		dev_info(&dev->dev, "VF BAR%d: %pR shifted to %pR (%sabling %d VFs shifted by %d)\n",
			 i, &res2, res, (offset > 0) ? "En" : "Dis",
			 num_vfs, offset);
954 955 956 957 958 959
		pci_update_resource(dev, i + PCI_IOV_RESOURCES);
	}
	return 0;
}
#endif /* CONFIG_PCI_IOV */

960
static struct pnv_ioda_pe *pnv_ioda_setup_dev_PE(struct pci_dev *dev)
961 962 963
{
	struct pci_controller *hose = pci_bus_to_host(dev->bus);
	struct pnv_phb *phb = hose->private_data;
964
	struct pci_dn *pdn = pci_get_pdn(dev);
965
	struct pnv_ioda_pe *pe;
966
	unsigned int pe_num;
967 968 969 970 971 972 973 974 975

	if (!pdn) {
		pr_err("%s: Device tree node not associated properly\n",
			   pci_name(dev));
		return NULL;
	}
	if (pdn->pe_number != IODA_INVALID_PE)
		return NULL;

976
	pe_num = pnv_ioda_alloc_pe(phb);
977 978 979 980 981 982 983 984 985 986 987 988 989 990 991 992 993
	if (pe_num == IODA_INVALID_PE) {
		pr_warning("%s: Not enough PE# available, disabling device\n",
			   pci_name(dev));
		return NULL;
	}

	/* NOTE: We get only one ref to the pci_dev for the pdn, not for the
	 * pointer in the PE data structure, both should be destroyed at the
	 * same time. However, this needs to be looked at more closely again
	 * once we actually start removing things (Hotplug, SR-IOV, ...)
	 *
	 * At some point we want to remove the PDN completely anyways
	 */
	pe = &phb->ioda.pe_array[pe_num];
	pci_dev_get(dev);
	pdn->pcidev = dev;
	pdn->pe_number = pe_num;
994
	pe->flags = PNV_IODA_PE_DEV;
995 996 997 998 999 1000 1001 1002 1003 1004 1005 1006 1007 1008 1009 1010 1011 1012 1013 1014 1015 1016 1017 1018 1019
	pe->pdev = dev;
	pe->pbus = NULL;
	pe->mve_number = -1;
	pe->rid = dev->bus->number << 8 | pdn->devfn;

	pe_info(pe, "Associated device to PE\n");

	if (pnv_ioda_configure_pe(phb, pe)) {
		/* XXX What do we do here ? */
		if (pe_num)
			pnv_ioda_free_pe(phb, pe_num);
		pdn->pe_number = IODA_INVALID_PE;
		pe->pdev = NULL;
		pci_dev_put(dev);
		return NULL;
	}

	return pe;
}

static void pnv_ioda_setup_same_PE(struct pci_bus *bus, struct pnv_ioda_pe *pe)
{
	struct pci_dev *dev;

	list_for_each_entry(dev, &bus->devices, bus_list) {
1020
		struct pci_dn *pdn = pci_get_pdn(dev);
1021 1022 1023 1024 1025 1026

		if (pdn == NULL) {
			pr_warn("%s: No device node associated with device !\n",
				pci_name(dev));
			continue;
		}
1027
		pdn->pcidev = dev;
1028
		pdn->pe_number = pe->pe_number;
1029
		if ((pe->flags & PNV_IODA_PE_BUS_ALL) && dev->subordinate)
1030 1031 1032 1033
			pnv_ioda_setup_same_PE(dev->subordinate, pe);
	}
}

1034 1035 1036 1037 1038 1039
/*
 * There're 2 types of PCI bus sensitive PEs: One that is compromised of
 * single PCI bus. Another one that contains the primary PCI bus and its
 * subordinate PCI devices and buses. The second type of PE is normally
 * orgiriated by PCIe-to-PCI bridge or PLX switch downstream ports.
 */
1040
static void pnv_ioda_setup_bus_PE(struct pci_bus *bus, bool all)
1041
{
1042
	struct pci_controller *hose = pci_bus_to_host(bus);
1043 1044
	struct pnv_phb *phb = hose->private_data;
	struct pnv_ioda_pe *pe;
1045
	unsigned int pe_num = IODA_INVALID_PE;
1046 1047 1048

	/* Check if PE is determined by M64 */
	if (phb->pick_m64_pe)
1049
		pe_num = phb->pick_m64_pe(bus, all);
1050 1051 1052 1053

	/* The PE number isn't pinned by M64 */
	if (pe_num == IODA_INVALID_PE)
		pe_num = pnv_ioda_alloc_pe(phb);
1054 1055

	if (pe_num == IODA_INVALID_PE) {
1056 1057
		pr_warning("%s: Not enough PE# available for PCI bus %04x:%02x\n",
			__func__, pci_domain_nr(bus), bus->number);
1058 1059 1060 1061
		return;
	}

	pe = &phb->ioda.pe_array[pe_num];
1062
	pe->flags |= (all ? PNV_IODA_PE_BUS_ALL : PNV_IODA_PE_BUS);
1063 1064 1065
	pe->pbus = bus;
	pe->pdev = NULL;
	pe->mve_number = -1;
1066
	pe->rid = bus->busn_res.start << 8;
1067

1068 1069 1070 1071 1072 1073
	if (all)
		pe_info(pe, "Secondary bus %d..%d associated with PE#%d\n",
			bus->busn_res.start, bus->busn_res.end, pe_num);
	else
		pe_info(pe, "Secondary bus %d associated with PE#%d\n",
			bus->busn_res.start, pe_num);
1074 1075 1076 1077 1078 1079 1080 1081 1082 1083 1084 1085

	if (pnv_ioda_configure_pe(phb, pe)) {
		/* XXX What do we do here ? */
		if (pe_num)
			pnv_ioda_free_pe(phb, pe_num);
		pe->pbus = NULL;
		return;
	}

	/* Associate it with all child devices */
	pnv_ioda_setup_same_PE(bus, pe);

1086 1087
	/* Put PE to the list */
	list_add_tail(&pe->list, &phb->ioda.pe_list);
1088 1089
}

1090 1091 1092 1093 1094 1095 1096 1097 1098 1099 1100 1101 1102 1103 1104 1105 1106 1107 1108 1109
static struct pnv_ioda_pe *pnv_ioda_setup_npu_PE(struct pci_dev *npu_pdev)
{
	int pe_num, found_pe = false, rc;
	long rid;
	struct pnv_ioda_pe *pe;
	struct pci_dev *gpu_pdev;
	struct pci_dn *npu_pdn;
	struct pci_controller *hose = pci_bus_to_host(npu_pdev->bus);
	struct pnv_phb *phb = hose->private_data;

	/*
	 * Due to a hardware errata PE#0 on the NPU is reserved for
	 * error handling. This means we only have three PEs remaining
	 * which need to be assigned to four links, implying some
	 * links must share PEs.
	 *
	 * To achieve this we assign PEs such that NPUs linking the
	 * same GPU get assigned the same PE.
	 */
	gpu_pdev = pnv_pci_get_gpu_dev(npu_pdev);
1110
	for (pe_num = 0; pe_num < phb->ioda.total_pe_num; pe_num++) {
1111 1112 1113 1114 1115 1116 1117 1118 1119 1120 1121 1122 1123 1124 1125 1126 1127 1128 1129 1130 1131 1132 1133 1134 1135 1136 1137 1138 1139 1140 1141 1142 1143 1144 1145 1146 1147 1148 1149 1150 1151 1152
		pe = &phb->ioda.pe_array[pe_num];
		if (!pe->pdev)
			continue;

		if (pnv_pci_get_gpu_dev(pe->pdev) == gpu_pdev) {
			/*
			 * This device has the same peer GPU so should
			 * be assigned the same PE as the existing
			 * peer NPU.
			 */
			dev_info(&npu_pdev->dev,
				"Associating to existing PE %d\n", pe_num);
			pci_dev_get(npu_pdev);
			npu_pdn = pci_get_pdn(npu_pdev);
			rid = npu_pdev->bus->number << 8 | npu_pdn->devfn;
			npu_pdn->pcidev = npu_pdev;
			npu_pdn->pe_number = pe_num;
			phb->ioda.pe_rmap[rid] = pe->pe_number;

			/* Map the PE to this link */
			rc = opal_pci_set_pe(phb->opal_id, pe_num, rid,
					OpalPciBusAll,
					OPAL_COMPARE_RID_DEVICE_NUMBER,
					OPAL_COMPARE_RID_FUNCTION_NUMBER,
					OPAL_MAP_PE);
			WARN_ON(rc != OPAL_SUCCESS);
			found_pe = true;
			break;
		}
	}

	if (!found_pe)
		/*
		 * Could not find an existing PE so allocate a new
		 * one.
		 */
		return pnv_ioda_setup_dev_PE(npu_pdev);
	else
		return pe;
}

static void pnv_ioda_setup_npu_PEs(struct pci_bus *bus)
1153 1154 1155 1156
{
	struct pci_dev *pdev;

	list_for_each_entry(pdev, &bus->devices, bus_list)
1157
		pnv_ioda_setup_npu_PE(pdev);
1158 1159
}

1160
static void pnv_ioda_setup_PEs(struct pci_bus *bus)
1161 1162
{
	struct pci_dev *dev;
1163

1164
	pnv_ioda_setup_bus_PE(bus, false);
1165 1166

	list_for_each_entry(dev, &bus->devices, bus_list) {
1167 1168
		if (dev->subordinate) {
			if (pci_pcie_type(dev) == PCI_EXP_TYPE_PCI_BRIDGE)
1169
				pnv_ioda_setup_bus_PE(dev->subordinate, true);
1170 1171 1172 1173 1174 1175 1176 1177 1178 1179 1180 1181 1182 1183
			else
				pnv_ioda_setup_PEs(dev->subordinate);
		}
	}
}

/*
 * Configure PEs so that the downstream PCI buses and devices
 * could have their associated PE#. Unfortunately, we didn't
 * figure out the way to identify the PLX bridge yet. So we
 * simply put the PCI bus and the subordinate behind the root
 * port to PE# here. The game rule here is expected to be changed
 * as soon as we can detected PLX bridge correctly.
 */
1184
static void pnv_pci_ioda_setup_PEs(void)
1185 1186
{
	struct pci_controller *hose, *tmp;
1187
	struct pnv_phb *phb;
1188 1189

	list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
1190 1191 1192
		phb = hose->private_data;

		/* M64 layout might affect PE allocation */
1193
		if (phb->reserve_m64_pe)
1194
			phb->reserve_m64_pe(hose->bus, NULL, true);
1195

1196 1197 1198 1199 1200
		/*
		 * On NPU PHB, we expect separate PEs for individual PCI
		 * functions. PCI bus dependent PEs are required for the
		 * remaining types of PHBs.
		 */
1201 1202 1203
		if (phb->type == PNV_PHB_NPU) {
			/* PE#0 is needed for error reporting */
			pnv_ioda_reserve_pe(phb, 0);
1204
			pnv_ioda_setup_npu_PEs(hose->bus);
1205
		} else
1206
			pnv_ioda_setup_PEs(hose->bus);
1207 1208 1209
	}
}

G
Gavin Shan 已提交
1210
#ifdef CONFIG_PCI_IOV
1211
static int pnv_pci_vf_release_m64(struct pci_dev *pdev, u16 num_vfs)
1212 1213 1214 1215 1216
{
	struct pci_bus        *bus;
	struct pci_controller *hose;
	struct pnv_phb        *phb;
	struct pci_dn         *pdn;
1217
	int                    i, j;
1218
	int                    m64_bars;
1219 1220 1221 1222 1223 1224

	bus = pdev->bus;
	hose = pci_bus_to_host(bus);
	phb = hose->private_data;
	pdn = pci_get_pdn(pdev);

1225 1226 1227 1228 1229
	if (pdn->m64_single_mode)
		m64_bars = num_vfs;
	else
		m64_bars = 1;

1230
	for (i = 0; i < PCI_SRIOV_NUM_BARS; i++)
1231 1232
		for (j = 0; j < m64_bars; j++) {
			if (pdn->m64_map[j][i] == IODA_INVALID_M64)
1233 1234
				continue;
			opal_pci_phb_mmio_enable(phb->opal_id,
1235 1236 1237
				OPAL_M64_WINDOW_TYPE, pdn->m64_map[j][i], 0);
			clear_bit(pdn->m64_map[j][i], &phb->ioda.m64_bar_alloc);
			pdn->m64_map[j][i] = IODA_INVALID_M64;
1238
		}
1239

1240
	kfree(pdn->m64_map);
1241 1242 1243
	return 0;
}

1244
static int pnv_pci_vf_assign_m64(struct pci_dev *pdev, u16 num_vfs)
1245 1246 1247 1248 1249 1250 1251
{
	struct pci_bus        *bus;
	struct pci_controller *hose;
	struct pnv_phb        *phb;
	struct pci_dn         *pdn;
	unsigned int           win;
	struct resource       *res;
1252
	int                    i, j;
1253
	int64_t                rc;
1254 1255 1256
	int                    total_vfs;
	resource_size_t        size, start;
	int                    pe_num;
1257
	int                    m64_bars;
1258 1259 1260 1261 1262

	bus = pdev->bus;
	hose = pci_bus_to_host(bus);
	phb = hose->private_data;
	pdn = pci_get_pdn(pdev);
1263
	total_vfs = pci_sriov_get_totalvfs(pdev);
1264

1265 1266 1267 1268 1269 1270 1271 1272 1273 1274 1275 1276
	if (pdn->m64_single_mode)
		m64_bars = num_vfs;
	else
		m64_bars = 1;

	pdn->m64_map = kmalloc(sizeof(*pdn->m64_map) * m64_bars, GFP_KERNEL);
	if (!pdn->m64_map)
		return -ENOMEM;
	/* Initialize the m64_map to IODA_INVALID_M64 */
	for (i = 0; i < m64_bars ; i++)
		for (j = 0; j < PCI_SRIOV_NUM_BARS; j++)
			pdn->m64_map[i][j] = IODA_INVALID_M64;
1277

1278 1279 1280 1281 1282 1283

	for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
		res = &pdev->resource[i + PCI_IOV_RESOURCES];
		if (!res->flags || !res->parent)
			continue;

1284
		for (j = 0; j < m64_bars; j++) {
1285 1286 1287 1288 1289 1290 1291 1292
			do {
				win = find_next_zero_bit(&phb->ioda.m64_bar_alloc,
						phb->ioda.m64_bar_idx + 1, 0);

				if (win >= phb->ioda.m64_bar_idx + 1)
					goto m64_failed;
			} while (test_and_set_bit(win, &phb->ioda.m64_bar_alloc));

1293
			pdn->m64_map[j][i] = win;
1294

1295
			if (pdn->m64_single_mode) {
1296 1297 1298 1299 1300 1301 1302 1303 1304
				size = pci_iov_resource_size(pdev,
							PCI_IOV_RESOURCES + i);
				start = res->start + size * j;
			} else {
				size = resource_size(res);
				start = res->start;
			}

			/* Map the M64 here */
1305
			if (pdn->m64_single_mode) {
1306
				pe_num = pdn->pe_num_map[j];
1307 1308
				rc = opal_pci_map_pe_mmio_window(phb->opal_id,
						pe_num, OPAL_M64_WINDOW_TYPE,
1309
						pdn->m64_map[j][i], 0);
1310 1311 1312 1313
			}

			rc = opal_pci_set_phb_mem_window(phb->opal_id,
						 OPAL_M64_WINDOW_TYPE,
1314
						 pdn->m64_map[j][i],
1315 1316 1317
						 start,
						 0, /* unused */
						 size);
1318 1319


1320 1321 1322 1323 1324
			if (rc != OPAL_SUCCESS) {
				dev_err(&pdev->dev, "Failed to map M64 window #%d: %lld\n",
					win, rc);
				goto m64_failed;
			}
1325

1326
			if (pdn->m64_single_mode)
1327
				rc = opal_pci_phb_mmio_enable(phb->opal_id,
1328
				     OPAL_M64_WINDOW_TYPE, pdn->m64_map[j][i], 2);
1329 1330
			else
				rc = opal_pci_phb_mmio_enable(phb->opal_id,
1331
				     OPAL_M64_WINDOW_TYPE, pdn->m64_map[j][i], 1);
1332

1333 1334 1335 1336 1337
			if (rc != OPAL_SUCCESS) {
				dev_err(&pdev->dev, "Failed to enable M64 window #%d: %llx\n",
					win, rc);
				goto m64_failed;
			}
1338 1339 1340 1341 1342
		}
	}
	return 0;

m64_failed:
1343
	pnv_pci_vf_release_m64(pdev, num_vfs);
1344 1345 1346
	return -EBUSY;
}

1347 1348 1349 1350
static long pnv_pci_ioda2_unset_window(struct iommu_table_group *table_group,
		int num);
static void pnv_pci_ioda2_set_bypass(struct pnv_ioda_pe *pe, bool enable);

1351 1352 1353 1354 1355
static void pnv_pci_ioda2_release_dma_pe(struct pci_dev *dev, struct pnv_ioda_pe *pe)
{
	struct iommu_table    *tbl;
	int64_t               rc;

1356
	tbl = pe->table_group.tables[0];
1357
	rc = pnv_pci_ioda2_unset_window(&pe->table_group, 0);
1358 1359 1360
	if (rc)
		pe_warn(pe, "OPAL error %ld release DMA window\n", rc);

1361
	pnv_pci_ioda2_set_bypass(pe, false);
1362 1363 1364
	if (pe->table_group.group) {
		iommu_group_put(pe->table_group.group);
		BUG_ON(pe->table_group.group);
1365
	}
1366
	pnv_pci_ioda2_table_free_pages(tbl);
1367 1368 1369
	iommu_free_table(tbl, of_node_full_name(dev->dev.of_node));
}

1370
static void pnv_ioda_release_vf_PE(struct pci_dev *pdev)
1371 1372 1373 1374 1375 1376 1377 1378 1379 1380
{
	struct pci_bus        *bus;
	struct pci_controller *hose;
	struct pnv_phb        *phb;
	struct pnv_ioda_pe    *pe, *pe_n;
	struct pci_dn         *pdn;

	bus = pdev->bus;
	hose = pci_bus_to_host(bus);
	phb = hose->private_data;
1381
	pdn = pci_get_pdn(pdev);
1382 1383 1384 1385 1386 1387 1388 1389 1390 1391 1392 1393 1394 1395 1396 1397 1398 1399 1400 1401 1402 1403 1404 1405 1406 1407 1408 1409

	if (!pdev->is_physfn)
		return;

	list_for_each_entry_safe(pe, pe_n, &phb->ioda.pe_list, list) {
		if (pe->parent_dev != pdev)
			continue;

		pnv_pci_ioda2_release_dma_pe(pdev, pe);

		/* Remove from list */
		mutex_lock(&phb->ioda.pe_list_mutex);
		list_del(&pe->list);
		mutex_unlock(&phb->ioda.pe_list_mutex);

		pnv_ioda_deconfigure_pe(phb, pe);

		pnv_ioda_free_pe(phb, pe->pe_number);
	}
}

void pnv_pci_sriov_disable(struct pci_dev *pdev)
{
	struct pci_bus        *bus;
	struct pci_controller *hose;
	struct pnv_phb        *phb;
	struct pci_dn         *pdn;
	struct pci_sriov      *iov;
1410
	u16                    num_vfs, i;
1411 1412 1413 1414 1415 1416 1417 1418 1419

	bus = pdev->bus;
	hose = pci_bus_to_host(bus);
	phb = hose->private_data;
	pdn = pci_get_pdn(pdev);
	iov = pdev->sriov;
	num_vfs = pdn->num_vfs;

	/* Release VF PEs */
1420
	pnv_ioda_release_vf_PE(pdev);
1421 1422

	if (phb->type == PNV_PHB_IODA2) {
1423
		if (!pdn->m64_single_mode)
1424
			pnv_pci_vf_resource_shift(pdev, -*pdn->pe_num_map);
1425 1426

		/* Release M64 windows */
1427
		pnv_pci_vf_release_m64(pdev, num_vfs);
1428 1429

		/* Release PE numbers */
1430 1431 1432 1433 1434 1435 1436 1437 1438
		if (pdn->m64_single_mode) {
			for (i = 0; i < num_vfs; i++) {
				if (pdn->pe_num_map[i] != IODA_INVALID_PE)
					pnv_ioda_free_pe(phb, pdn->pe_num_map[i]);
			}
		} else
			bitmap_clear(phb->ioda.pe_alloc, *pdn->pe_num_map, num_vfs);
		/* Releasing pe_num_map */
		kfree(pdn->pe_num_map);
1439 1440 1441 1442 1443 1444 1445 1446 1447 1448 1449 1450 1451 1452 1453 1454 1455 1456 1457 1458 1459 1460 1461 1462 1463
	}
}

static void pnv_pci_ioda2_setup_dma_pe(struct pnv_phb *phb,
				       struct pnv_ioda_pe *pe);
static void pnv_ioda_setup_vf_PE(struct pci_dev *pdev, u16 num_vfs)
{
	struct pci_bus        *bus;
	struct pci_controller *hose;
	struct pnv_phb        *phb;
	struct pnv_ioda_pe    *pe;
	int                    pe_num;
	u16                    vf_index;
	struct pci_dn         *pdn;

	bus = pdev->bus;
	hose = pci_bus_to_host(bus);
	phb = hose->private_data;
	pdn = pci_get_pdn(pdev);

	if (!pdev->is_physfn)
		return;

	/* Reserve PE for each VF */
	for (vf_index = 0; vf_index < num_vfs; vf_index++) {
1464 1465 1466 1467
		if (pdn->m64_single_mode)
			pe_num = pdn->pe_num_map[vf_index];
		else
			pe_num = *pdn->pe_num_map + vf_index;
1468 1469 1470 1471 1472 1473 1474 1475 1476 1477 1478 1479 1480 1481 1482 1483 1484 1485 1486 1487 1488 1489 1490 1491 1492 1493 1494 1495 1496 1497 1498 1499 1500 1501 1502 1503 1504 1505 1506 1507

		pe = &phb->ioda.pe_array[pe_num];
		pe->pe_number = pe_num;
		pe->phb = phb;
		pe->flags = PNV_IODA_PE_VF;
		pe->pbus = NULL;
		pe->parent_dev = pdev;
		pe->mve_number = -1;
		pe->rid = (pci_iov_virtfn_bus(pdev, vf_index) << 8) |
			   pci_iov_virtfn_devfn(pdev, vf_index);

		pe_info(pe, "VF %04d:%02d:%02d.%d associated with PE#%d\n",
			hose->global_number, pdev->bus->number,
			PCI_SLOT(pci_iov_virtfn_devfn(pdev, vf_index)),
			PCI_FUNC(pci_iov_virtfn_devfn(pdev, vf_index)), pe_num);

		if (pnv_ioda_configure_pe(phb, pe)) {
			/* XXX What do we do here ? */
			if (pe_num)
				pnv_ioda_free_pe(phb, pe_num);
			pe->pdev = NULL;
			continue;
		}

		/* Put PE to the list */
		mutex_lock(&phb->ioda.pe_list_mutex);
		list_add_tail(&pe->list, &phb->ioda.pe_list);
		mutex_unlock(&phb->ioda.pe_list_mutex);

		pnv_pci_ioda2_setup_dma_pe(phb, pe);
	}
}

int pnv_pci_sriov_enable(struct pci_dev *pdev, u16 num_vfs)
{
	struct pci_bus        *bus;
	struct pci_controller *hose;
	struct pnv_phb        *phb;
	struct pci_dn         *pdn;
	int                    ret;
1508
	u16                    i;
1509 1510 1511 1512 1513 1514 1515

	bus = pdev->bus;
	hose = pci_bus_to_host(bus);
	phb = hose->private_data;
	pdn = pci_get_pdn(pdev);

	if (phb->type == PNV_PHB_IODA2) {
1516 1517 1518 1519 1520 1521
		if (!pdn->vfs_expanded) {
			dev_info(&pdev->dev, "don't support this SRIOV device"
				" with non 64bit-prefetchable IOV BAR\n");
			return -ENOSPC;
		}

1522 1523 1524 1525 1526 1527 1528 1529 1530
		/*
		 * When M64 BARs functions in Single PE mode, the number of VFs
		 * could be enabled must be less than the number of M64 BARs.
		 */
		if (pdn->m64_single_mode && num_vfs > phb->ioda.m64_bar_idx) {
			dev_info(&pdev->dev, "Not enough M64 BAR for VFs\n");
			return -EBUSY;
		}

1531 1532 1533 1534 1535 1536 1537 1538 1539 1540 1541 1542 1543 1544
		/* Allocating pe_num_map */
		if (pdn->m64_single_mode)
			pdn->pe_num_map = kmalloc(sizeof(*pdn->pe_num_map) * num_vfs,
					GFP_KERNEL);
		else
			pdn->pe_num_map = kmalloc(sizeof(*pdn->pe_num_map), GFP_KERNEL);

		if (!pdn->pe_num_map)
			return -ENOMEM;

		if (pdn->m64_single_mode)
			for (i = 0; i < num_vfs; i++)
				pdn->pe_num_map[i] = IODA_INVALID_PE;

1545
		/* Calculate available PE for required VFs */
1546 1547 1548 1549 1550 1551 1552 1553 1554 1555 1556
		if (pdn->m64_single_mode) {
			for (i = 0; i < num_vfs; i++) {
				pdn->pe_num_map[i] = pnv_ioda_alloc_pe(phb);
				if (pdn->pe_num_map[i] == IODA_INVALID_PE) {
					ret = -EBUSY;
					goto m64_failed;
				}
			}
		} else {
			mutex_lock(&phb->ioda.pe_alloc_mutex);
			*pdn->pe_num_map = bitmap_find_next_zero_area(
1557
				phb->ioda.pe_alloc, phb->ioda.total_pe_num,
1558
				0, num_vfs, 0);
1559
			if (*pdn->pe_num_map >= phb->ioda.total_pe_num) {
1560 1561 1562 1563 1564 1565
				mutex_unlock(&phb->ioda.pe_alloc_mutex);
				dev_info(&pdev->dev, "Failed to enable VF%d\n", num_vfs);
				kfree(pdn->pe_num_map);
				return -EBUSY;
			}
			bitmap_set(phb->ioda.pe_alloc, *pdn->pe_num_map, num_vfs);
1566 1567 1568 1569 1570
			mutex_unlock(&phb->ioda.pe_alloc_mutex);
		}
		pdn->num_vfs = num_vfs;

		/* Assign M64 window accordingly */
1571
		ret = pnv_pci_vf_assign_m64(pdev, num_vfs);
1572 1573 1574 1575 1576 1577 1578 1579 1580 1581
		if (ret) {
			dev_info(&pdev->dev, "Not enough M64 window resources\n");
			goto m64_failed;
		}

		/*
		 * When using one M64 BAR to map one IOV BAR, we need to shift
		 * the IOV BAR according to the PE# allocated to the VFs.
		 * Otherwise, the PE# for the VF will conflict with others.
		 */
1582
		if (!pdn->m64_single_mode) {
1583
			ret = pnv_pci_vf_resource_shift(pdev, *pdn->pe_num_map);
1584 1585 1586
			if (ret)
				goto m64_failed;
		}
1587 1588 1589 1590 1591 1592 1593 1594
	}

	/* Setup VF PEs */
	pnv_ioda_setup_vf_PE(pdev, num_vfs);

	return 0;

m64_failed:
1595 1596 1597 1598 1599 1600 1601 1602 1603 1604
	if (pdn->m64_single_mode) {
		for (i = 0; i < num_vfs; i++) {
			if (pdn->pe_num_map[i] != IODA_INVALID_PE)
				pnv_ioda_free_pe(phb, pdn->pe_num_map[i]);
		}
	} else
		bitmap_clear(phb->ioda.pe_alloc, *pdn->pe_num_map, num_vfs);

	/* Releasing pe_num_map */
	kfree(pdn->pe_num_map);
1605 1606 1607 1608

	return ret;
}

G
Gavin Shan 已提交
1609 1610
int pcibios_sriov_disable(struct pci_dev *pdev)
{
1611 1612
	pnv_pci_sriov_disable(pdev);

G
Gavin Shan 已提交
1613 1614 1615 1616 1617 1618 1619 1620 1621
	/* Release PCI data */
	remove_dev_pci_data(pdev);
	return 0;
}

int pcibios_sriov_enable(struct pci_dev *pdev, u16 num_vfs)
{
	/* Allocate PCI data */
	add_dev_pci_data(pdev);
1622

1623
	return pnv_pci_sriov_enable(pdev, num_vfs);
G
Gavin Shan 已提交
1624 1625 1626
}
#endif /* CONFIG_PCI_IOV */

1627
static void pnv_pci_ioda_dma_dev_setup(struct pnv_phb *phb, struct pci_dev *pdev)
1628
{
1629
	struct pci_dn *pdn = pci_get_pdn(pdev);
1630
	struct pnv_ioda_pe *pe;
1631

1632 1633 1634 1635 1636 1637 1638
	/*
	 * The function can be called while the PE#
	 * hasn't been assigned. Do nothing for the
	 * case.
	 */
	if (!pdn || pdn->pe_number == IODA_INVALID_PE)
		return;
1639

1640
	pe = &phb->ioda.pe_array[pdn->pe_number];
1641
	WARN_ON(get_dma_ops(&pdev->dev) != &dma_iommu_ops);
1642
	set_dma_offset(&pdev->dev, pe->tce_bypass_base);
1643
	set_iommu_table_base(&pdev->dev, pe->table_group.tables[0]);
1644 1645 1646 1647 1648 1649
	/*
	 * Note: iommu_add_device() will fail here as
	 * for physical PE: the device is already added by now;
	 * for virtual PE: sysfs entries are not ready yet and
	 * tce_iommu_bus_notifier will add the device to a group later.
	 */
1650 1651
}

1652
static int pnv_pci_ioda_dma_set_mask(struct pci_dev *pdev, u64 dma_mask)
1653
{
1654 1655
	struct pci_controller *hose = pci_bus_to_host(pdev->bus);
	struct pnv_phb *phb = hose->private_data;
1656 1657 1658 1659
	struct pci_dn *pdn = pci_get_pdn(pdev);
	struct pnv_ioda_pe *pe;
	uint64_t top;
	bool bypass = false;
1660 1661
	struct pci_dev *linked_npu_dev;
	int i;
1662 1663 1664 1665 1666 1667 1668 1669 1670 1671 1672 1673 1674 1675 1676 1677 1678

	if (WARN_ON(!pdn || pdn->pe_number == IODA_INVALID_PE))
		return -ENODEV;;

	pe = &phb->ioda.pe_array[pdn->pe_number];
	if (pe->tce_bypass_enabled) {
		top = pe->tce_bypass_base + memblock_end_of_DRAM() - 1;
		bypass = (dma_mask >= top);
	}

	if (bypass) {
		dev_info(&pdev->dev, "Using 64-bit DMA iommu bypass\n");
		set_dma_ops(&pdev->dev, &dma_direct_ops);
	} else {
		dev_info(&pdev->dev, "Using 32-bit DMA via iommu\n");
		set_dma_ops(&pdev->dev, &dma_iommu_ops);
	}
1679
	*pdev->dev.dma_mask = dma_mask;
1680 1681 1682

	/* Update peer npu devices */
	if (pe->flags & PNV_IODA_PE_PEER)
1683 1684 1685 1686
		for (i = 0; i < PNV_IODA_MAX_PEER_PES; i++) {
			if (!pe->peers[i])
				continue;

1687 1688 1689 1690 1691
			linked_npu_dev = pe->peers[i]->pdev;
			if (dma_get_mask(&linked_npu_dev->dev) != dma_mask)
				dma_set_mask(&linked_npu_dev->dev, dma_mask);
		}

1692 1693 1694
	return 0;
}

1695
static u64 pnv_pci_ioda_dma_get_required_mask(struct pci_dev *pdev)
1696
{
1697 1698
	struct pci_controller *hose = pci_bus_to_host(pdev->bus);
	struct pnv_phb *phb = hose->private_data;
1699 1700 1701 1702 1703 1704 1705 1706 1707 1708 1709 1710 1711 1712 1713 1714 1715 1716 1717
	struct pci_dn *pdn = pci_get_pdn(pdev);
	struct pnv_ioda_pe *pe;
	u64 end, mask;

	if (WARN_ON(!pdn || pdn->pe_number == IODA_INVALID_PE))
		return 0;

	pe = &phb->ioda.pe_array[pdn->pe_number];
	if (!pe->tce_bypass_enabled)
		return __dma_get_required_mask(&pdev->dev);


	end = pe->tce_bypass_base + memblock_end_of_DRAM();
	mask = 1ULL << (fls64(end) - 1);
	mask += mask - 1;

	return mask;
}

1718
static void pnv_ioda_setup_bus_dma(struct pnv_ioda_pe *pe,
1719
				   struct pci_bus *bus)
1720 1721 1722 1723
{
	struct pci_dev *dev;

	list_for_each_entry(dev, &bus->devices, bus_list) {
1724
		set_iommu_table_base(&dev->dev, pe->table_group.tables[0]);
1725
		set_dma_offset(&dev->dev, pe->tce_bypass_base);
1726
		iommu_add_device(&dev->dev);
1727

1728
		if ((pe->flags & PNV_IODA_PE_BUS_ALL) && dev->subordinate)
1729
			pnv_ioda_setup_bus_dma(pe, dev->subordinate);
1730 1731 1732
	}
}

1733 1734
static void pnv_pci_ioda1_tce_invalidate(struct iommu_table *tbl,
		unsigned long index, unsigned long npages, bool rm)
1735
{
1736 1737 1738 1739
	struct iommu_table_group_link *tgl = list_first_entry_or_null(
			&tbl->it_group_list, struct iommu_table_group_link,
			next);
	struct pnv_ioda_pe *pe = container_of(tgl->table_group,
1740
			struct pnv_ioda_pe, table_group);
1741
	__be64 __iomem *invalidate = rm ?
1742 1743
		(__be64 __iomem *)pe->phb->ioda.tce_inval_reg_phys :
		pe->phb->ioda.tce_inval_reg;
1744
	unsigned long start, end, inc;
1745
	const unsigned shift = tbl->it_page_shift;
1746

1747 1748 1749
	start = __pa(((__be64 *)tbl->it_base) + index - tbl->it_offset);
	end = __pa(((__be64 *)tbl->it_base) + index - tbl->it_offset +
			npages - 1);
1750 1751 1752

	/* BML uses this case for p6/p7/galaxy2: Shift addr and put in node */
	if (tbl->it_busno) {
1753 1754 1755
		start <<= shift;
		end <<= shift;
		inc = 128ull << shift;
1756 1757 1758 1759 1760 1761 1762 1763 1764 1765 1766 1767 1768 1769 1770 1771
		start |= tbl->it_busno;
		end |= tbl->it_busno;
	} else if (tbl->it_type & TCE_PCI_SWINV_PAIR) {
		/* p7ioc-style invalidation, 2 TCEs per write */
		start |= (1ull << 63);
		end |= (1ull << 63);
		inc = 16;
        } else {
		/* Default (older HW) */
                inc = 128;
	}

        end |= inc - 1;	/* round up end to be different than start */

        mb(); /* Ensure above stores are visible */
        while (start <= end) {
1772
		if (rm)
1773
			__raw_rm_writeq(cpu_to_be64(start), invalidate);
1774
		else
1775
			__raw_writeq(cpu_to_be64(start), invalidate);
1776 1777 1778 1779 1780 1781 1782 1783 1784
                start += inc;
        }

	/*
	 * The iommu layer will do another mb() for us on build()
	 * and we don't care on free()
	 */
}

1785 1786 1787 1788 1789 1790 1791 1792 1793 1794 1795 1796 1797 1798
static int pnv_ioda1_tce_build(struct iommu_table *tbl, long index,
		long npages, unsigned long uaddr,
		enum dma_data_direction direction,
		struct dma_attrs *attrs)
{
	int ret = pnv_tce_build(tbl, index, npages, uaddr, direction,
			attrs);

	if (!ret && (tbl->it_type & TCE_PCI_SWINV_CREATE))
		pnv_pci_ioda1_tce_invalidate(tbl, index, npages, false);

	return ret;
}

1799 1800 1801 1802 1803 1804 1805 1806 1807 1808 1809 1810 1811 1812
#ifdef CONFIG_IOMMU_API
static int pnv_ioda1_tce_xchg(struct iommu_table *tbl, long index,
		unsigned long *hpa, enum dma_data_direction *direction)
{
	long ret = pnv_tce_xchg(tbl, index, hpa, direction);

	if (!ret && (tbl->it_type &
			(TCE_PCI_SWINV_CREATE | TCE_PCI_SWINV_FREE)))
		pnv_pci_ioda1_tce_invalidate(tbl, index, 1, false);

	return ret;
}
#endif

1813 1814 1815 1816 1817 1818 1819 1820 1821
static void pnv_ioda1_tce_free(struct iommu_table *tbl, long index,
		long npages)
{
	pnv_tce_free(tbl, index, npages);

	if (tbl->it_type & TCE_PCI_SWINV_FREE)
		pnv_pci_ioda1_tce_invalidate(tbl, index, npages, false);
}

1822
static struct iommu_table_ops pnv_ioda1_iommu_ops = {
1823
	.set = pnv_ioda1_tce_build,
1824 1825 1826
#ifdef CONFIG_IOMMU_API
	.exchange = pnv_ioda1_tce_xchg,
#endif
1827
	.clear = pnv_ioda1_tce_free,
1828 1829 1830
	.get = pnv_tce_get,
};

1831 1832 1833 1834 1835
static inline void pnv_pci_ioda2_tce_invalidate_entire(struct pnv_ioda_pe *pe)
{
	/* 01xb - invalidate TCEs that match the specified PE# */
	unsigned long val = (0x4ull << 60) | (pe->pe_number & 0xFF);
	struct pnv_phb *phb = pe->phb;
1836 1837
	struct pnv_ioda_pe *npe;
	int i;
1838 1839 1840 1841 1842 1843

	if (!phb->ioda.tce_inval_reg)
		return;

	mb(); /* Ensure above stores are visible */
	__raw_writeq(cpu_to_be64(val), phb->ioda.tce_inval_reg);
1844 1845 1846 1847 1848 1849 1850 1851 1852

	if (pe->flags & PNV_IODA_PE_PEER)
		for (i = 0; i < PNV_IODA_MAX_PEER_PES; i++) {
			npe = pe->peers[i];
			if (!npe || npe->phb->type != PNV_PHB_NPU)
				continue;

			pnv_npu_tce_invalidate_entire(npe);
		}
1853 1854
}

1855 1856 1857
static void pnv_pci_ioda2_do_tce_invalidate(unsigned pe_number, bool rm,
		__be64 __iomem *invalidate, unsigned shift,
		unsigned long index, unsigned long npages)
1858 1859 1860 1861
{
	unsigned long start, end, inc;

	/* We'll invalidate DMA address in PE scope */
1862
	start = 0x2ull << 60;
1863
	start |= (pe_number & 0xFF);
1864 1865 1866
	end = start;

	/* Figure out the start, end and step */
1867 1868
	start |= (index << shift);
	end |= ((index + npages - 1) << shift);
1869
	inc = (0x1ull << shift);
1870 1871 1872
	mb();

	while (start <= end) {
1873
		if (rm)
1874
			__raw_rm_writeq(cpu_to_be64(start), invalidate);
1875
		else
1876
			__raw_writeq(cpu_to_be64(start), invalidate);
1877 1878 1879 1880
		start += inc;
	}
}

1881 1882 1883 1884 1885 1886
static void pnv_pci_ioda2_tce_invalidate(struct iommu_table *tbl,
		unsigned long index, unsigned long npages, bool rm)
{
	struct iommu_table_group_link *tgl;

	list_for_each_entry_rcu(tgl, &tbl->it_group_list, next) {
1887
		struct pnv_ioda_pe *npe;
1888 1889 1890 1891 1892
		struct pnv_ioda_pe *pe = container_of(tgl->table_group,
				struct pnv_ioda_pe, table_group);
		__be64 __iomem *invalidate = rm ?
			(__be64 __iomem *)pe->phb->ioda.tce_inval_reg_phys :
			pe->phb->ioda.tce_inval_reg;
1893
		int i;
1894 1895 1896 1897

		pnv_pci_ioda2_do_tce_invalidate(pe->pe_number, rm,
			invalidate, tbl->it_page_shift,
			index, npages);
1898 1899 1900 1901 1902 1903 1904 1905 1906 1907 1908

		if (pe->flags & PNV_IODA_PE_PEER)
			/* Invalidate PEs using the same TCE table */
			for (i = 0; i < PNV_IODA_MAX_PEER_PES; i++) {
				npe = pe->peers[i];
				if (!npe || npe->phb->type != PNV_PHB_NPU)
					continue;

				pnv_npu_tce_invalidate(npe, tbl, index,
							npages, rm);
			}
1909 1910 1911
	}
}

1912 1913 1914 1915
static int pnv_ioda2_tce_build(struct iommu_table *tbl, long index,
		long npages, unsigned long uaddr,
		enum dma_data_direction direction,
		struct dma_attrs *attrs)
1916
{
1917 1918
	int ret = pnv_tce_build(tbl, index, npages, uaddr, direction,
			attrs);
1919

1920 1921 1922 1923 1924 1925
	if (!ret && (tbl->it_type & TCE_PCI_SWINV_CREATE))
		pnv_pci_ioda2_tce_invalidate(tbl, index, npages, false);

	return ret;
}

1926 1927 1928 1929 1930 1931 1932 1933 1934 1935 1936 1937 1938 1939
#ifdef CONFIG_IOMMU_API
static int pnv_ioda2_tce_xchg(struct iommu_table *tbl, long index,
		unsigned long *hpa, enum dma_data_direction *direction)
{
	long ret = pnv_tce_xchg(tbl, index, hpa, direction);

	if (!ret && (tbl->it_type &
			(TCE_PCI_SWINV_CREATE | TCE_PCI_SWINV_FREE)))
		pnv_pci_ioda2_tce_invalidate(tbl, index, 1, false);

	return ret;
}
#endif

1940 1941 1942 1943 1944 1945 1946
static void pnv_ioda2_tce_free(struct iommu_table *tbl, long index,
		long npages)
{
	pnv_tce_free(tbl, index, npages);

	if (tbl->it_type & TCE_PCI_SWINV_FREE)
		pnv_pci_ioda2_tce_invalidate(tbl, index, npages, false);
1947 1948
}

1949 1950 1951 1952 1953 1954
static void pnv_ioda2_table_free(struct iommu_table *tbl)
{
	pnv_pci_ioda2_table_free_pages(tbl);
	iommu_free_table(tbl, "pnv");
}

1955
static struct iommu_table_ops pnv_ioda2_iommu_ops = {
1956
	.set = pnv_ioda2_tce_build,
1957 1958 1959
#ifdef CONFIG_IOMMU_API
	.exchange = pnv_ioda2_tce_xchg,
#endif
1960
	.clear = pnv_ioda2_tce_free,
1961
	.get = pnv_tce_get,
1962
	.free = pnv_ioda2_table_free,
1963 1964
};

1965 1966 1967 1968 1969 1970 1971 1972 1973 1974 1975 1976 1977 1978 1979 1980 1981 1982 1983 1984 1985 1986 1987 1988 1989 1990 1991 1992 1993 1994 1995 1996 1997 1998 1999 2000 2001 2002 2003 2004 2005 2006 2007 2008 2009 2010 2011 2012
static int pnv_pci_ioda_dev_dma_weight(struct pci_dev *dev, void *data)
{
	unsigned int *weight = (unsigned int *)data;

	/* This is quite simplistic. The "base" weight of a device
	 * is 10. 0 means no DMA is to be accounted for it.
	 */
	if (dev->hdr_type != PCI_HEADER_TYPE_NORMAL)
		return 0;

	if (dev->class == PCI_CLASS_SERIAL_USB_UHCI ||
	    dev->class == PCI_CLASS_SERIAL_USB_OHCI ||
	    dev->class == PCI_CLASS_SERIAL_USB_EHCI)
		*weight += 3;
	else if ((dev->class >> 8) == PCI_CLASS_STORAGE_RAID)
		*weight += 15;
	else
		*weight += 10;

	return 0;
}

static unsigned int pnv_pci_ioda_pe_dma_weight(struct pnv_ioda_pe *pe)
{
	unsigned int weight = 0;

	/* SRIOV VF has same DMA32 weight as its PF */
#ifdef CONFIG_PCI_IOV
	if ((pe->flags & PNV_IODA_PE_VF) && pe->parent_dev) {
		pnv_pci_ioda_dev_dma_weight(pe->parent_dev, &weight);
		return weight;
	}
#endif

	if ((pe->flags & PNV_IODA_PE_DEV) && pe->pdev) {
		pnv_pci_ioda_dev_dma_weight(pe->pdev, &weight);
	} else if ((pe->flags & PNV_IODA_PE_BUS) && pe->pbus) {
		struct pci_dev *pdev;

		list_for_each_entry(pdev, &pe->pbus->devices, bus_list)
			pnv_pci_ioda_dev_dma_weight(pdev, &weight);
	} else if ((pe->flags & PNV_IODA_PE_BUS_ALL) && pe->pbus) {
		pci_walk_bus(pe->pbus, pnv_pci_ioda_dev_dma_weight, &weight);
	}

	return weight;
}

2013
static void pnv_pci_ioda1_setup_dma_pe(struct pnv_phb *phb,
2014
				       struct pnv_ioda_pe *pe)
2015 2016 2017 2018
{

	struct page *tce_mem = NULL;
	struct iommu_table *tbl;
2019 2020
	unsigned int weight, total_weight = 0;
	unsigned int tce32_segsz, base, segs, avail, i;
2021 2022 2023 2024 2025 2026
	int64_t rc;
	void *addr;

	/* XXX FIXME: Handle 64-bit only DMA devices */
	/* XXX FIXME: Provide 64-bit DMA facilities & non-4K TCE tables etc.. */
	/* XXX FIXME: Allocate multi-level tables on PHB3 */
2027 2028 2029 2030 2031 2032 2033 2034 2035
	weight = pnv_pci_ioda_pe_dma_weight(pe);
	if (!weight)
		return;

	pci_walk_bus(phb->hose->bus, pnv_pci_ioda_dev_dma_weight,
		     &total_weight);
	segs = (weight * phb->ioda.dma32_count) / total_weight;
	if (!segs)
		segs = 1;
2036

2037 2038 2039 2040 2041 2042 2043 2044 2045 2046 2047 2048 2049 2050 2051 2052 2053 2054 2055 2056 2057 2058 2059 2060 2061
	/*
	 * Allocate contiguous DMA32 segments. We begin with the expected
	 * number of segments. With one more attempt, the number of DMA32
	 * segments to be allocated is decreased by one until one segment
	 * is allocated successfully.
	 */
	do {
		for (base = 0; base <= phb->ioda.dma32_count - segs; base++) {
			for (avail = 0, i = base; i < base + segs; i++) {
				if (phb->ioda.dma32_segmap[i] ==
				    IODA_INVALID_PE)
					avail++;
			}

			if (avail == segs)
				goto found;
		}
	} while (--segs);

	if (!segs) {
		pe_warn(pe, "No available DMA32 segments\n");
		return;
	}

found:
2062
	tbl = pnv_pci_table_alloc(phb->hose->node);
2063 2064
	iommu_register_group(&pe->table_group, phb->hose->global_number,
			pe->pe_number);
2065
	pnv_pci_link_table_and_group(phb->hose->node, 0, tbl, &pe->table_group);
2066

2067
	/* Grab a 32-bit TCE table */
2068 2069
	pe_info(pe, "DMA weight %d (%d), assigned (%d) %d DMA32 segments\n",
		weight, total_weight, base, segs);
2070
	pe_info(pe, " Setting up 32-bit TCE table at %08x..%08x\n",
2071 2072
		base * PNV_IODA1_DMA32_SEGSIZE,
		(base + segs) * PNV_IODA1_DMA32_SEGSIZE - 1);
2073 2074 2075 2076 2077

	/* XXX Currently, we allocate one big contiguous table for the
	 * TCEs. We only really need one chunk per 256M of TCE space
	 * (ie per segment) but that's an optimization for later, it
	 * requires some added smarts with our get/put_tce implementation
2078 2079 2080
	 *
	 * Each TCE page is 4KB in size and each TCE entry occupies 8
	 * bytes
2081
	 */
2082
	tce32_segsz = PNV_IODA1_DMA32_SEGSIZE >> (IOMMU_PAGE_SHIFT_4K - 3);
2083
	tce_mem = alloc_pages_node(phb->hose->node, GFP_KERNEL,
2084
				   get_order(tce32_segsz * segs));
2085 2086 2087 2088 2089
	if (!tce_mem) {
		pe_err(pe, " Failed to allocate a 32-bit TCE memory\n");
		goto fail;
	}
	addr = page_address(tce_mem);
2090
	memset(addr, 0, tce32_segsz * segs);
2091 2092 2093 2094 2095 2096

	/* Configure HW */
	for (i = 0; i < segs; i++) {
		rc = opal_pci_map_pe_dma_window(phb->opal_id,
					      pe->pe_number,
					      base + i, 1,
2097 2098
					      __pa(addr) + tce32_segsz * i,
					      tce32_segsz, IOMMU_PAGE_SIZE_4K);
2099 2100 2101 2102 2103 2104 2105
		if (rc) {
			pe_err(pe, " Failed to configure 32-bit TCE table,"
			       " err %ld\n", rc);
			goto fail;
		}
	}

2106 2107 2108 2109
	/* Setup DMA32 segment mapping */
	for (i = base; i < base + segs; i++)
		phb->ioda.dma32_segmap[i] = pe->pe_number;

2110
	/* Setup linux iommu table */
2111 2112 2113
	pnv_pci_setup_iommu_table(tbl, addr, tce32_segsz * segs,
				  base * PNV_IODA1_DMA32_SEGSIZE,
				  IOMMU_PAGE_SHIFT_4K);
2114 2115

	/* OPAL variant of P7IOC SW invalidated TCEs */
2116
	if (phb->ioda.tce_inval_reg)
2117 2118 2119
		tbl->it_type |= (TCE_PCI_SWINV_CREATE |
				 TCE_PCI_SWINV_FREE   |
				 TCE_PCI_SWINV_PAIR);
2120

2121
	tbl->it_ops = &pnv_ioda1_iommu_ops;
2122 2123
	pe->table_group.tce32_start = tbl->it_offset << tbl->it_page_shift;
	pe->table_group.tce32_size = tbl->it_size << tbl->it_page_shift;
2124 2125
	iommu_init_table(tbl, phb->hose->node);

2126
	if (pe->flags & PNV_IODA_PE_DEV) {
2127 2128 2129 2130 2131 2132 2133
		/*
		 * Setting table base here only for carrying iommu_group
		 * further down to let iommu_add_device() do the job.
		 * pnv_pci_ioda_dma_dev_setup will override it later anyway.
		 */
		set_iommu_table_base(&pe->pdev->dev, tbl);
		iommu_add_device(&pe->pdev->dev);
2134
	} else if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL))
2135
		pnv_ioda_setup_bus_dma(pe, pe->pbus);
2136

2137 2138 2139 2140
	return;
 fail:
	/* XXX Failure: Try to fallback to 64-bit only ? */
	if (tce_mem)
2141
		__free_pages(tce_mem, get_order(tce32_segsz * segs));
2142 2143 2144 2145
	if (tbl) {
		pnv_pci_unlink_table_and_group(tbl, &pe->table_group);
		iommu_free_table(tbl, "pnv");
	}
2146 2147
}

2148 2149 2150 2151 2152 2153 2154
static long pnv_pci_ioda2_set_window(struct iommu_table_group *table_group,
		int num, struct iommu_table *tbl)
{
	struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe,
			table_group);
	struct pnv_phb *phb = pe->phb;
	int64_t rc;
2155 2156
	const unsigned long size = tbl->it_indirect_levels ?
			tbl->it_level_size : tbl->it_size;
2157 2158 2159
	const __u64 start_addr = tbl->it_offset << tbl->it_page_shift;
	const __u64 win_size = tbl->it_size << tbl->it_page_shift;

2160
	pe_info(pe, "Setting up window#%d %llx..%llx pg=%x\n", num,
2161 2162 2163 2164 2165 2166 2167 2168 2169
			start_addr, start_addr + win_size - 1,
			IOMMU_PAGE_SIZE(tbl));

	/*
	 * Map TCE table through TVT. The TVE index is the PE number
	 * shifted by 1 bit for 32-bits DMA space.
	 */
	rc = opal_pci_map_pe_dma_window(phb->opal_id,
			pe->pe_number,
2170
			(pe->pe_number << 1) + num,
2171
			tbl->it_indirect_levels + 1,
2172
			__pa(tbl->it_base),
2173
			size << 3,
2174 2175 2176 2177 2178 2179 2180 2181 2182 2183 2184 2185 2186
			IOMMU_PAGE_SIZE(tbl));
	if (rc) {
		pe_err(pe, "Failed to configure TCE table, err %ld\n", rc);
		return rc;
	}

	pnv_pci_link_table_and_group(phb->hose->node, num,
			tbl, &pe->table_group);
	pnv_pci_ioda2_tce_invalidate_entire(pe);

	return 0;
}

2187
static void pnv_pci_ioda2_set_bypass(struct pnv_ioda_pe *pe, bool enable)
2188 2189 2190 2191 2192 2193 2194 2195 2196 2197 2198 2199 2200 2201 2202 2203 2204 2205 2206 2207 2208 2209 2210 2211 2212 2213 2214
{
	uint16_t window_id = (pe->pe_number << 1 ) + 1;
	int64_t rc;

	pe_info(pe, "%sabling 64-bit DMA bypass\n", enable ? "En" : "Dis");
	if (enable) {
		phys_addr_t top = memblock_end_of_DRAM();

		top = roundup_pow_of_two(top);
		rc = opal_pci_map_pe_dma_window_real(pe->phb->opal_id,
						     pe->pe_number,
						     window_id,
						     pe->tce_bypass_base,
						     top);
	} else {
		rc = opal_pci_map_pe_dma_window_real(pe->phb->opal_id,
						     pe->pe_number,
						     window_id,
						     pe->tce_bypass_base,
						     0);
	}
	if (rc)
		pe_err(pe, "OPAL error %lld configuring bypass window\n", rc);
	else
		pe->tce_bypass_enabled = enable;
}

2215 2216 2217 2218 2219 2220 2221 2222 2223 2224 2225 2226 2227 2228 2229 2230 2231 2232 2233 2234 2235 2236 2237 2238 2239 2240 2241 2242 2243 2244 2245 2246 2247 2248 2249 2250
static long pnv_pci_ioda2_table_alloc_pages(int nid, __u64 bus_offset,
		__u32 page_shift, __u64 window_size, __u32 levels,
		struct iommu_table *tbl);

static long pnv_pci_ioda2_create_table(struct iommu_table_group *table_group,
		int num, __u32 page_shift, __u64 window_size, __u32 levels,
		struct iommu_table **ptbl)
{
	struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe,
			table_group);
	int nid = pe->phb->hose->node;
	__u64 bus_offset = num ? pe->tce_bypass_base : table_group->tce32_start;
	long ret;
	struct iommu_table *tbl;

	tbl = pnv_pci_table_alloc(nid);
	if (!tbl)
		return -ENOMEM;

	ret = pnv_pci_ioda2_table_alloc_pages(nid,
			bus_offset, page_shift, window_size,
			levels, tbl);
	if (ret) {
		iommu_free_table(tbl, "pnv");
		return ret;
	}

	tbl->it_ops = &pnv_ioda2_iommu_ops;
	if (pe->phb->ioda.tce_inval_reg)
		tbl->it_type |= (TCE_PCI_SWINV_CREATE | TCE_PCI_SWINV_FREE);

	*ptbl = tbl;

	return 0;
}

2251 2252 2253 2254 2255
static long pnv_pci_ioda2_setup_default_config(struct pnv_ioda_pe *pe)
{
	struct iommu_table *tbl = NULL;
	long rc;

2256 2257 2258 2259 2260 2261 2262
	/*
	 * crashkernel= specifies the kdump kernel's maximum memory at
	 * some offset and there is no guaranteed the result is a power
	 * of 2, which will cause errors later.
	 */
	const u64 max_memory = __rounddown_pow_of_two(memory_hotplug_max());

2263 2264 2265 2266 2267
	/*
	 * In memory constrained environments, e.g. kdump kernel, the
	 * DMA window can be larger than available memory, which will
	 * cause errors later.
	 */
2268
	const u64 window_size = min((u64)pe->table_group.tce32_size, max_memory);
2269

2270 2271
	rc = pnv_pci_ioda2_create_table(&pe->table_group, 0,
			IOMMU_PAGE_SHIFT_4K,
2272
			window_size,
2273 2274 2275 2276 2277 2278 2279 2280 2281 2282 2283 2284 2285 2286 2287 2288 2289 2290 2291 2292 2293 2294 2295 2296 2297 2298 2299 2300 2301 2302 2303 2304 2305 2306 2307
			POWERNV_IOMMU_DEFAULT_LEVELS, &tbl);
	if (rc) {
		pe_err(pe, "Failed to create 32-bit TCE table, err %ld",
				rc);
		return rc;
	}

	iommu_init_table(tbl, pe->phb->hose->node);

	rc = pnv_pci_ioda2_set_window(&pe->table_group, 0, tbl);
	if (rc) {
		pe_err(pe, "Failed to configure 32-bit TCE table, err %ld\n",
				rc);
		pnv_ioda2_table_free(tbl);
		return rc;
	}

	if (!pnv_iommu_bypass_disabled)
		pnv_pci_ioda2_set_bypass(pe, true);

	/* OPAL variant of PHB3 invalidated TCEs */
	if (pe->phb->ioda.tce_inval_reg)
		tbl->it_type |= (TCE_PCI_SWINV_CREATE | TCE_PCI_SWINV_FREE);

	/*
	 * Setting table base here only for carrying iommu_group
	 * further down to let iommu_add_device() do the job.
	 * pnv_pci_ioda_dma_dev_setup will override it later anyway.
	 */
	if (pe->flags & PNV_IODA_PE_DEV)
		set_iommu_table_base(&pe->pdev->dev, tbl);

	return 0;
}

2308 2309 2310 2311 2312 2313 2314 2315 2316 2317 2318 2319 2320 2321 2322 2323 2324 2325 2326 2327 2328 2329 2330 2331 2332 2333
#if defined(CONFIG_IOMMU_API) || defined(CONFIG_PCI_IOV)
static long pnv_pci_ioda2_unset_window(struct iommu_table_group *table_group,
		int num)
{
	struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe,
			table_group);
	struct pnv_phb *phb = pe->phb;
	long ret;

	pe_info(pe, "Removing DMA window #%d\n", num);

	ret = opal_pci_map_pe_dma_window(phb->opal_id, pe->pe_number,
			(pe->pe_number << 1) + num,
			0/* levels */, 0/* table address */,
			0/* table size */, 0/* page size */);
	if (ret)
		pe_warn(pe, "Unmapping failed, ret = %ld\n", ret);
	else
		pnv_pci_ioda2_tce_invalidate_entire(pe);

	pnv_pci_unlink_table_and_group(table_group->tables[num], table_group);

	return ret;
}
#endif

2334
#ifdef CONFIG_IOMMU_API
2335 2336 2337 2338 2339 2340 2341 2342 2343 2344 2345 2346 2347 2348 2349 2350 2351 2352 2353 2354 2355 2356 2357 2358 2359 2360 2361 2362 2363 2364 2365 2366
static unsigned long pnv_pci_ioda2_get_table_size(__u32 page_shift,
		__u64 window_size, __u32 levels)
{
	unsigned long bytes = 0;
	const unsigned window_shift = ilog2(window_size);
	unsigned entries_shift = window_shift - page_shift;
	unsigned table_shift = entries_shift + 3;
	unsigned long tce_table_size = max(0x1000UL, 1UL << table_shift);
	unsigned long direct_table_size;

	if (!levels || (levels > POWERNV_IOMMU_MAX_LEVELS) ||
			(window_size > memory_hotplug_max()) ||
			!is_power_of_2(window_size))
		return 0;

	/* Calculate a direct table size from window_size and levels */
	entries_shift = (entries_shift + levels - 1) / levels;
	table_shift = entries_shift + 3;
	table_shift = max_t(unsigned, table_shift, PAGE_SHIFT);
	direct_table_size =  1UL << table_shift;

	for ( ; levels; --levels) {
		bytes += _ALIGN_UP(tce_table_size, direct_table_size);

		tce_table_size /= direct_table_size;
		tce_table_size <<= 3;
		tce_table_size = _ALIGN_UP(tce_table_size, direct_table_size);
	}

	return bytes;
}

2367
static void pnv_ioda2_take_ownership(struct iommu_table_group *table_group)
2368
{
2369 2370
	struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe,
						table_group);
2371 2372
	/* Store @tbl as pnv_pci_ioda2_unset_window() resets it */
	struct iommu_table *tbl = pe->table_group.tables[0];
2373

2374
	pnv_pci_ioda2_set_bypass(pe, false);
2375 2376
	pnv_pci_ioda2_unset_window(&pe->table_group, 0);
	pnv_ioda2_table_free(tbl);
2377
}
2378

2379 2380 2381 2382 2383
static void pnv_ioda2_release_ownership(struct iommu_table_group *table_group)
{
	struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe,
						table_group);

2384
	pnv_pci_ioda2_setup_default_config(pe);
2385 2386
}

2387
static struct iommu_table_group_ops pnv_pci_ioda2_ops = {
2388
	.get_table_size = pnv_pci_ioda2_get_table_size,
2389 2390 2391
	.create_table = pnv_pci_ioda2_create_table,
	.set_window = pnv_pci_ioda2_set_window,
	.unset_window = pnv_pci_ioda2_unset_window,
2392 2393 2394 2395 2396
	.take_ownership = pnv_ioda2_take_ownership,
	.release_ownership = pnv_ioda2_release_ownership,
};
#endif

2397 2398 2399 2400 2401 2402 2403 2404 2405 2406 2407 2408 2409
static void pnv_pci_ioda_setup_opal_tce_kill(struct pnv_phb *phb)
{
	const __be64 *swinvp;

	/* OPAL variant of PHB3 invalidated TCEs */
	swinvp = of_get_property(phb->hose->dn, "ibm,opal-tce-kill", NULL);
	if (!swinvp)
		return;

	phb->ioda.tce_inval_reg_phys = be64_to_cpup(swinvp);
	phb->ioda.tce_inval_reg = ioremap(phb->ioda.tce_inval_reg_phys, 8);
}

2410 2411
static __be64 *pnv_pci_ioda2_table_do_alloc_pages(int nid, unsigned shift,
		unsigned levels, unsigned long limit,
2412
		unsigned long *current_offset, unsigned long *total_allocated)
2413 2414
{
	struct page *tce_mem = NULL;
2415
	__be64 *addr, *tmp;
2416
	unsigned order = max_t(unsigned, shift, PAGE_SHIFT) - PAGE_SHIFT;
2417 2418 2419
	unsigned long allocated = 1UL << (order + PAGE_SHIFT);
	unsigned entries = 1UL << (shift - 3);
	long i;
2420 2421 2422 2423 2424 2425 2426

	tce_mem = alloc_pages_node(nid, GFP_KERNEL, order);
	if (!tce_mem) {
		pr_err("Failed to allocate a TCE memory, order=%d\n", order);
		return NULL;
	}
	addr = page_address(tce_mem);
2427
	memset(addr, 0, allocated);
2428
	*total_allocated += allocated;
2429 2430 2431 2432 2433 2434 2435 2436 2437

	--levels;
	if (!levels) {
		*current_offset += allocated;
		return addr;
	}

	for (i = 0; i < entries; ++i) {
		tmp = pnv_pci_ioda2_table_do_alloc_pages(nid, shift,
2438
				levels, limit, current_offset, total_allocated);
2439 2440 2441 2442 2443 2444 2445 2446 2447
		if (!tmp)
			break;

		addr[i] = cpu_to_be64(__pa(tmp) |
				TCE_PCI_READ | TCE_PCI_WRITE);

		if (*current_offset >= limit)
			break;
	}
2448 2449 2450 2451

	return addr;
}

2452 2453 2454
static void pnv_pci_ioda2_table_do_free_pages(__be64 *addr,
		unsigned long size, unsigned level);

2455
static long pnv_pci_ioda2_table_alloc_pages(int nid, __u64 bus_offset,
2456 2457
		__u32 page_shift, __u64 window_size, __u32 levels,
		struct iommu_table *tbl)
2458
{
2459
	void *addr;
2460
	unsigned long offset = 0, level_shift, total_allocated = 0;
2461 2462 2463 2464 2465
	const unsigned window_shift = ilog2(window_size);
	unsigned entries_shift = window_shift - page_shift;
	unsigned table_shift = max_t(unsigned, entries_shift + 3, PAGE_SHIFT);
	const unsigned long tce_table_size = 1UL << table_shift;

2466 2467 2468
	if (!levels || (levels > POWERNV_IOMMU_MAX_LEVELS))
		return -EINVAL;

2469 2470 2471
	if ((window_size > memory_hotplug_max()) || !is_power_of_2(window_size))
		return -EINVAL;

2472 2473 2474 2475 2476
	/* Adjust direct table size from window_size and levels */
	entries_shift = (entries_shift + levels - 1) / levels;
	level_shift = entries_shift + 3;
	level_shift = max_t(unsigned, level_shift, PAGE_SHIFT);

2477
	/* Allocate TCE table */
2478
	addr = pnv_pci_ioda2_table_do_alloc_pages(nid, level_shift,
2479
			levels, tce_table_size, &offset, &total_allocated);
2480 2481

	/* addr==NULL means that the first level allocation failed */
2482 2483 2484
	if (!addr)
		return -ENOMEM;

2485 2486 2487 2488 2489 2490 2491 2492 2493 2494 2495
	/*
	 * First level was allocated but some lower level failed as
	 * we did not allocate as much as we wanted,
	 * release partially allocated table.
	 */
	if (offset < tce_table_size) {
		pnv_pci_ioda2_table_do_free_pages(addr,
				1ULL << (level_shift - 3), levels - 1);
		return -ENOMEM;
	}

2496 2497 2498
	/* Setup linux iommu table */
	pnv_pci_setup_iommu_table(tbl, addr, tce_table_size, bus_offset,
			page_shift);
2499 2500
	tbl->it_level_size = 1ULL << (level_shift - 3);
	tbl->it_indirect_levels = levels - 1;
2501
	tbl->it_allocated_size = total_allocated;
2502 2503 2504 2505 2506 2507 2508

	pr_devel("Created TCE table: ws=%08llx ts=%lx @%08llx\n",
			window_size, tce_table_size, bus_offset);

	return 0;
}

2509 2510 2511 2512 2513 2514 2515 2516 2517 2518 2519 2520 2521 2522 2523 2524 2525 2526 2527 2528 2529 2530 2531 2532
static void pnv_pci_ioda2_table_do_free_pages(__be64 *addr,
		unsigned long size, unsigned level)
{
	const unsigned long addr_ul = (unsigned long) addr &
			~(TCE_PCI_READ | TCE_PCI_WRITE);

	if (level) {
		long i;
		u64 *tmp = (u64 *) addr_ul;

		for (i = 0; i < size; ++i) {
			unsigned long hpa = be64_to_cpu(tmp[i]);

			if (!(hpa & (TCE_PCI_READ | TCE_PCI_WRITE)))
				continue;

			pnv_pci_ioda2_table_do_free_pages(__va(hpa), size,
					level - 1);
		}
	}

	free_pages(addr_ul, get_order(size << 3));
}

2533 2534
static void pnv_pci_ioda2_table_free_pages(struct iommu_table *tbl)
{
2535 2536 2537
	const unsigned long size = tbl->it_indirect_levels ?
			tbl->it_level_size : tbl->it_size;

2538 2539 2540
	if (!tbl->it_size)
		return;

2541 2542
	pnv_pci_ioda2_table_do_free_pages((__be64 *)tbl->it_base, size,
			tbl->it_indirect_levels);
2543 2544 2545 2546 2547
}

static void pnv_pci_ioda2_setup_dma_pe(struct pnv_phb *phb,
				       struct pnv_ioda_pe *pe)
{
2548 2549
	int64_t rc;

2550 2551 2552
	/* TVE #1 is selected by PCI address bit 59 */
	pe->tce_bypass_base = 1ull << 59;

2553 2554
	iommu_register_group(&pe->table_group, phb->hose->global_number,
			pe->pe_number);
2555

2556 2557
	/* The PE will reserve all possible 32-bits space */
	pe_info(pe, "Setting up 32-bit TCE table at 0..%08x\n",
2558
		phb->ioda.m32_pci_base);
2559

2560
	/* Setup linux iommu table */
2561 2562 2563 2564 2565 2566
	pe->table_group.tce32_start = 0;
	pe->table_group.tce32_size = phb->ioda.m32_pci_base;
	pe->table_group.max_dynamic_windows_supported =
			IOMMU_TABLE_GROUP_MAX_TABLES;
	pe->table_group.max_levels = POWERNV_IOMMU_MAX_LEVELS;
	pe->table_group.pgsizes = SZ_4K | SZ_64K | SZ_16M;
2567 2568 2569 2570
#ifdef CONFIG_IOMMU_API
	pe->table_group.ops = &pnv_pci_ioda2_ops;
#endif

2571
	rc = pnv_pci_ioda2_setup_default_config(pe);
2572
	if (rc)
2573
		return;
2574

2575
	if (pe->flags & PNV_IODA_PE_DEV)
2576
		iommu_add_device(&pe->pdev->dev);
2577
	else if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL))
2578
		pnv_ioda_setup_bus_dma(pe, pe->pbus);
2579 2580
}

2581
static void pnv_ioda_setup_dma(struct pnv_phb *phb)
2582 2583 2584
{
	struct pci_controller *hose = phb->hose;
	struct pnv_ioda_pe *pe;
2585
	unsigned int weight;
2586

2587 2588 2589 2590 2591
	/* If we have more PE# than segments available, hand out one
	 * per PE until we run out and let the rest fail. If not,
	 * then we assign at least one segment per PE, plus more based
	 * on the amount of devices under that PE
	 */
2592 2593
	pr_info("PCI: Domain %04x has %d available 32-bit DMA segments\n",
		hose->global_number, phb->ioda.dma32_count);
2594

2595 2596
	pnv_pci_ioda_setup_opal_tce_kill(phb);

2597
	/* Walk our PE list and configure their DMA segments */
2598 2599 2600
	list_for_each_entry(pe, &phb->ioda.pe_list, list) {
		weight = pnv_pci_ioda_pe_dma_weight(pe);
		if (!weight)
2601
			continue;
2602

2603 2604 2605 2606 2607 2608
		/*
		 * For IODA2 compliant PHB3, we needn't care about the weight.
		 * The all available 32-bits DMA space will be assigned to
		 * the specific PE.
		 */
		if (phb->type == PNV_PHB_IODA1) {
2609
			pnv_pci_ioda1_setup_dma_pe(phb, pe);
2610
		} else if (phb->type == PNV_PHB_IODA2) {
2611 2612
			pe_info(pe, "Assign DMA32 space\n");
			pnv_pci_ioda2_setup_dma_pe(phb, pe);
2613 2614 2615 2616 2617 2618 2619
		} else if (phb->type == PNV_PHB_NPU) {
			/*
			 * We initialise the DMA space for an NPU PHB
			 * after setup of the PHB is complete as we
			 * point the NPU TVT to the the same location
			 * as the PHB3 TVT.
			 */
2620
		}
2621 2622 2623 2624
	}
}

#ifdef CONFIG_PCI_MSI
2625 2626 2627 2628 2629 2630 2631 2632 2633 2634 2635 2636 2637 2638
static void pnv_ioda2_msi_eoi(struct irq_data *d)
{
	unsigned int hw_irq = (unsigned int)irqd_to_hwirq(d);
	struct irq_chip *chip = irq_data_get_irq_chip(d);
	struct pnv_phb *phb = container_of(chip, struct pnv_phb,
					   ioda.irq_chip);
	int64_t rc;

	rc = opal_pci_msi_eoi(phb->opal_id, hw_irq);
	WARN_ON_ONCE(rc);

	icp_native_eoi(d);
}

2639 2640 2641 2642 2643 2644 2645 2646 2647 2648 2649 2650 2651 2652 2653 2654 2655 2656 2657 2658 2659 2660 2661

static void set_msi_irq_chip(struct pnv_phb *phb, unsigned int virq)
{
	struct irq_data *idata;
	struct irq_chip *ichip;

	if (phb->type != PNV_PHB_IODA2)
		return;

	if (!phb->ioda.irq_chip_init) {
		/*
		 * First time we setup an MSI IRQ, we need to setup the
		 * corresponding IRQ chip to route correctly.
		 */
		idata = irq_get_irq_data(virq);
		ichip = irq_data_get_irq_chip(idata);
		phb->ioda.irq_chip_init = 1;
		phb->ioda.irq_chip = *ichip;
		phb->ioda.irq_chip.irq_eoi = pnv_ioda2_msi_eoi;
	}
	irq_set_chip(virq, &phb->ioda.irq_chip);
}

2662 2663
#ifdef CONFIG_CXL_BASE

2664
struct device_node *pnv_pci_get_phb_node(struct pci_dev *dev)
2665 2666 2667
{
	struct pci_controller *hose = pci_bus_to_host(dev->bus);

2668
	return of_node_get(hose->dn);
2669
}
2670
EXPORT_SYMBOL(pnv_pci_get_phb_node);
2671

R
Ryan Grimm 已提交
2672
int pnv_phb_to_cxl_mode(struct pci_dev *dev, uint64_t mode)
2673 2674 2675 2676 2677 2678 2679 2680 2681 2682 2683 2684
{
	struct pci_controller *hose = pci_bus_to_host(dev->bus);
	struct pnv_phb *phb = hose->private_data;
	struct pnv_ioda_pe *pe;
	int rc;

	pe = pnv_ioda_get_pe(dev);
	if (!pe)
		return -ENODEV;

	pe_info(pe, "Switching PHB to CXL\n");

R
Ryan Grimm 已提交
2685
	rc = opal_pci_set_phb_cxl_mode(phb->opal_id, mode, pe->pe_number);
2686 2687 2688 2689 2690
	if (rc)
		dev_err(&dev->dev, "opal_pci_set_phb_cxl_mode failed: %i\n", rc);

	return rc;
}
R
Ryan Grimm 已提交
2691
EXPORT_SYMBOL(pnv_phb_to_cxl_mode);
2692 2693 2694 2695 2696 2697 2698 2699 2700 2701 2702 2703 2704 2705 2706 2707 2708 2709 2710 2711 2712 2713 2714 2715 2716 2717 2718 2719 2720 2721 2722 2723 2724 2725 2726 2727 2728 2729 2730 2731 2732 2733 2734 2735 2736 2737 2738 2739 2740 2741 2742 2743 2744 2745 2746 2747 2748 2749 2750 2751 2752 2753 2754 2755 2756 2757 2758 2759 2760 2761 2762 2763 2764 2765 2766 2767 2768 2769 2770 2771 2772 2773 2774 2775 2776 2777 2778 2779 2780 2781 2782 2783 2784 2785 2786 2787 2788 2789 2790 2791 2792 2793 2794 2795 2796 2797 2798 2799 2800 2801 2802 2803 2804 2805 2806 2807 2808 2809 2810 2811 2812

/* Find PHB for cxl dev and allocate MSI hwirqs?
 * Returns the absolute hardware IRQ number
 */
int pnv_cxl_alloc_hwirqs(struct pci_dev *dev, int num)
{
	struct pci_controller *hose = pci_bus_to_host(dev->bus);
	struct pnv_phb *phb = hose->private_data;
	int hwirq = msi_bitmap_alloc_hwirqs(&phb->msi_bmp, num);

	if (hwirq < 0) {
		dev_warn(&dev->dev, "Failed to find a free MSI\n");
		return -ENOSPC;
	}

	return phb->msi_base + hwirq;
}
EXPORT_SYMBOL(pnv_cxl_alloc_hwirqs);

void pnv_cxl_release_hwirqs(struct pci_dev *dev, int hwirq, int num)
{
	struct pci_controller *hose = pci_bus_to_host(dev->bus);
	struct pnv_phb *phb = hose->private_data;

	msi_bitmap_free_hwirqs(&phb->msi_bmp, hwirq - phb->msi_base, num);
}
EXPORT_SYMBOL(pnv_cxl_release_hwirqs);

void pnv_cxl_release_hwirq_ranges(struct cxl_irq_ranges *irqs,
				  struct pci_dev *dev)
{
	struct pci_controller *hose = pci_bus_to_host(dev->bus);
	struct pnv_phb *phb = hose->private_data;
	int i, hwirq;

	for (i = 1; i < CXL_IRQ_RANGES; i++) {
		if (!irqs->range[i])
			continue;
		pr_devel("cxl release irq range 0x%x: offset: 0x%lx  limit: %ld\n",
			 i, irqs->offset[i],
			 irqs->range[i]);
		hwirq = irqs->offset[i] - phb->msi_base;
		msi_bitmap_free_hwirqs(&phb->msi_bmp, hwirq,
				       irqs->range[i]);
	}
}
EXPORT_SYMBOL(pnv_cxl_release_hwirq_ranges);

int pnv_cxl_alloc_hwirq_ranges(struct cxl_irq_ranges *irqs,
			       struct pci_dev *dev, int num)
{
	struct pci_controller *hose = pci_bus_to_host(dev->bus);
	struct pnv_phb *phb = hose->private_data;
	int i, hwirq, try;

	memset(irqs, 0, sizeof(struct cxl_irq_ranges));

	/* 0 is reserved for the multiplexed PSL DSI interrupt */
	for (i = 1; i < CXL_IRQ_RANGES && num; i++) {
		try = num;
		while (try) {
			hwirq = msi_bitmap_alloc_hwirqs(&phb->msi_bmp, try);
			if (hwirq >= 0)
				break;
			try /= 2;
		}
		if (!try)
			goto fail;

		irqs->offset[i] = phb->msi_base + hwirq;
		irqs->range[i] = try;
		pr_devel("cxl alloc irq range 0x%x: offset: 0x%lx  limit: %li\n",
			 i, irqs->offset[i], irqs->range[i]);
		num -= try;
	}
	if (num)
		goto fail;

	return 0;
fail:
	pnv_cxl_release_hwirq_ranges(irqs, dev);
	return -ENOSPC;
}
EXPORT_SYMBOL(pnv_cxl_alloc_hwirq_ranges);

int pnv_cxl_get_irq_count(struct pci_dev *dev)
{
	struct pci_controller *hose = pci_bus_to_host(dev->bus);
	struct pnv_phb *phb = hose->private_data;

	return phb->msi_bmp.irq_count;
}
EXPORT_SYMBOL(pnv_cxl_get_irq_count);

int pnv_cxl_ioda_msi_setup(struct pci_dev *dev, unsigned int hwirq,
			   unsigned int virq)
{
	struct pci_controller *hose = pci_bus_to_host(dev->bus);
	struct pnv_phb *phb = hose->private_data;
	unsigned int xive_num = hwirq - phb->msi_base;
	struct pnv_ioda_pe *pe;
	int rc;

	if (!(pe = pnv_ioda_get_pe(dev)))
		return -ENODEV;

	/* Assign XIVE to PE */
	rc = opal_pci_set_xive_pe(phb->opal_id, pe->pe_number, xive_num);
	if (rc) {
		pe_warn(pe, "%s: OPAL error %d setting msi_base 0x%x "
			"hwirq 0x%x XIVE 0x%x PE\n",
			pci_name(dev), rc, phb->msi_base, hwirq, xive_num);
		return -EIO;
	}
	set_msi_irq_chip(phb, virq);

	return 0;
}
EXPORT_SYMBOL(pnv_cxl_ioda_msi_setup);
#endif

2813
static int pnv_pci_ioda_msi_setup(struct pnv_phb *phb, struct pci_dev *dev,
2814 2815
				  unsigned int hwirq, unsigned int virq,
				  unsigned int is_64, struct msi_msg *msg)
2816 2817 2818
{
	struct pnv_ioda_pe *pe = pnv_ioda_get_pe(dev);
	unsigned int xive_num = hwirq - phb->msi_base;
2819
	__be32 data;
2820 2821 2822 2823 2824 2825 2826 2827 2828 2829
	int rc;

	/* No PE assigned ? bail out ... no MSI for you ! */
	if (pe == NULL)
		return -ENXIO;

	/* Check if we have an MVE */
	if (pe->mve_number < 0)
		return -ENXIO;

2830
	/* Force 32-bit MSI on some broken devices */
2831
	if (dev->no_64bit_msi)
2832 2833
		is_64 = 0;

2834 2835 2836 2837 2838 2839 2840 2841 2842
	/* Assign XIVE to PE */
	rc = opal_pci_set_xive_pe(phb->opal_id, pe->pe_number, xive_num);
	if (rc) {
		pr_warn("%s: OPAL error %d setting XIVE %d PE\n",
			pci_name(dev), rc, xive_num);
		return -EIO;
	}

	if (is_64) {
2843 2844
		__be64 addr64;

2845 2846 2847 2848 2849 2850 2851
		rc = opal_get_msi_64(phb->opal_id, pe->mve_number, xive_num, 1,
				     &addr64, &data);
		if (rc) {
			pr_warn("%s: OPAL error %d getting 64-bit MSI data\n",
				pci_name(dev), rc);
			return -EIO;
		}
2852 2853
		msg->address_hi = be64_to_cpu(addr64) >> 32;
		msg->address_lo = be64_to_cpu(addr64) & 0xfffffffful;
2854
	} else {
2855 2856
		__be32 addr32;

2857 2858 2859 2860 2861 2862 2863 2864
		rc = opal_get_msi_32(phb->opal_id, pe->mve_number, xive_num, 1,
				     &addr32, &data);
		if (rc) {
			pr_warn("%s: OPAL error %d getting 32-bit MSI data\n",
				pci_name(dev), rc);
			return -EIO;
		}
		msg->address_hi = 0;
2865
		msg->address_lo = be32_to_cpu(addr32);
2866
	}
2867
	msg->data = be32_to_cpu(data);
2868

2869
	set_msi_irq_chip(phb, virq);
2870

2871 2872 2873 2874 2875 2876 2877 2878 2879 2880
	pr_devel("%s: %s-bit MSI on hwirq %x (xive #%d),"
		 " address=%x_%08x data=%x PE# %d\n",
		 pci_name(dev), is_64 ? "64" : "32", hwirq, xive_num,
		 msg->address_hi, msg->address_lo, data, pe->pe_number);

	return 0;
}

static void pnv_pci_init_ioda_msis(struct pnv_phb *phb)
{
2881
	unsigned int count;
2882 2883 2884 2885 2886 2887 2888 2889 2890 2891
	const __be32 *prop = of_get_property(phb->hose->dn,
					     "ibm,opal-msi-ranges", NULL);
	if (!prop) {
		/* BML Fallback */
		prop = of_get_property(phb->hose->dn, "msi-ranges", NULL);
	}
	if (!prop)
		return;

	phb->msi_base = be32_to_cpup(prop);
2892 2893
	count = be32_to_cpup(prop + 1);
	if (msi_bitmap_alloc(&phb->msi_bmp, count, phb->hose->dn)) {
2894 2895 2896 2897
		pr_err("PCI %d: Failed to allocate MSI bitmap !\n",
		       phb->hose->global_number);
		return;
	}
2898

2899 2900 2901
	phb->msi_setup = pnv_pci_ioda_msi_setup;
	phb->msi32_support = 1;
	pr_info("  Allocated bitmap for %d MSIs (base IRQ 0x%x)\n",
2902
		count, phb->msi_base);
2903 2904 2905 2906 2907
}
#else
static void pnv_pci_init_ioda_msis(struct pnv_phb *phb) { }
#endif /* CONFIG_PCI_MSI */

2908 2909 2910
#ifdef CONFIG_PCI_IOV
static void pnv_pci_ioda_fixup_iov_resources(struct pci_dev *pdev)
{
2911 2912 2913
	struct pci_controller *hose = pci_bus_to_host(pdev->bus);
	struct pnv_phb *phb = hose->private_data;
	const resource_size_t gate = phb->ioda.m64_segsize >> 2;
2914 2915
	struct resource *res;
	int i;
2916
	resource_size_t size, total_vf_bar_sz;
2917
	struct pci_dn *pdn;
2918
	int mul, total_vfs;
2919 2920 2921 2922 2923 2924

	if (!pdev->is_physfn || pdev->is_added)
		return;

	pdn = pci_get_pdn(pdev);
	pdn->vfs_expanded = 0;
2925
	pdn->m64_single_mode = false;
2926

2927
	total_vfs = pci_sriov_get_totalvfs(pdev);
2928
	mul = phb->ioda.total_pe_num;
2929
	total_vf_bar_sz = 0;
2930 2931 2932 2933 2934 2935

	for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
		res = &pdev->resource[i + PCI_IOV_RESOURCES];
		if (!res->flags || res->parent)
			continue;
		if (!pnv_pci_is_mem_pref_64(res->flags)) {
2936 2937
			dev_warn(&pdev->dev, "Don't support SR-IOV with"
					" non M64 VF BAR%d: %pR. \n",
2938
				 i, res);
2939
			goto truncate_iov;
2940 2941
		}

2942 2943
		total_vf_bar_sz += pci_iov_resource_size(pdev,
				i + PCI_IOV_RESOURCES);
2944

2945 2946 2947 2948 2949 2950 2951 2952 2953 2954 2955 2956
		/*
		 * If bigger than quarter of M64 segment size, just round up
		 * power of two.
		 *
		 * Generally, one M64 BAR maps one IOV BAR. To avoid conflict
		 * with other devices, IOV BAR size is expanded to be
		 * (total_pe * VF_BAR_size).  When VF_BAR_size is half of M64
		 * segment size , the expanded size would equal to half of the
		 * whole M64 space size, which will exhaust the M64 Space and
		 * limit the system flexibility.  This is a design decision to
		 * set the boundary to quarter of the M64 segment size.
		 */
2957
		if (total_vf_bar_sz > gate) {
2958
			mul = roundup_pow_of_two(total_vfs);
2959 2960 2961
			dev_info(&pdev->dev,
				"VF BAR Total IOV size %llx > %llx, roundup to %d VFs\n",
				total_vf_bar_sz, gate, mul);
2962
			pdn->m64_single_mode = true;
2963 2964 2965 2966
			break;
		}
	}

2967 2968 2969 2970 2971 2972
	for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
		res = &pdev->resource[i + PCI_IOV_RESOURCES];
		if (!res->flags || res->parent)
			continue;

		size = pci_iov_resource_size(pdev, i + PCI_IOV_RESOURCES);
2973 2974 2975 2976 2977 2978 2979
		/*
		 * On PHB3, the minimum size alignment of M64 BAR in single
		 * mode is 32MB.
		 */
		if (pdn->m64_single_mode && (size < SZ_32M))
			goto truncate_iov;
		dev_dbg(&pdev->dev, " Fixing VF BAR%d: %pR to\n", i, res);
2980
		res->end = res->start + size * mul - 1;
2981 2982
		dev_dbg(&pdev->dev, "                       %pR\n", res);
		dev_info(&pdev->dev, "VF BAR%d: %pR (expanded to %d VFs for PE alignment)",
2983
			 i, res, mul);
2984
	}
2985
	pdn->vfs_expanded = mul;
2986 2987 2988 2989 2990 2991 2992 2993 2994 2995

	return;

truncate_iov:
	/* To save MMIO space, IOV BAR is truncated. */
	for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
		res = &pdev->resource[i + PCI_IOV_RESOURCES];
		res->flags = 0;
		res->end = res->start - 1;
	}
2996 2997 2998
}
#endif /* CONFIG_PCI_IOV */

2999 3000 3001 3002 3003 3004 3005 3006 3007 3008 3009 3010 3011 3012 3013 3014 3015 3016 3017 3018 3019 3020 3021 3022 3023 3024 3025 3026 3027 3028 3029 3030 3031 3032 3033 3034 3035 3036 3037 3038 3039 3040 3041 3042 3043 3044 3045 3046 3047 3048 3049 3050 3051 3052 3053 3054 3055
static void pnv_ioda_setup_pe_res(struct pnv_ioda_pe *pe,
				  struct resource *res)
{
	struct pnv_phb *phb = pe->phb;
	struct pci_bus_region region;
	int index;
	int64_t rc;

	if (!res || !res->flags || res->start > res->end)
		return;

	if (res->flags & IORESOURCE_IO) {
		region.start = res->start - phb->ioda.io_pci_base;
		region.end   = res->end - phb->ioda.io_pci_base;
		index = region.start / phb->ioda.io_segsize;

		while (index < phb->ioda.total_pe_num &&
		       region.start <= region.end) {
			phb->ioda.io_segmap[index] = pe->pe_number;
			rc = opal_pci_map_pe_mmio_window(phb->opal_id,
				pe->pe_number, OPAL_IO_WINDOW_TYPE, 0, index);
			if (rc != OPAL_SUCCESS) {
				pr_err("%s: Error %lld mapping IO segment#%d to PE#%d\n",
				       __func__, rc, index, pe->pe_number);
				break;
			}

			region.start += phb->ioda.io_segsize;
			index++;
		}
	} else if ((res->flags & IORESOURCE_MEM) &&
		   !pnv_pci_is_mem_pref_64(res->flags)) {
		region.start = res->start -
			       phb->hose->mem_offset[0] -
			       phb->ioda.m32_pci_base;
		region.end   = res->end -
			       phb->hose->mem_offset[0] -
			       phb->ioda.m32_pci_base;
		index = region.start / phb->ioda.m32_segsize;

		while (index < phb->ioda.total_pe_num &&
		       region.start <= region.end) {
			phb->ioda.m32_segmap[index] = pe->pe_number;
			rc = opal_pci_map_pe_mmio_window(phb->opal_id,
				pe->pe_number, OPAL_M32_WINDOW_TYPE, 0, index);
			if (rc != OPAL_SUCCESS) {
				pr_err("%s: Error %lld mapping M32 segment#%d to PE#%d",
				       __func__, rc, index, pe->pe_number);
				break;
			}

			region.start += phb->ioda.m32_segsize;
			index++;
		}
	}
}

3056 3057 3058 3059 3060
/*
 * This function is supposed to be called on basis of PE from top
 * to bottom style. So the the I/O or MMIO segment assigned to
 * parent PE could be overrided by its child PEs if necessary.
 */
3061
static void pnv_ioda_setup_pe_seg(struct pnv_ioda_pe *pe)
3062
{
3063
	struct pci_dev *pdev;
3064
	int i;
3065 3066 3067 3068 3069 3070 3071 3072

	/*
	 * NOTE: We only care PCI bus based PE for now. For PCI
	 * device based PE, for example SRIOV sensitive VF should
	 * be figured out later.
	 */
	BUG_ON(!(pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL)));

3073 3074 3075 3076 3077 3078 3079 3080 3081 3082 3083 3084 3085 3086 3087
	list_for_each_entry(pdev, &pe->pbus->devices, bus_list) {
		for (i = 0; i <= PCI_ROM_RESOURCE; i++)
			pnv_ioda_setup_pe_res(pe, &pdev->resource[i]);

		/*
		 * If the PE contains all subordinate PCI buses, the
		 * windows of the child bridges should be mapped to
		 * the PE as well.
		 */
		if (!(pe->flags & PNV_IODA_PE_BUS_ALL) || !pci_is_bridge(pdev))
			continue;
		for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++)
			pnv_ioda_setup_pe_res(pe,
				&pdev->resource[PCI_BRIDGE_RESOURCES + i]);
	}
3088 3089
}

3090
static void pnv_pci_ioda_setup_seg(void)
3091 3092 3093 3094 3095 3096 3097
{
	struct pci_controller *tmp, *hose;
	struct pnv_phb *phb;
	struct pnv_ioda_pe *pe;

	list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
		phb = hose->private_data;
3098 3099 3100 3101 3102

		/* NPU PHB does not support IO or MMIO segmentation */
		if (phb->type == PNV_PHB_NPU)
			continue;

3103
		list_for_each_entry(pe, &phb->ioda.pe_list, list) {
3104
			pnv_ioda_setup_pe_seg(pe);
3105 3106 3107 3108
		}
	}
}

3109
static void pnv_pci_ioda_setup_DMA(void)
3110 3111
{
	struct pci_controller *hose, *tmp;
3112
	struct pnv_phb *phb;
3113 3114 3115

	list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
		pnv_ioda_setup_dma(hose->private_data);
3116 3117 3118 3119

		/* Mark the PHB initialization done */
		phb = hose->private_data;
		phb->initialized = 1;
3120 3121 3122
	}
}

3123 3124 3125 3126 3127 3128 3129 3130 3131 3132 3133 3134 3135 3136 3137 3138 3139 3140 3141
static void pnv_pci_ioda_create_dbgfs(void)
{
#ifdef CONFIG_DEBUG_FS
	struct pci_controller *hose, *tmp;
	struct pnv_phb *phb;
	char name[16];

	list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
		phb = hose->private_data;

		sprintf(name, "PCI%04x", hose->global_number);
		phb->dbgfs = debugfs_create_dir(name, powerpc_debugfs_root);
		if (!phb->dbgfs)
			pr_warning("%s: Error on creating debugfs on PHB#%x\n",
				__func__, hose->global_number);
	}
#endif /* CONFIG_DEBUG_FS */
}

3142 3143 3144 3145 3146 3147
static void pnv_npu_ioda_fixup(void)
{
	bool enable_bypass;
	struct pci_controller *hose, *tmp;
	struct pnv_phb *phb;
	struct pnv_ioda_pe *pe;
3148
	unsigned int weight;
3149 3150 3151 3152 3153 3154

	list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
		phb = hose->private_data;
		if (phb->type != PNV_PHB_NPU)
			continue;

3155 3156 3157 3158 3159
		list_for_each_entry(pe, &phb->ioda.pe_list, list) {
			weight = pnv_pci_ioda_pe_dma_weight(pe);
			if (WARN_ON(!weight))
				continue;

3160 3161 3162 3163 3164 3165 3166 3167
			enable_bypass = dma_get_mask(&pe->pdev->dev) ==
				DMA_BIT_MASK(64);
			pnv_npu_init_dma_pe(pe);
			pnv_npu_dma_set_bypass(pe, enable_bypass);
		}
	}
}

3168
static void pnv_pci_ioda_fixup(void)
3169 3170
{
	pnv_pci_ioda_setup_PEs();
3171
	pnv_pci_ioda_setup_seg();
3172
	pnv_pci_ioda_setup_DMA();
3173

3174 3175
	pnv_pci_ioda_create_dbgfs();

3176 3177
#ifdef CONFIG_EEH
	eeh_init();
M
Mike Qiu 已提交
3178
	eeh_addr_cache_build();
3179
#endif
3180 3181 3182

	/* Link NPU IODA tables to their PCI devices. */
	pnv_npu_ioda_fixup();
3183 3184
}

3185 3186 3187 3188 3189 3190 3191 3192 3193 3194 3195 3196 3197 3198 3199 3200 3201 3202 3203 3204 3205 3206 3207 3208 3209 3210 3211 3212 3213 3214 3215
/*
 * Returns the alignment for I/O or memory windows for P2P
 * bridges. That actually depends on how PEs are segmented.
 * For now, we return I/O or M32 segment size for PE sensitive
 * P2P bridges. Otherwise, the default values (4KiB for I/O,
 * 1MiB for memory) will be returned.
 *
 * The current PCI bus might be put into one PE, which was
 * create against the parent PCI bridge. For that case, we
 * needn't enlarge the alignment so that we can save some
 * resources.
 */
static resource_size_t pnv_pci_window_alignment(struct pci_bus *bus,
						unsigned long type)
{
	struct pci_dev *bridge;
	struct pci_controller *hose = pci_bus_to_host(bus);
	struct pnv_phb *phb = hose->private_data;
	int num_pci_bridges = 0;

	bridge = bus->self;
	while (bridge) {
		if (pci_pcie_type(bridge) == PCI_EXP_TYPE_PCI_BRIDGE) {
			num_pci_bridges++;
			if (num_pci_bridges >= 2)
				return 1;
		}

		bridge = bridge->bus->self;
	}

3216 3217 3218 3219
	/* We fail back to M32 if M64 isn't supported */
	if (phb->ioda.m64_segsize &&
	    pnv_pci_is_mem_pref_64(type))
		return phb->ioda.m64_segsize;
3220 3221 3222 3223 3224 3225
	if (type & IORESOURCE_MEM)
		return phb->ioda.m32_segsize;

	return phb->ioda.io_segsize;
}

3226 3227 3228 3229
#ifdef CONFIG_PCI_IOV
static resource_size_t pnv_pci_iov_resource_alignment(struct pci_dev *pdev,
						      int resno)
{
3230 3231
	struct pci_controller *hose = pci_bus_to_host(pdev->bus);
	struct pnv_phb *phb = hose->private_data;
3232
	struct pci_dn *pdn = pci_get_pdn(pdev);
3233
	resource_size_t align;
3234

3235 3236 3237 3238 3239
	/*
	 * On PowerNV platform, IOV BAR is mapped by M64 BAR to enable the
	 * SR-IOV. While from hardware perspective, the range mapped by M64
	 * BAR should be size aligned.
	 *
3240 3241 3242 3243 3244 3245 3246
	 * When IOV BAR is mapped with M64 BAR in Single PE mode, the extra
	 * powernv-specific hardware restriction is gone. But if just use the
	 * VF BAR size as the alignment, PF BAR / VF BAR may be allocated with
	 * in one segment of M64 #15, which introduces the PE conflict between
	 * PF and VF. Based on this, the minimum alignment of an IOV BAR is
	 * m64_segsize.
	 *
3247 3248
	 * This function returns the total IOV BAR size if M64 BAR is in
	 * Shared PE mode or just VF BAR size if not.
3249 3250
	 * If the M64 BAR is in Single PE mode, return the VF BAR size or
	 * M64 segment size if IOV BAR size is less.
3251
	 */
3252
	align = pci_iov_resource_size(pdev, resno);
3253 3254
	if (!pdn->vfs_expanded)
		return align;
3255 3256
	if (pdn->m64_single_mode)
		return max(align, (resource_size_t)phb->ioda.m64_segsize);
3257

3258
	return pdn->vfs_expanded * align;
3259 3260 3261
}
#endif /* CONFIG_PCI_IOV */

3262 3263 3264
/* Prevent enabling devices for which we couldn't properly
 * assign a PE
 */
3265
static bool pnv_pci_enable_device_hook(struct pci_dev *dev)
3266
{
3267 3268 3269
	struct pci_controller *hose = pci_bus_to_host(dev->bus);
	struct pnv_phb *phb = hose->private_data;
	struct pci_dn *pdn;
3270

3271 3272 3273 3274 3275 3276
	/* The function is probably called while the PEs have
	 * not be created yet. For example, resource reassignment
	 * during PCI probe period. We just skip the check if
	 * PEs isn't ready.
	 */
	if (!phb->initialized)
3277
		return true;
3278

3279
	pdn = pci_get_pdn(dev);
3280
	if (!pdn || pdn->pe_number == IODA_INVALID_PE)
3281
		return false;
3282

3283
	return true;
3284 3285
}

3286
static void pnv_pci_ioda_shutdown(struct pci_controller *hose)
3287
{
3288 3289
	struct pnv_phb *phb = hose->private_data;

3290
	opal_pci_reset(phb->opal_id, OPAL_RESET_PCI_IODA_TABLE,
3291 3292 3293
		       OPAL_ASSERT_RESET);
}

3294
static const struct pci_controller_ops pnv_pci_ioda_controller_ops = {
3295 3296
	.dma_dev_setup		= pnv_pci_dma_dev_setup,
	.dma_bus_setup		= pnv_pci_dma_bus_setup,
3297
#ifdef CONFIG_PCI_MSI
3298 3299
	.setup_msi_irqs		= pnv_setup_msi_irqs,
	.teardown_msi_irqs	= pnv_teardown_msi_irqs,
3300
#endif
3301 3302 3303 3304 3305 3306
	.enable_device_hook	= pnv_pci_enable_device_hook,
	.window_alignment	= pnv_pci_window_alignment,
	.reset_secondary_bus	= pnv_pci_reset_secondary_bus,
	.dma_set_mask		= pnv_pci_ioda_dma_set_mask,
	.dma_get_required_mask	= pnv_pci_ioda_dma_get_required_mask,
	.shutdown		= pnv_pci_ioda_shutdown,
3307 3308
};

3309
static const struct pci_controller_ops pnv_npu_ioda_controller_ops = {
3310
	.dma_dev_setup		= pnv_pci_dma_dev_setup,
3311
#ifdef CONFIG_PCI_MSI
3312 3313
	.setup_msi_irqs		= pnv_setup_msi_irqs,
	.teardown_msi_irqs	= pnv_teardown_msi_irqs,
3314
#endif
3315 3316 3317 3318 3319
	.enable_device_hook	= pnv_pci_enable_device_hook,
	.window_alignment	= pnv_pci_window_alignment,
	.reset_secondary_bus	= pnv_pci_reset_secondary_bus,
	.dma_set_mask		= pnv_npu_dma_set_mask,
	.shutdown		= pnv_pci_ioda_shutdown,
3320 3321
};

3322 3323
static void __init pnv_pci_init_ioda_phb(struct device_node *np,
					 u64 hub_id, int ioda_type)
3324 3325 3326
{
	struct pci_controller *hose;
	struct pnv_phb *phb;
3327 3328
	unsigned long size, m64map_off, m32map_off, pemap_off;
	unsigned long iomap_off = 0, dma32map_off = 0;
3329
	const __be64 *prop64;
3330
	const __be32 *prop32;
3331
	int len;
3332
	unsigned int segno;
3333 3334 3335 3336
	u64 phb_id;
	void *aux;
	long rc;

3337
	pr_info("Initializing IODA%d OPAL PHB %s\n", ioda_type, np->full_name);
3338 3339 3340 3341 3342 3343 3344 3345 3346

	prop64 = of_get_property(np, "ibm,opal-phbid", NULL);
	if (!prop64) {
		pr_err("  Missing \"ibm,opal-phbid\" property !\n");
		return;
	}
	phb_id = be64_to_cpup(prop64);
	pr_debug("  PHB-ID  : 0x%016llx\n", phb_id);

3347
	phb = memblock_virt_alloc(sizeof(struct pnv_phb), 0);
3348 3349 3350 3351 3352

	/* Allocate PCI controller */
	phb->hose = hose = pcibios_alloc_controller(np);
	if (!phb->hose) {
		pr_err("  Can't allocate PCI controller for %s\n",
3353
		       np->full_name);
3354
		memblock_free(__pa(phb), sizeof(struct pnv_phb));
3355 3356 3357 3358
		return;
	}

	spin_lock_init(&phb->lock);
3359 3360
	prop32 = of_get_property(np, "bus-range", &len);
	if (prop32 && len == 8) {
3361 3362
		hose->first_busno = be32_to_cpu(prop32[0]);
		hose->last_busno = be32_to_cpu(prop32[1]);
3363 3364 3365 3366 3367
	} else {
		pr_warn("  Broken <bus-range> on %s\n", np->full_name);
		hose->first_busno = 0;
		hose->last_busno = 0xff;
	}
3368
	hose->private_data = phb;
3369
	phb->hub_id = hub_id;
3370
	phb->opal_id = phb_id;
G
Gavin Shan 已提交
3371
	phb->type = ioda_type;
3372
	mutex_init(&phb->ioda.pe_alloc_mutex);
3373

3374 3375 3376
	/* Detect specific models for error handling */
	if (of_device_is_compatible(np, "ibm,p7ioc-pciex"))
		phb->model = PNV_PHB_MODEL_P7IOC;
3377
	else if (of_device_is_compatible(np, "ibm,power8-pciex"))
G
Gavin Shan 已提交
3378
		phb->model = PNV_PHB_MODEL_PHB3;
3379 3380
	else if (of_device_is_compatible(np, "ibm,power8-npu-pciex"))
		phb->model = PNV_PHB_MODEL_NPU;
3381 3382 3383
	else
		phb->model = PNV_PHB_MODEL_UNKNOWN;

G
Gavin Shan 已提交
3384
	/* Parse 32-bit and IO ranges (if any) */
3385
	pci_process_bridge_OF_ranges(hose, np, !hose->global_number);
3386

G
Gavin Shan 已提交
3387
	/* Get registers */
3388 3389 3390 3391 3392
	phb->regs = of_iomap(np, 0);
	if (phb->regs == NULL)
		pr_err("  Failed to map registers !\n");

	/* Initialize more IODA stuff */
3393
	phb->ioda.total_pe_num = 1;
G
Gavin Shan 已提交
3394
	prop32 = of_get_property(np, "ibm,opal-num-pes", NULL);
3395
	if (prop32)
3396
		phb->ioda.total_pe_num = be32_to_cpup(prop32);
3397 3398
	prop32 = of_get_property(np, "ibm,opal-reserved-pe", NULL);
	if (prop32)
3399
		phb->ioda.reserved_pe_idx = be32_to_cpup(prop32);
3400 3401 3402 3403

	/* Parse 64-bit MMIO range */
	pnv_ioda_parse_m64_window(phb);

3404
	phb->ioda.m32_size = resource_size(&hose->mem_resources[0]);
G
Gavin Shan 已提交
3405
	/* FW Has already off top 64k of M32 space (MSI space) */
3406 3407
	phb->ioda.m32_size += 0x10000;

3408
	phb->ioda.m32_segsize = phb->ioda.m32_size / phb->ioda.total_pe_num;
3409
	phb->ioda.m32_pci_base = hose->mem_resources[0].start - hose->mem_offset[0];
3410
	phb->ioda.io_size = hose->pci_io_size;
3411
	phb->ioda.io_segsize = phb->ioda.io_size / phb->ioda.total_pe_num;
3412 3413
	phb->ioda.io_pci_base = 0; /* XXX calculate this ? */

3414 3415 3416 3417
	/* Calculate how many 32-bit TCE segments we have */
	phb->ioda.dma32_count = phb->ioda.m32_pci_base /
				PNV_IODA1_DMA32_SEGSIZE;

3418
	/* Allocate aux data & arrays. We don't have IO ports on PHB3 */
3419
	size = _ALIGN_UP(phb->ioda.total_pe_num / 8, sizeof(unsigned long));
3420 3421
	m64map_off = size;
	size += phb->ioda.total_pe_num * sizeof(phb->ioda.m64_segmap[0]);
3422
	m32map_off = size;
3423
	size += phb->ioda.total_pe_num * sizeof(phb->ioda.m32_segmap[0]);
3424 3425
	if (phb->type == PNV_PHB_IODA1) {
		iomap_off = size;
3426
		size += phb->ioda.total_pe_num * sizeof(phb->ioda.io_segmap[0]);
3427 3428 3429
		dma32map_off = size;
		size += phb->ioda.dma32_count *
			sizeof(phb->ioda.dma32_segmap[0]);
3430
	}
3431
	pemap_off = size;
3432
	size += phb->ioda.total_pe_num * sizeof(struct pnv_ioda_pe);
3433
	aux = memblock_virt_alloc(size, 0);
3434
	phb->ioda.pe_alloc = aux;
3435
	phb->ioda.m64_segmap = aux + m64map_off;
3436
	phb->ioda.m32_segmap = aux + m32map_off;
3437 3438
	for (segno = 0; segno < phb->ioda.total_pe_num; segno++) {
		phb->ioda.m64_segmap[segno] = IODA_INVALID_PE;
3439
		phb->ioda.m32_segmap[segno] = IODA_INVALID_PE;
3440
	}
3441
	if (phb->type == PNV_PHB_IODA1) {
3442
		phb->ioda.io_segmap = aux + iomap_off;
3443 3444
		for (segno = 0; segno < phb->ioda.total_pe_num; segno++)
			phb->ioda.io_segmap[segno] = IODA_INVALID_PE;
3445 3446 3447 3448

		phb->ioda.dma32_segmap = aux + dma32map_off;
		for (segno = 0; segno < phb->ioda.dma32_count; segno++)
			phb->ioda.dma32_segmap[segno] = IODA_INVALID_PE;
3449
	}
3450
	phb->ioda.pe_array = aux + pemap_off;
3451
	set_bit(phb->ioda.reserved_pe_idx, phb->ioda.pe_alloc);
3452 3453

	INIT_LIST_HEAD(&phb->ioda.pe_list);
3454
	mutex_init(&phb->ioda.pe_list_mutex);
3455 3456

	/* Calculate how many 32-bit TCE segments we have */
3457
	phb->ioda.dma32_count = phb->ioda.m32_pci_base /
3458
				PNV_IODA1_DMA32_SEGSIZE;
3459

G
Gavin Shan 已提交
3460
#if 0 /* We should really do that ... */
3461 3462 3463 3464 3465 3466 3467 3468
	rc = opal_pci_set_phb_mem_window(opal->phb_id,
					 window_type,
					 window_num,
					 starting_real_address,
					 starting_pci_address,
					 segment_size);
#endif

3469
	pr_info("  %03d (%03d) PE's M32: 0x%x [segment=0x%x]\n",
3470
		phb->ioda.total_pe_num, phb->ioda.reserved_pe_idx,
3471 3472 3473 3474 3475 3476 3477 3478
		phb->ioda.m32_size, phb->ioda.m32_segsize);
	if (phb->ioda.m64_size)
		pr_info("                 M64: 0x%lx [segment=0x%lx]\n",
			phb->ioda.m64_size, phb->ioda.m64_segsize);
	if (phb->ioda.io_size)
		pr_info("                  IO: 0x%x [segment=0x%x]\n",
			phb->ioda.io_size, phb->ioda.io_segsize);

3479 3480

	phb->hose->ops = &pnv_pci_ops;
G
Gavin Shan 已提交
3481 3482 3483
	phb->get_pe_state = pnv_ioda_get_pe_state;
	phb->freeze_pe = pnv_ioda_freeze_pe;
	phb->unfreeze_pe = pnv_ioda_unfreeze_pe;
3484 3485 3486 3487 3488 3489 3490

	/* Setup TCEs */
	phb->dma_dev_setup = pnv_pci_ioda_dma_dev_setup;

	/* Setup MSI support */
	pnv_pci_init_ioda_msis(phb);

3491 3492 3493 3494 3495 3496
	/*
	 * We pass the PCI probe flag PCI_REASSIGN_ALL_RSRC here
	 * to let the PCI core do resource assignment. It's supposed
	 * that the PCI core will do correct I/O and MMIO alignment
	 * for the P2P bridge bars so that each PCI bus (excluding
	 * the child P2P bridges) can form individual PE.
3497
	 */
3498
	ppc_md.pcibios_fixup = pnv_pci_ioda_fixup;
3499 3500 3501 3502 3503

	if (phb->type == PNV_PHB_NPU)
		hose->controller_ops = pnv_npu_ioda_controller_ops;
	else
		hose->controller_ops = pnv_pci_ioda_controller_ops;
3504

3505 3506
#ifdef CONFIG_PCI_IOV
	ppc_md.pcibios_fixup_sriov = pnv_pci_ioda_fixup_iov_resources;
3507
	ppc_md.pcibios_iov_resource_alignment = pnv_pci_iov_resource_alignment;
3508 3509
#endif

3510
	pci_add_flags(PCI_REASSIGN_ALL_RSRC);
3511 3512

	/* Reset IODA tables to a clean state */
3513
	rc = opal_pci_reset(phb_id, OPAL_RESET_PCI_IODA_TABLE, OPAL_ASSERT_RESET);
3514
	if (rc)
3515
		pr_warning("  OPAL Error %ld performing IODA table reset !\n", rc);
3516 3517 3518 3519 3520 3521 3522 3523

	/* If we're running in kdump kerenl, the previous kerenl never
	 * shutdown PCI devices correctly. We already got IODA table
	 * cleaned out. So we have to issue PHB reset to stop all PCI
	 * transactions from previous kerenl.
	 */
	if (is_kdump_kernel()) {
		pr_info("  Issue PHB reset ...\n");
3524 3525
		pnv_eeh_phb_reset(hose, EEH_RESET_FUNDAMENTAL);
		pnv_eeh_phb_reset(hose, EEH_RESET_DEACTIVATE);
3526
	}
3527

3528 3529
	/* Remove M64 resource if we can't configure it successfully */
	if (!phb->init_m64 || phb->init_m64(phb))
3530
		hose->mem_resources[1].flags = 0;
G
Gavin Shan 已提交
3531 3532
}

3533
void __init pnv_pci_init_ioda2_phb(struct device_node *np)
G
Gavin Shan 已提交
3534
{
3535
	pnv_pci_init_ioda_phb(np, 0, PNV_PHB_IODA2);
3536 3537
}

3538 3539 3540 3541 3542
void __init pnv_pci_init_npu_phb(struct device_node *np)
{
	pnv_pci_init_ioda_phb(np, 0, PNV_PHB_NPU);
}

3543 3544 3545
void __init pnv_pci_init_ioda_hub(struct device_node *np)
{
	struct device_node *phbn;
3546
	const __be64 *prop64;
3547 3548 3549 3550 3551 3552 3553 3554 3555 3556 3557 3558 3559 3560 3561 3562
	u64 hub_id;

	pr_info("Probing IODA IO-Hub %s\n", np->full_name);

	prop64 = of_get_property(np, "ibm,opal-hubid", NULL);
	if (!prop64) {
		pr_err(" Missing \"ibm,opal-hubid\" property !\n");
		return;
	}
	hub_id = be64_to_cpup(prop64);
	pr_devel(" HUB-ID : 0x%016llx\n", hub_id);

	/* Count child PHBs */
	for_each_child_of_node(np, phbn) {
		/* Look for IODA1 PHBs */
		if (of_device_is_compatible(phbn, "ibm,ioda-phb"))
3563
			pnv_pci_init_ioda_phb(phbn, hub_id, PNV_PHB_IODA1);
3564 3565
	}
}