sdhci-pci-core.c 47.7 KB
Newer Older
1 2 3 4 5 6 7 8 9 10 11 12 13 14
/*  linux/drivers/mmc/host/sdhci-pci.c - SDHCI on PCI bus interface
 *
 *  Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or (at
 * your option) any later version.
 *
 * Thanks to the following companies for their support:
 *
 *     - JMicron (hardware and technical support)
 */

15
#include <linux/string.h>
16 17
#include <linux/delay.h>
#include <linux/highmem.h>
18
#include <linux/module.h>
19 20
#include <linux/pci.h>
#include <linux/dma-mapping.h>
21
#include <linux/slab.h>
22
#include <linux/device.h>
23
#include <linux/mmc/host.h>
24
#include <linux/mmc/mmc.h>
25 26
#include <linux/scatterlist.h>
#include <linux/io.h>
27
#include <linux/gpio.h>
28
#include <linux/pm_runtime.h>
29
#include <linux/mmc/slot-gpio.h>
30
#include <linux/mmc/sdhci-pci-data.h>
31
#include <linux/acpi.h>
32

33 34
#include "cqhci.h"

35
#include "sdhci.h"
36
#include "sdhci-pci.h"
37

38 39
static void sdhci_pci_hw_reset(struct sdhci_host *host);

40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119
#ifdef CONFIG_PM_SLEEP
static int __sdhci_pci_suspend_host(struct sdhci_pci_chip *chip)
{
	int i, ret;

	for (i = 0; i < chip->num_slots; i++) {
		struct sdhci_pci_slot *slot = chip->slots[i];
		struct sdhci_host *host;

		if (!slot)
			continue;

		host = slot->host;

		if (chip->pm_retune && host->tuning_mode != SDHCI_TUNING_MODE_3)
			mmc_retune_needed(host->mmc);

		ret = sdhci_suspend_host(host);
		if (ret)
			goto err_pci_suspend;

		if (host->mmc->pm_flags & MMC_PM_WAKE_SDIO_IRQ)
			sdhci_enable_irq_wakeups(host);
	}

	return 0;

err_pci_suspend:
	while (--i >= 0)
		sdhci_resume_host(chip->slots[i]->host);
	return ret;
}

static int sdhci_pci_init_wakeup(struct sdhci_pci_chip *chip)
{
	mmc_pm_flag_t pm_flags = 0;
	int i;

	for (i = 0; i < chip->num_slots; i++) {
		struct sdhci_pci_slot *slot = chip->slots[i];

		if (slot)
			pm_flags |= slot->host->mmc->pm_flags;
	}

	return device_init_wakeup(&chip->pdev->dev,
				  (pm_flags & MMC_PM_KEEP_POWER) &&
				  (pm_flags & MMC_PM_WAKE_SDIO_IRQ));
}

static int sdhci_pci_suspend_host(struct sdhci_pci_chip *chip)
{
	int ret;

	ret = __sdhci_pci_suspend_host(chip);
	if (ret)
		return ret;

	sdhci_pci_init_wakeup(chip);

	return 0;
}

int sdhci_pci_resume_host(struct sdhci_pci_chip *chip)
{
	struct sdhci_pci_slot *slot;
	int i, ret;

	for (i = 0; i < chip->num_slots; i++) {
		slot = chip->slots[i];
		if (!slot)
			continue;

		ret = sdhci_resume_host(slot->host);
		if (ret)
			return ret;
	}

	return 0;
}
120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141

static int sdhci_cqhci_suspend(struct sdhci_pci_chip *chip)
{
	int ret;

	ret = cqhci_suspend(chip->slots[0]->host->mmc);
	if (ret)
		return ret;

	return sdhci_pci_suspend_host(chip);
}

static int sdhci_cqhci_resume(struct sdhci_pci_chip *chip)
{
	int ret;

	ret = sdhci_pci_resume_host(chip);
	if (ret)
		return ret;

	return cqhci_resume(chip->slots[0]->host->mmc);
}
142 143
#endif

144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191
#ifdef CONFIG_PM
static int sdhci_pci_runtime_suspend_host(struct sdhci_pci_chip *chip)
{
	struct sdhci_pci_slot *slot;
	struct sdhci_host *host;
	int i, ret;

	for (i = 0; i < chip->num_slots; i++) {
		slot = chip->slots[i];
		if (!slot)
			continue;

		host = slot->host;

		ret = sdhci_runtime_suspend_host(host);
		if (ret)
			goto err_pci_runtime_suspend;

		if (chip->rpm_retune &&
		    host->tuning_mode != SDHCI_TUNING_MODE_3)
			mmc_retune_needed(host->mmc);
	}

	return 0;

err_pci_runtime_suspend:
	while (--i >= 0)
		sdhci_runtime_resume_host(chip->slots[i]->host);
	return ret;
}

static int sdhci_pci_runtime_resume_host(struct sdhci_pci_chip *chip)
{
	struct sdhci_pci_slot *slot;
	int i, ret;

	for (i = 0; i < chip->num_slots; i++) {
		slot = chip->slots[i];
		if (!slot)
			continue;

		ret = sdhci_runtime_resume_host(slot->host);
		if (ret)
			return ret;
	}

	return 0;
}
192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213

static int sdhci_cqhci_runtime_suspend(struct sdhci_pci_chip *chip)
{
	int ret;

	ret = cqhci_suspend(chip->slots[0]->host->mmc);
	if (ret)
		return ret;

	return sdhci_pci_runtime_suspend_host(chip);
}

static int sdhci_cqhci_runtime_resume(struct sdhci_pci_chip *chip)
{
	int ret;

	ret = sdhci_pci_runtime_resume_host(chip);
	if (ret)
		return ret;

	return cqhci_resume(chip->slots[0]->host->mmc);
}
214 215
#endif

216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233
static u32 sdhci_cqhci_irq(struct sdhci_host *host, u32 intmask)
{
	int cmd_error = 0;
	int data_error = 0;

	if (!sdhci_cqe_irq(host, intmask, &cmd_error, &data_error))
		return intmask;

	cqhci_irq(host->mmc, intmask, cmd_error, data_error);

	return 0;
}

static void sdhci_pci_dumpregs(struct mmc_host *mmc)
{
	sdhci_dumpregs(mmc_priv(mmc));
}

234 235 236 237 238 239 240 241
/*****************************************************************************\
 *                                                                           *
 * Hardware specific quirk handling                                          *
 *                                                                           *
\*****************************************************************************/

static int ricoh_probe(struct sdhci_pci_chip *chip)
{
242 243
	if (chip->pdev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG ||
	    chip->pdev->subsystem_vendor == PCI_VENDOR_ID_SONY)
244
		chip->quirks |= SDHCI_QUIRK_NO_CARD_NO_RESET;
245 246 247 248 249 250 251 252
	return 0;
}

static int ricoh_mmc_probe_slot(struct sdhci_pci_slot *slot)
{
	slot->host->caps =
		((0x21 << SDHCI_TIMEOUT_CLK_SHIFT)
			& SDHCI_TIMEOUT_CLK_MASK) |
253

254 255 256 257 258
		((0x21 << SDHCI_CLOCK_BASE_SHIFT)
			& SDHCI_CLOCK_BASE_MASK) |

		SDHCI_TIMEOUT_CLK_UNIT |
		SDHCI_CAN_VDD_330 |
259
		SDHCI_CAN_DO_HISPD |
260 261 262 263
		SDHCI_CAN_DO_SDMA;
	return 0;
}

264
#ifdef CONFIG_PM_SLEEP
265 266 267 268 269 270
static int ricoh_mmc_resume(struct sdhci_pci_chip *chip)
{
	/* Apply a delay to allow controller to settle */
	/* Otherwise it becomes confused if card state changed
		during suspend */
	msleep(500);
271
	return sdhci_pci_resume_host(chip);
272
}
273
#endif
274 275 276

static const struct sdhci_pci_fixes sdhci_ricoh = {
	.probe		= ricoh_probe,
277 278 279
	.quirks		= SDHCI_QUIRK_32BIT_DMA_ADDR |
			  SDHCI_QUIRK_FORCE_DMA |
			  SDHCI_QUIRK_CLOCK_BEFORE_RESET,
280 281
};

282 283
static const struct sdhci_pci_fixes sdhci_ricoh_mmc = {
	.probe_slot	= ricoh_mmc_probe_slot,
284
#ifdef CONFIG_PM_SLEEP
285
	.resume		= ricoh_mmc_resume,
286
#endif
287 288 289 290 291 292
	.quirks		= SDHCI_QUIRK_32BIT_DMA_ADDR |
			  SDHCI_QUIRK_CLOCK_BEFORE_RESET |
			  SDHCI_QUIRK_NO_CARD_NO_RESET |
			  SDHCI_QUIRK_MISSING_CAPS
};

293 294 295 296 297 298 299 300 301 302 303 304 305
static const struct sdhci_pci_fixes sdhci_ene_712 = {
	.quirks		= SDHCI_QUIRK_SINGLE_POWER_WRITE |
			  SDHCI_QUIRK_BROKEN_DMA,
};

static const struct sdhci_pci_fixes sdhci_ene_714 = {
	.quirks		= SDHCI_QUIRK_SINGLE_POWER_WRITE |
			  SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS |
			  SDHCI_QUIRK_BROKEN_DMA,
};

static const struct sdhci_pci_fixes sdhci_cafe = {
	.quirks		= SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER |
306
			  SDHCI_QUIRK_NO_BUSY_IRQ |
307
			  SDHCI_QUIRK_BROKEN_CARD_DETECTION |
308
			  SDHCI_QUIRK_BROKEN_TIMEOUT_VAL,
309 310
};

311 312 313 314
static const struct sdhci_pci_fixes sdhci_intel_qrk = {
	.quirks		= SDHCI_QUIRK_NO_HISPD_BIT,
};

315 316 317 318 319 320
static int mrst_hc_probe_slot(struct sdhci_pci_slot *slot)
{
	slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA;
	return 0;
}

321 322 323 324
/*
 * ADMA operation is disabled for Moorestown platform due to
 * hardware bugs.
 */
325
static int mrst_hc_probe(struct sdhci_pci_chip *chip)
326 327
{
	/*
328 329
	 * slots number is fixed here for MRST as SDIO3/5 are never used and
	 * have hardware bugs.
330 331 332 333 334
	 */
	chip->num_slots = 1;
	return 0;
}

335 336 337 338 339 340
static int pch_hc_probe_slot(struct sdhci_pci_slot *slot)
{
	slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA;
	return 0;
}

341
#ifdef CONFIG_PM
342

343
static irqreturn_t sdhci_pci_sd_cd(int irq, void *dev_id)
344 345 346 347 348 349 350 351
{
	struct sdhci_pci_slot *slot = dev_id;
	struct sdhci_host *host = slot->host;

	mmc_detect_change(host->mmc, msecs_to_jiffies(200));
	return IRQ_HANDLED;
}

352
static void sdhci_pci_add_own_cd(struct sdhci_pci_slot *slot)
353
{
354
	int err, irq, gpio = slot->cd_gpio;
355 356 357 358

	slot->cd_gpio = -EINVAL;
	slot->cd_irq = -EINVAL;

359 360 361
	if (!gpio_is_valid(gpio))
		return;

362
	err = devm_gpio_request(&slot->chip->pdev->dev, gpio, "sd_cd");
363 364 365 366 367 368 369 370 371 372 373
	if (err < 0)
		goto out;

	err = gpio_direction_input(gpio);
	if (err < 0)
		goto out_free;

	irq = gpio_to_irq(gpio);
	if (irq < 0)
		goto out_free;

374
	err = request_irq(irq, sdhci_pci_sd_cd, IRQF_TRIGGER_RISING |
375 376 377 378 379 380 381
			  IRQF_TRIGGER_FALLING, "sd_cd", slot);
	if (err)
		goto out_free;

	slot->cd_gpio = gpio;
	slot->cd_irq = irq;

382
	return;
383 384

out_free:
385
	devm_gpio_free(&slot->chip->pdev->dev, gpio);
386 387 388 389
out:
	dev_warn(&slot->chip->pdev->dev, "failed to setup card detect wake up\n");
}

390
static void sdhci_pci_remove_own_cd(struct sdhci_pci_slot *slot)
391 392 393 394 395 396 397
{
	if (slot->cd_irq >= 0)
		free_irq(slot->cd_irq, slot);
}

#else

398 399 400 401 402 403 404
static inline void sdhci_pci_add_own_cd(struct sdhci_pci_slot *slot)
{
}

static inline void sdhci_pci_remove_own_cd(struct sdhci_pci_slot *slot)
{
}
405 406 407

#endif

408 409
static int mfd_emmc_probe_slot(struct sdhci_pci_slot *slot)
{
410
	slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE;
411
	slot->host->mmc->caps2 |= MMC_CAP2_BOOTPART_NOACC;
412 413 414
	return 0;
}

415 416
static int mfd_sdio_probe_slot(struct sdhci_pci_slot *slot)
{
417
	slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE;
418 419 420
	return 0;
}

421 422
static const struct sdhci_pci_fixes sdhci_intel_mrst_hc0 = {
	.quirks		= SDHCI_QUIRK_BROKEN_ADMA | SDHCI_QUIRK_NO_HISPD_BIT,
423
	.probe_slot	= mrst_hc_probe_slot,
424 425
};

426
static const struct sdhci_pci_fixes sdhci_intel_mrst_hc1_hc2 = {
427
	.quirks		= SDHCI_QUIRK_BROKEN_ADMA | SDHCI_QUIRK_NO_HISPD_BIT,
428
	.probe		= mrst_hc_probe,
429 430
};

431 432
static const struct sdhci_pci_fixes sdhci_intel_mfd_sd = {
	.quirks		= SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
433
	.allow_runtime_pm = true,
434
	.own_cd_for_runtime_pm = true,
435 436
};

437 438
static const struct sdhci_pci_fixes sdhci_intel_mfd_sdio = {
	.quirks		= SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
439
	.quirks2	= SDHCI_QUIRK2_HOST_OFF_CARD_ON,
440
	.allow_runtime_pm = true,
441
	.probe_slot	= mfd_sdio_probe_slot,
442 443 444
};

static const struct sdhci_pci_fixes sdhci_intel_mfd_emmc = {
445
	.quirks		= SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
446
	.allow_runtime_pm = true,
447
	.probe_slot	= mfd_emmc_probe_slot,
448 449
};

450 451 452 453 454
static const struct sdhci_pci_fixes sdhci_intel_pch_sdio = {
	.quirks		= SDHCI_QUIRK_BROKEN_ADMA,
	.probe_slot	= pch_hc_probe_slot,
};

455 456
enum {
	INTEL_DSM_FNS		=  0,
457
	INTEL_DSM_V18_SWITCH	=  3,
458
	INTEL_DSM_DRV_STRENGTH	=  9,
459 460 461 462 463
	INTEL_DSM_D3_RETUNE	= 10,
};

struct intel_host {
	u32	dsm_fns;
464
	int	drv_strength;
465 466 467
	bool	d3_retune;
};

468
static const guid_t intel_dsm_guid =
469 470
	GUID_INIT(0xF6C13EA5, 0x65CD, 0x461F,
		  0xAB, 0x7A, 0x29, 0xF7, 0xE8, 0xD5, 0xBD, 0x61);
471 472 473 474 475 476

static int __intel_dsm(struct intel_host *intel_host, struct device *dev,
		       unsigned int fn, u32 *result)
{
	union acpi_object *obj;
	int err = 0;
477
	size_t len;
478

479
	obj = acpi_evaluate_dsm(ACPI_HANDLE(dev), &intel_dsm_guid, 0, fn, NULL);
480 481 482 483 484 485 486 487
	if (!obj)
		return -EOPNOTSUPP;

	if (obj->type != ACPI_TYPE_BUFFER || obj->buffer.length < 1) {
		err = -EINVAL;
		goto out;
	}

488 489 490 491
	len = min_t(size_t, obj->buffer.length, 4);

	*result = 0;
	memcpy(result, obj->buffer.pointer, len);
492 493 494 495 496 497 498 499 500 501 502 503 504 505 506 507 508 509 510 511 512
out:
	ACPI_FREE(obj);

	return err;
}

static int intel_dsm(struct intel_host *intel_host, struct device *dev,
		     unsigned int fn, u32 *result)
{
	if (fn > 31 || !(intel_host->dsm_fns & (1 << fn)))
		return -EOPNOTSUPP;

	return __intel_dsm(intel_host, dev, fn, result);
}

static void intel_dsm_init(struct intel_host *intel_host, struct device *dev,
			   struct mmc_host *mmc)
{
	int err;
	u32 val;

513 514
	intel_host->d3_retune = true;

515 516 517 518 519 520 521 522 523 524
	err = __intel_dsm(intel_host, dev, INTEL_DSM_FNS, &intel_host->dsm_fns);
	if (err) {
		pr_debug("%s: DSM not supported, error %d\n",
			 mmc_hostname(mmc), err);
		return;
	}

	pr_debug("%s: DSM function mask %#x\n",
		 mmc_hostname(mmc), intel_host->dsm_fns);

525 526 527
	err = intel_dsm(intel_host, dev, INTEL_DSM_DRV_STRENGTH, &val);
	intel_host->drv_strength = err ? 0 : val;

528 529 530 531
	err = intel_dsm(intel_host, dev, INTEL_DSM_D3_RETUNE, &val);
	intel_host->d3_retune = err ? true : !!val;
}

532 533 534 535 536 537 538 539 540 541 542 543 544 545 546
static void sdhci_pci_int_hw_reset(struct sdhci_host *host)
{
	u8 reg;

	reg = sdhci_readb(host, SDHCI_POWER_CONTROL);
	reg |= 0x10;
	sdhci_writeb(host, reg, SDHCI_POWER_CONTROL);
	/* For eMMC, minimum is 1us but give it 9us for good measure */
	udelay(9);
	reg &= ~0x10;
	sdhci_writeb(host, reg, SDHCI_POWER_CONTROL);
	/* For eMMC, minimum is 200us but give it 300us for good measure */
	usleep_range(300, 1000);
}

547 548 549
static int intel_select_drive_strength(struct mmc_card *card,
				       unsigned int max_dtr, int host_drv,
				       int card_drv, int *drv_type)
550
{
551 552 553
	struct sdhci_host *host = mmc_priv(card->host);
	struct sdhci_pci_slot *slot = sdhci_priv(host);
	struct intel_host *intel_host = sdhci_pci_priv(slot);
554

555
	return intel_host->drv_strength;
556 557
}

558 559 560 561 562 563 564 565 566 567 568 569 570 571 572 573 574 575 576 577 578 579
static int bxt_get_cd(struct mmc_host *mmc)
{
	int gpio_cd = mmc_gpio_get_cd(mmc);
	struct sdhci_host *host = mmc_priv(mmc);
	unsigned long flags;
	int ret = 0;

	if (!gpio_cd)
		return 0;

	spin_lock_irqsave(&host->lock, flags);

	if (host->flags & SDHCI_DEVICE_DEAD)
		goto out;

	ret = !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT);
out:
	spin_unlock_irqrestore(&host->lock, flags);

	return ret;
}

580 581 582 583 584 585 586 587 588 589 590 591 592 593 594 595 596 597 598 599 600 601 602 603 604 605 606 607
#define SDHCI_INTEL_PWR_TIMEOUT_CNT	20
#define SDHCI_INTEL_PWR_TIMEOUT_UDELAY	100

static void sdhci_intel_set_power(struct sdhci_host *host, unsigned char mode,
				  unsigned short vdd)
{
	int cntr;
	u8 reg;

	sdhci_set_power(host, mode, vdd);

	if (mode == MMC_POWER_OFF)
		return;

	/*
	 * Bus power might not enable after D3 -> D0 transition due to the
	 * present state not yet having propagated. Retry for up to 2ms.
	 */
	for (cntr = 0; cntr < SDHCI_INTEL_PWR_TIMEOUT_CNT; cntr++) {
		reg = sdhci_readb(host, SDHCI_POWER_CONTROL);
		if (reg & SDHCI_POWER_ON)
			break;
		udelay(SDHCI_INTEL_PWR_TIMEOUT_UDELAY);
		reg |= SDHCI_POWER_ON;
		sdhci_writeb(host, reg, SDHCI_POWER_CONTROL);
	}
}

608 609 610 611 612 613 614 615 616 617 618 619 620 621 622 623 624
#define INTEL_HS400_ES_REG 0x78
#define INTEL_HS400_ES_BIT BIT(0)

static void intel_hs400_enhanced_strobe(struct mmc_host *mmc,
					struct mmc_ios *ios)
{
	struct sdhci_host *host = mmc_priv(mmc);
	u32 val;

	val = sdhci_readl(host, INTEL_HS400_ES_REG);
	if (ios->enhanced_strobe)
		val |= INTEL_HS400_ES_BIT;
	else
		val &= ~INTEL_HS400_ES_BIT;
	sdhci_writel(host, val, INTEL_HS400_ES_REG);
}

625 626 627 628 629 630 631 632 633 634 635 636 637
static void sdhci_intel_voltage_switch(struct sdhci_host *host)
{
	struct sdhci_pci_slot *slot = sdhci_priv(host);
	struct intel_host *intel_host = sdhci_pci_priv(slot);
	struct device *dev = &slot->chip->pdev->dev;
	u32 result = 0;
	int err;

	err = intel_dsm(intel_host, dev, INTEL_DSM_V18_SWITCH, &result);
	pr_debug("%s: %s DSM error %d result %u\n",
		 mmc_hostname(host->mmc), __func__, err, result);
}

638 639 640 641
static const struct sdhci_ops sdhci_intel_byt_ops = {
	.set_clock		= sdhci_set_clock,
	.set_power		= sdhci_intel_set_power,
	.enable_dma		= sdhci_pci_enable_dma,
642
	.set_bus_width		= sdhci_set_bus_width,
643 644 645
	.reset			= sdhci_reset,
	.set_uhs_signaling	= sdhci_set_uhs_signaling,
	.hw_reset		= sdhci_pci_hw_reset,
646
	.voltage_switch		= sdhci_intel_voltage_switch,
647 648
};

649 650 651 652 653 654 655 656 657 658 659 660
static const struct sdhci_ops sdhci_intel_glk_ops = {
	.set_clock		= sdhci_set_clock,
	.set_power		= sdhci_intel_set_power,
	.enable_dma		= sdhci_pci_enable_dma,
	.set_bus_width		= sdhci_set_bus_width,
	.reset			= sdhci_reset,
	.set_uhs_signaling	= sdhci_set_uhs_signaling,
	.hw_reset		= sdhci_pci_hw_reset,
	.voltage_switch		= sdhci_intel_voltage_switch,
	.irq			= sdhci_cqhci_irq,
};

661 662 663 664 665 666 667 668 669 670
static void byt_read_dsm(struct sdhci_pci_slot *slot)
{
	struct intel_host *intel_host = sdhci_pci_priv(slot);
	struct device *dev = &slot->chip->pdev->dev;
	struct mmc_host *mmc = slot->host->mmc;

	intel_dsm_init(intel_host, dev, mmc);
	slot->chip->rpm_retune = intel_host->d3_retune;
}

671 672
static int byt_emmc_probe_slot(struct sdhci_pci_slot *slot)
{
673
	byt_read_dsm(slot);
674
	slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE |
675
				 MMC_CAP_HW_RESET | MMC_CAP_1_8V_DDR |
676
				 MMC_CAP_CMD_DURING_TFR |
677
				 MMC_CAP_WAIT_WHILE_BUSY;
678
	slot->hw_reset = sdhci_pci_int_hw_reset;
679 680
	if (slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BSW_EMMC)
		slot->host->timeout_clk = 1000; /* 1000 kHz i.e. 1 MHz */
681 682
	slot->host->mmc_host_ops.select_drive_strength =
						intel_select_drive_strength;
683 684 685
	return 0;
}

686 687 688 689
static int glk_emmc_probe_slot(struct sdhci_pci_slot *slot)
{
	int ret = byt_emmc_probe_slot(slot);

690 691
	slot->host->mmc->caps2 |= MMC_CAP2_CQE;

692 693 694 695
	if (slot->chip->pdev->device != PCI_DEVICE_ID_INTEL_GLK_EMMC) {
		slot->host->mmc->caps2 |= MMC_CAP2_HS400_ES,
		slot->host->mmc_host_ops.hs400_enhanced_strobe =
						intel_hs400_enhanced_strobe;
696
		slot->host->mmc->caps2 |= MMC_CAP2_CQE_DCMD;
697 698 699 700 701
	}

	return ret;
}

702 703 704 705 706 707 708 709 710 711 712 713 714 715 716 717 718 719 720 721 722 723 724 725 726 727 728 729 730 731 732 733 734 735 736 737 738 739 740 741 742 743 744 745 746 747 748 749 750 751 752 753 754 755 756 757 758 759 760 761 762 763 764 765 766
static void glk_cqe_enable(struct mmc_host *mmc)
{
	struct sdhci_host *host = mmc_priv(mmc);
	u32 reg;

	/*
	 * CQE gets stuck if it sees Buffer Read Enable bit set, which can be
	 * the case after tuning, so ensure the buffer is drained.
	 */
	reg = sdhci_readl(host, SDHCI_PRESENT_STATE);
	while (reg & SDHCI_DATA_AVAILABLE) {
		sdhci_readl(host, SDHCI_BUFFER);
		reg = sdhci_readl(host, SDHCI_PRESENT_STATE);
	}

	sdhci_cqe_enable(mmc);
}

static const struct cqhci_host_ops glk_cqhci_ops = {
	.enable		= glk_cqe_enable,
	.disable	= sdhci_cqe_disable,
	.dumpregs	= sdhci_pci_dumpregs,
};

static int glk_emmc_add_host(struct sdhci_pci_slot *slot)
{
	struct device *dev = &slot->chip->pdev->dev;
	struct sdhci_host *host = slot->host;
	struct cqhci_host *cq_host;
	bool dma64;
	int ret;

	ret = sdhci_setup_host(host);
	if (ret)
		return ret;

	cq_host = devm_kzalloc(dev, sizeof(*cq_host), GFP_KERNEL);
	if (!cq_host) {
		ret = -ENOMEM;
		goto cleanup;
	}

	cq_host->mmio = host->ioaddr + 0x200;
	cq_host->quirks |= CQHCI_QUIRK_SHORT_TXFR_DESC_SZ;
	cq_host->ops = &glk_cqhci_ops;

	dma64 = host->flags & SDHCI_USE_64_BIT_DMA;
	if (dma64)
		cq_host->caps |= CQHCI_TASK_DESC_SZ_128;

	ret = cqhci_init(cq_host, host->mmc, dma64);
	if (ret)
		goto cleanup;

	ret = __sdhci_add_host(host);
	if (ret)
		goto cleanup;

	return 0;

cleanup:
	sdhci_cleanup_host(host);
	return ret;
}

767 768 769 770 771 772 773 774 775 776 777 778 779 780 781 782 783 784 785 786 787 788 789 790 791
#ifdef CONFIG_ACPI
static int ni_set_max_freq(struct sdhci_pci_slot *slot)
{
	acpi_status status;
	unsigned long long max_freq;

	status = acpi_evaluate_integer(ACPI_HANDLE(&slot->chip->pdev->dev),
				       "MXFQ", NULL, &max_freq);
	if (ACPI_FAILURE(status)) {
		dev_err(&slot->chip->pdev->dev,
			"MXFQ not found in acpi table\n");
		return -EINVAL;
	}

	slot->host->mmc->f_max = max_freq * 1000000;

	return 0;
}
#else
static inline int ni_set_max_freq(struct sdhci_pci_slot *slot)
{
	return 0;
}
#endif

792 793
static int ni_byt_sdio_probe_slot(struct sdhci_pci_slot *slot)
{
794 795
	int err;

796 797
	byt_read_dsm(slot);

798 799 800 801
	err = ni_set_max_freq(slot);
	if (err)
		return err;

802 803 804 805 806
	slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE |
				 MMC_CAP_WAIT_WHILE_BUSY;
	return 0;
}

807 808
static int byt_sdio_probe_slot(struct sdhci_pci_slot *slot)
{
809
	byt_read_dsm(slot);
810 811
	slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE |
				 MMC_CAP_WAIT_WHILE_BUSY;
812 813 814
	return 0;
}

815 816
static int byt_sd_probe_slot(struct sdhci_pci_slot *slot)
{
817
	byt_read_dsm(slot);
818
	slot->host->mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY |
819
				 MMC_CAP_AGGRESSIVE_PM | MMC_CAP_CD_WAKE;
820 821
	slot->cd_idx = 0;
	slot->cd_override_level = true;
822
	if (slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BXT_SD ||
823
	    slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BXTM_SD ||
824
	    slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_APL_SD ||
825
	    slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_GLK_SD)
826 827
		slot->host->mmc_host_ops.get_cd = bxt_get_cd;

828 829 830
	return 0;
}

831 832 833
static const struct sdhci_pci_fixes sdhci_intel_byt_emmc = {
	.allow_runtime_pm = true,
	.probe_slot	= byt_emmc_probe_slot,
834
	.quirks		= SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
835
	.quirks2	= SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
836
			  SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 |
837
			  SDHCI_QUIRK2_STOP_WITH_TC,
838
	.ops		= &sdhci_intel_byt_ops,
839
	.priv_size	= sizeof(struct intel_host),
840 841
};

842 843 844
static const struct sdhci_pci_fixes sdhci_intel_glk_emmc = {
	.allow_runtime_pm	= true,
	.probe_slot		= glk_emmc_probe_slot,
845 846 847 848 849 850 851 852 853
	.add_host		= glk_emmc_add_host,
#ifdef CONFIG_PM_SLEEP
	.suspend		= sdhci_cqhci_suspend,
	.resume			= sdhci_cqhci_resume,
#endif
#ifdef CONFIG_PM
	.runtime_suspend	= sdhci_cqhci_runtime_suspend,
	.runtime_resume		= sdhci_cqhci_runtime_resume,
#endif
854 855 856 857
	.quirks			= SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
	.quirks2		= SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
				  SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 |
				  SDHCI_QUIRK2_STOP_WITH_TC,
858
	.ops			= &sdhci_intel_glk_ops,
859 860 861
	.priv_size		= sizeof(struct intel_host),
};

862 863 864 865 866 867 868
static const struct sdhci_pci_fixes sdhci_ni_byt_sdio = {
	.quirks		= SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
	.quirks2	= SDHCI_QUIRK2_HOST_OFF_CARD_ON |
			  SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
	.allow_runtime_pm = true,
	.probe_slot	= ni_byt_sdio_probe_slot,
	.ops		= &sdhci_intel_byt_ops,
869
	.priv_size	= sizeof(struct intel_host),
870 871
};

872
static const struct sdhci_pci_fixes sdhci_intel_byt_sdio = {
873
	.quirks		= SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
874 875
	.quirks2	= SDHCI_QUIRK2_HOST_OFF_CARD_ON |
			SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
876 877
	.allow_runtime_pm = true,
	.probe_slot	= byt_sdio_probe_slot,
878
	.ops		= &sdhci_intel_byt_ops,
879
	.priv_size	= sizeof(struct intel_host),
880 881 882
};

static const struct sdhci_pci_fixes sdhci_intel_byt_sd = {
883
	.quirks		= SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
884
	.quirks2	= SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON |
885 886
			  SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
			  SDHCI_QUIRK2_STOP_WITH_TC,
887
	.allow_runtime_pm = true,
888
	.own_cd_for_runtime_pm = true,
889
	.probe_slot	= byt_sd_probe_slot,
890
	.ops		= &sdhci_intel_byt_ops,
891
	.priv_size	= sizeof(struct intel_host),
892 893
};

894
/* Define Host controllers for Intel Merrifield platform */
895 896
#define INTEL_MRFLD_EMMC_0	0
#define INTEL_MRFLD_EMMC_1	1
897
#define INTEL_MRFLD_SD		2
898
#define INTEL_MRFLD_SDIO	3
899

900 901 902 903 904 905 906 907 908 909 910 911 912 913 914 915 916 917
#ifdef CONFIG_ACPI
static void intel_mrfld_mmc_fix_up_power_slot(struct sdhci_pci_slot *slot)
{
	struct acpi_device *device, *child;

	device = ACPI_COMPANION(&slot->chip->pdev->dev);
	if (!device)
		return;

	acpi_device_fix_up_power(device);
	list_for_each_entry(child, &device->children, node)
		if (child->status.present && child->status.enabled)
			acpi_device_fix_up_power(child);
}
#else
static inline void intel_mrfld_mmc_fix_up_power_slot(struct sdhci_pci_slot *slot) {}
#endif

918
static int intel_mrfld_mmc_probe_slot(struct sdhci_pci_slot *slot)
919
{
920 921 922 923 924 925 926 927 928
	unsigned int func = PCI_FUNC(slot->chip->pdev->devfn);

	switch (func) {
	case INTEL_MRFLD_EMMC_0:
	case INTEL_MRFLD_EMMC_1:
		slot->host->mmc->caps |= MMC_CAP_NONREMOVABLE |
					 MMC_CAP_8_BIT_DATA |
					 MMC_CAP_1_8V_DDR;
		break;
929 930 931
	case INTEL_MRFLD_SD:
		slot->host->quirks2 |= SDHCI_QUIRK2_NO_1_8_V;
		break;
932
	case INTEL_MRFLD_SDIO:
933 934
		/* Advertise 2.0v for compatibility with the SDIO card's OCR */
		slot->host->ocr_mask = MMC_VDD_20_21 | MMC_VDD_165_195;
935 936 937
		slot->host->mmc->caps |= MMC_CAP_NONREMOVABLE |
					 MMC_CAP_POWER_OFF_CARD;
		break;
938
	default:
939
		return -ENODEV;
940
	}
941 942

	intel_mrfld_mmc_fix_up_power_slot(slot);
943 944 945
	return 0;
}

946
static const struct sdhci_pci_fixes sdhci_intel_mrfld_mmc = {
947
	.quirks		= SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
948 949
	.quirks2	= SDHCI_QUIRK2_BROKEN_HS200 |
			SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
950
	.allow_runtime_pm = true,
951
	.probe_slot	= intel_mrfld_mmc_probe_slot,
952 953
};

954 955 956 957 958 959 960 961 962 963 964 965 966 967 968 969 970 971
static int jmicron_pmos(struct sdhci_pci_chip *chip, int on)
{
	u8 scratch;
	int ret;

	ret = pci_read_config_byte(chip->pdev, 0xAE, &scratch);
	if (ret)
		return ret;

	/*
	 * Turn PMOS on [bit 0], set over current detection to 2.4 V
	 * [bit 1:2] and enable over current debouncing [bit 6].
	 */
	if (on)
		scratch |= 0x47;
	else
		scratch &= ~0x47;

972
	return pci_write_config_byte(chip->pdev, 0xAE, scratch);
973 974 975 976 977
}

static int jmicron_probe(struct sdhci_pci_chip *chip)
{
	int ret;
978
	u16 mmcdev = 0;
979

980 981 982
	if (chip->pdev->revision == 0) {
		chip->quirks |= SDHCI_QUIRK_32BIT_DMA_ADDR |
			  SDHCI_QUIRK_32BIT_DMA_SIZE |
983
			  SDHCI_QUIRK_32BIT_ADMA_SIZE |
984
			  SDHCI_QUIRK_RESET_AFTER_REQUEST |
985
			  SDHCI_QUIRK_BROKEN_SMALL_PIO;
986 987
	}

988 989 990 991 992 993 994 995 996 997 998 999
	/*
	 * JMicron chips can have two interfaces to the same hardware
	 * in order to work around limitations in Microsoft's driver.
	 * We need to make sure we only bind to one of them.
	 *
	 * This code assumes two things:
	 *
	 * 1. The PCI code adds subfunctions in order.
	 *
	 * 2. The MMC interface has a lower subfunction number
	 *    than the SD interface.
	 */
1000 1001 1002 1003 1004 1005
	if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_SD)
		mmcdev = PCI_DEVICE_ID_JMICRON_JMB38X_MMC;
	else if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_SD)
		mmcdev = PCI_DEVICE_ID_JMICRON_JMB388_ESD;

	if (mmcdev) {
1006 1007 1008 1009
		struct pci_dev *sd_dev;

		sd_dev = NULL;
		while ((sd_dev = pci_get_device(PCI_VENDOR_ID_JMICRON,
1010
						mmcdev, sd_dev)) != NULL) {
1011 1012 1013 1014 1015 1016 1017 1018 1019 1020 1021 1022 1023 1024
			if ((PCI_SLOT(chip->pdev->devfn) ==
				PCI_SLOT(sd_dev->devfn)) &&
				(chip->pdev->bus == sd_dev->bus))
				break;
		}

		if (sd_dev) {
			pci_dev_put(sd_dev);
			dev_info(&chip->pdev->dev, "Refusing to bind to "
				"secondary interface.\n");
			return -ENODEV;
		}
	}

1025 1026 1027 1028 1029 1030 1031 1032 1033 1034
	/*
	 * JMicron chips need a bit of a nudge to enable the power
	 * output pins.
	 */
	ret = jmicron_pmos(chip, 1);
	if (ret) {
		dev_err(&chip->pdev->dev, "Failure enabling card power\n");
		return ret;
	}

1035 1036 1037 1038 1039
	/* quirk for unsable RO-detection on JM388 chips */
	if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_SD ||
	    chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD)
		chip->quirks |= SDHCI_QUIRK_UNSTABLE_RO_DETECT;

1040 1041 1042
	return 0;
}

1043 1044 1045 1046 1047 1048 1049 1050 1051 1052 1053 1054 1055 1056 1057 1058
static void jmicron_enable_mmc(struct sdhci_host *host, int on)
{
	u8 scratch;

	scratch = readb(host->ioaddr + 0xC0);

	if (on)
		scratch |= 0x01;
	else
		scratch &= ~0x01;

	writeb(scratch, host->ioaddr + 0xC0);
}

static int jmicron_probe_slot(struct sdhci_pci_slot *slot)
{
1059 1060 1061 1062 1063 1064 1065 1066 1067 1068 1069 1070 1071 1072 1073 1074
	if (slot->chip->pdev->revision == 0) {
		u16 version;

		version = readl(slot->host->ioaddr + SDHCI_HOST_VERSION);
		version = (version & SDHCI_VENDOR_VER_MASK) >>
			SDHCI_VENDOR_VER_SHIFT;

		/*
		 * Older versions of the chip have lots of nasty glitches
		 * in the ADMA engine. It's best just to avoid it
		 * completely.
		 */
		if (version < 0xAC)
			slot->host->quirks |= SDHCI_QUIRK_BROKEN_ADMA;
	}

1075 1076 1077 1078 1079 1080 1081 1082 1083
	/* JM388 MMC doesn't support 1.8V while SD supports it */
	if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) {
		slot->host->ocr_avail_sd = MMC_VDD_32_33 | MMC_VDD_33_34 |
			MMC_VDD_29_30 | MMC_VDD_30_31 |
			MMC_VDD_165_195; /* allow 1.8V */
		slot->host->ocr_avail_mmc = MMC_VDD_32_33 | MMC_VDD_33_34 |
			MMC_VDD_29_30 | MMC_VDD_30_31; /* no 1.8V for MMC */
	}

1084 1085 1086 1087
	/*
	 * The secondary interface requires a bit set to get the
	 * interrupts.
	 */
1088 1089
	if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC ||
	    slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD)
1090 1091
		jmicron_enable_mmc(slot->host, 1);

1092 1093
	slot->host->mmc->caps |= MMC_CAP_BUS_WIDTH_TEST;

1094 1095 1096
	return 0;
}

P
Pierre Ossman 已提交
1097
static void jmicron_remove_slot(struct sdhci_pci_slot *slot, int dead)
1098
{
P
Pierre Ossman 已提交
1099 1100 1101
	if (dead)
		return;

1102 1103
	if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC ||
	    slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD)
1104 1105 1106
		jmicron_enable_mmc(slot->host, 0);
}

1107
#ifdef CONFIG_PM_SLEEP
1108
static int jmicron_suspend(struct sdhci_pci_chip *chip)
1109
{
1110 1111 1112 1113 1114
	int i, ret;

	ret = __sdhci_pci_suspend_host(chip);
	if (ret)
		return ret;
1115

1116 1117
	if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC ||
	    chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) {
1118
		for (i = 0; i < chip->num_slots; i++)
1119 1120 1121
			jmicron_enable_mmc(chip->slots[i]->host, 0);
	}

1122 1123
	sdhci_pci_init_wakeup(chip);

1124 1125 1126
	return 0;
}

1127 1128
static int jmicron_resume(struct sdhci_pci_chip *chip)
{
1129 1130
	int ret, i;

1131 1132
	if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC ||
	    chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) {
1133
		for (i = 0; i < chip->num_slots; i++)
1134 1135
			jmicron_enable_mmc(chip->slots[i]->host, 1);
	}
1136 1137 1138 1139 1140 1141 1142

	ret = jmicron_pmos(chip, 1);
	if (ret) {
		dev_err(&chip->pdev->dev, "Failure enabling card power\n");
		return ret;
	}

1143
	return sdhci_pci_resume_host(chip);
1144
}
1145
#endif
1146

1147
static const struct sdhci_pci_fixes sdhci_o2 = {
1148 1149
	.probe = sdhci_pci_o2_probe,
	.quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
1150
	.quirks2 = SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD,
1151
	.probe_slot = sdhci_pci_o2_probe_slot,
1152
#ifdef CONFIG_PM_SLEEP
1153
	.resume = sdhci_pci_o2_resume,
1154
#endif
1155 1156
};

1157
static const struct sdhci_pci_fixes sdhci_jmicron = {
1158 1159
	.probe		= jmicron_probe,

1160 1161 1162
	.probe_slot	= jmicron_probe_slot,
	.remove_slot	= jmicron_remove_slot,

1163
#ifdef CONFIG_PM_SLEEP
1164
	.suspend	= jmicron_suspend,
1165
	.resume		= jmicron_resume,
1166
#endif
1167 1168
};

1169 1170 1171 1172 1173 1174 1175 1176 1177 1178 1179 1180 1181 1182 1183 1184 1185 1186 1187 1188 1189 1190 1191 1192 1193 1194 1195 1196 1197 1198 1199 1200 1201 1202 1203 1204 1205 1206 1207 1208 1209 1210 1211 1212 1213 1214 1215 1216 1217 1218 1219 1220 1221 1222 1223 1224 1225 1226 1227 1228 1229 1230 1231 1232 1233 1234 1235
/* SysKonnect CardBus2SDIO extra registers */
#define SYSKT_CTRL		0x200
#define SYSKT_RDFIFO_STAT	0x204
#define SYSKT_WRFIFO_STAT	0x208
#define SYSKT_POWER_DATA	0x20c
#define   SYSKT_POWER_330	0xef
#define   SYSKT_POWER_300	0xf8
#define   SYSKT_POWER_184	0xcc
#define SYSKT_POWER_CMD		0x20d
#define   SYSKT_POWER_START	(1 << 7)
#define SYSKT_POWER_STATUS	0x20e
#define   SYSKT_POWER_STATUS_OK	(1 << 0)
#define SYSKT_BOARD_REV		0x210
#define SYSKT_CHIP_REV		0x211
#define SYSKT_CONF_DATA		0x212
#define   SYSKT_CONF_DATA_1V8	(1 << 2)
#define   SYSKT_CONF_DATA_2V5	(1 << 1)
#define   SYSKT_CONF_DATA_3V3	(1 << 0)

static int syskt_probe(struct sdhci_pci_chip *chip)
{
	if ((chip->pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) {
		chip->pdev->class &= ~0x0000FF;
		chip->pdev->class |= PCI_SDHCI_IFDMA;
	}
	return 0;
}

static int syskt_probe_slot(struct sdhci_pci_slot *slot)
{
	int tm, ps;

	u8 board_rev = readb(slot->host->ioaddr + SYSKT_BOARD_REV);
	u8  chip_rev = readb(slot->host->ioaddr + SYSKT_CHIP_REV);
	dev_info(&slot->chip->pdev->dev, "SysKonnect CardBus2SDIO, "
					 "board rev %d.%d, chip rev %d.%d\n",
					 board_rev >> 4, board_rev & 0xf,
					 chip_rev >> 4,  chip_rev & 0xf);
	if (chip_rev >= 0x20)
		slot->host->quirks |= SDHCI_QUIRK_FORCE_DMA;

	writeb(SYSKT_POWER_330, slot->host->ioaddr + SYSKT_POWER_DATA);
	writeb(SYSKT_POWER_START, slot->host->ioaddr + SYSKT_POWER_CMD);
	udelay(50);
	tm = 10;  /* Wait max 1 ms */
	do {
		ps = readw(slot->host->ioaddr + SYSKT_POWER_STATUS);
		if (ps & SYSKT_POWER_STATUS_OK)
			break;
		udelay(100);
	} while (--tm);
	if (!tm) {
		dev_err(&slot->chip->pdev->dev,
			"power regulator never stabilized");
		writeb(0, slot->host->ioaddr + SYSKT_POWER_CMD);
		return -ENODEV;
	}

	return 0;
}

static const struct sdhci_pci_fixes sdhci_syskt = {
	.quirks		= SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER,
	.probe		= syskt_probe,
	.probe_slot	= syskt_probe_slot,
};

1236 1237 1238 1239 1240 1241 1242 1243 1244 1245 1246 1247
static int via_probe(struct sdhci_pci_chip *chip)
{
	if (chip->pdev->revision == 0x10)
		chip->quirks |= SDHCI_QUIRK_DELAY_AFTER_POWER;

	return 0;
}

static const struct sdhci_pci_fixes sdhci_via = {
	.probe		= via_probe,
};

1248 1249 1250 1251 1252 1253 1254 1255
static int rtsx_probe_slot(struct sdhci_pci_slot *slot)
{
	slot->host->mmc->caps2 |= MMC_CAP2_HS200;
	return 0;
}

static const struct sdhci_pci_fixes sdhci_rtsx = {
	.quirks2	= SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
1256
			SDHCI_QUIRK2_BROKEN_64_BIT_DMA |
1257 1258 1259 1260
			SDHCI_QUIRK2_BROKEN_DDR50,
	.probe_slot	= rtsx_probe_slot,
};

1261 1262 1263 1264 1265 1266 1267 1268
/*AMD chipset generation*/
enum amd_chipset_gen {
	AMD_CHIPSET_BEFORE_ML,
	AMD_CHIPSET_CZ,
	AMD_CHIPSET_NL,
	AMD_CHIPSET_UNKNOWN,
};

1269 1270 1271 1272 1273 1274 1275 1276 1277 1278 1279 1280 1281 1282 1283 1284 1285 1286 1287 1288 1289 1290 1291 1292 1293 1294 1295 1296 1297 1298 1299 1300 1301 1302 1303 1304 1305 1306 1307 1308 1309 1310 1311 1312 1313 1314 1315 1316 1317 1318 1319 1320 1321 1322 1323 1324 1325 1326 1327 1328 1329 1330 1331 1332 1333 1334 1335 1336 1337 1338 1339 1340 1341 1342 1343 1344 1345 1346 1347 1348
/* AMD registers */
#define AMD_SD_AUTO_PATTERN		0xB8
#define AMD_MSLEEP_DURATION		4
#define AMD_SD_MISC_CONTROL		0xD0
#define AMD_MAX_TUNE_VALUE		0x0B
#define AMD_AUTO_TUNE_SEL		0x10800
#define AMD_FIFO_PTR			0x30
#define AMD_BIT_MASK			0x1F

static void amd_tuning_reset(struct sdhci_host *host)
{
	unsigned int val;

	val = sdhci_readw(host, SDHCI_HOST_CONTROL2);
	val |= SDHCI_CTRL_PRESET_VAL_ENABLE | SDHCI_CTRL_EXEC_TUNING;
	sdhci_writew(host, val, SDHCI_HOST_CONTROL2);

	val = sdhci_readw(host, SDHCI_HOST_CONTROL2);
	val &= ~SDHCI_CTRL_EXEC_TUNING;
	sdhci_writew(host, val, SDHCI_HOST_CONTROL2);
}

static void amd_config_tuning_phase(struct pci_dev *pdev, u8 phase)
{
	unsigned int val;

	pci_read_config_dword(pdev, AMD_SD_AUTO_PATTERN, &val);
	val &= ~AMD_BIT_MASK;
	val |= (AMD_AUTO_TUNE_SEL | (phase << 1));
	pci_write_config_dword(pdev, AMD_SD_AUTO_PATTERN, val);
}

static void amd_enable_manual_tuning(struct pci_dev *pdev)
{
	unsigned int val;

	pci_read_config_dword(pdev, AMD_SD_MISC_CONTROL, &val);
	val |= AMD_FIFO_PTR;
	pci_write_config_dword(pdev, AMD_SD_MISC_CONTROL, val);
}

static int amd_execute_tuning(struct sdhci_host *host, u32 opcode)
{
	struct sdhci_pci_slot *slot = sdhci_priv(host);
	struct pci_dev *pdev = slot->chip->pdev;
	u8 valid_win = 0;
	u8 valid_win_max = 0;
	u8 valid_win_end = 0;
	u8 ctrl, tune_around;

	amd_tuning_reset(host);

	for (tune_around = 0; tune_around < 12; tune_around++) {
		amd_config_tuning_phase(pdev, tune_around);

		if (mmc_send_tuning(host->mmc, opcode, NULL)) {
			valid_win = 0;
			msleep(AMD_MSLEEP_DURATION);
			ctrl = SDHCI_RESET_CMD | SDHCI_RESET_DATA;
			sdhci_writeb(host, ctrl, SDHCI_SOFTWARE_RESET);
		} else if (++valid_win > valid_win_max) {
			valid_win_max = valid_win;
			valid_win_end = tune_around;
		}
	}

	if (!valid_win_max) {
		dev_err(&pdev->dev, "no tuning point found\n");
		return -EIO;
	}

	amd_config_tuning_phase(pdev, valid_win_end - valid_win_max / 2);

	amd_enable_manual_tuning(pdev);

	host->mmc->retune_period = 0;

	return 0;
}

1349 1350 1351
static int amd_probe(struct sdhci_pci_chip *chip)
{
	struct pci_dev	*smbus_dev;
1352
	enum amd_chipset_gen gen;
1353 1354 1355

	smbus_dev = pci_get_device(PCI_VENDOR_ID_AMD,
			PCI_DEVICE_ID_AMD_HUDSON2_SMBUS, NULL);
1356 1357 1358 1359 1360 1361 1362 1363 1364 1365 1366 1367 1368 1369
	if (smbus_dev) {
		gen = AMD_CHIPSET_BEFORE_ML;
	} else {
		smbus_dev = pci_get_device(PCI_VENDOR_ID_AMD,
				PCI_DEVICE_ID_AMD_KERNCZ_SMBUS, NULL);
		if (smbus_dev) {
			if (smbus_dev->revision < 0x51)
				gen = AMD_CHIPSET_CZ;
			else
				gen = AMD_CHIPSET_NL;
		} else {
			gen = AMD_CHIPSET_UNKNOWN;
		}
	}
1370

1371
	if (gen == AMD_CHIPSET_BEFORE_ML || gen == AMD_CHIPSET_CZ)
1372 1373 1374 1375 1376
		chip->quirks2 |= SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD;

	return 0;
}

1377 1378 1379
static const struct sdhci_ops amd_sdhci_pci_ops = {
	.set_clock			= sdhci_set_clock,
	.enable_dma			= sdhci_pci_enable_dma,
1380
	.set_bus_width			= sdhci_set_bus_width,
1381 1382 1383 1384 1385
	.reset				= sdhci_reset,
	.set_uhs_signaling		= sdhci_set_uhs_signaling,
	.platform_execute_tuning	= amd_execute_tuning,
};

1386 1387
static const struct sdhci_pci_fixes sdhci_amd = {
	.probe		= amd_probe,
1388
	.ops		= &amd_sdhci_pci_ops,
1389 1390
};

1391
static const struct pci_device_id pci_ids[] = {
1392 1393 1394 1395 1396 1397 1398 1399 1400 1401 1402 1403 1404 1405 1406 1407 1408 1409 1410 1411 1412 1413 1414 1415 1416 1417 1418 1419 1420 1421 1422 1423 1424 1425 1426 1427 1428 1429 1430 1431 1432 1433 1434 1435 1436
	SDHCI_PCI_DEVICE(RICOH, R5C822,  ricoh),
	SDHCI_PCI_DEVICE(RICOH, R5C843,  ricoh_mmc),
	SDHCI_PCI_DEVICE(RICOH, R5CE822, ricoh_mmc),
	SDHCI_PCI_DEVICE(RICOH, R5CE823, ricoh_mmc),
	SDHCI_PCI_DEVICE(ENE, CB712_SD,   ene_712),
	SDHCI_PCI_DEVICE(ENE, CB712_SD_2, ene_712),
	SDHCI_PCI_DEVICE(ENE, CB714_SD,   ene_714),
	SDHCI_PCI_DEVICE(ENE, CB714_SD_2, ene_714),
	SDHCI_PCI_DEVICE(MARVELL, 88ALP01_SD, cafe),
	SDHCI_PCI_DEVICE(JMICRON, JMB38X_SD,  jmicron),
	SDHCI_PCI_DEVICE(JMICRON, JMB38X_MMC, jmicron),
	SDHCI_PCI_DEVICE(JMICRON, JMB388_SD,  jmicron),
	SDHCI_PCI_DEVICE(JMICRON, JMB388_ESD, jmicron),
	SDHCI_PCI_DEVICE(SYSKONNECT, 8000, syskt),
	SDHCI_PCI_DEVICE(VIA, 95D0, via),
	SDHCI_PCI_DEVICE(REALTEK, 5250, rtsx),
	SDHCI_PCI_DEVICE(INTEL, QRK_SD,    intel_qrk),
	SDHCI_PCI_DEVICE(INTEL, MRST_SD0,  intel_mrst_hc0),
	SDHCI_PCI_DEVICE(INTEL, MRST_SD1,  intel_mrst_hc1_hc2),
	SDHCI_PCI_DEVICE(INTEL, MRST_SD2,  intel_mrst_hc1_hc2),
	SDHCI_PCI_DEVICE(INTEL, MFD_SD,    intel_mfd_sd),
	SDHCI_PCI_DEVICE(INTEL, MFD_SDIO1, intel_mfd_sdio),
	SDHCI_PCI_DEVICE(INTEL, MFD_SDIO2, intel_mfd_sdio),
	SDHCI_PCI_DEVICE(INTEL, MFD_EMMC0, intel_mfd_emmc),
	SDHCI_PCI_DEVICE(INTEL, MFD_EMMC1, intel_mfd_emmc),
	SDHCI_PCI_DEVICE(INTEL, PCH_SDIO0, intel_pch_sdio),
	SDHCI_PCI_DEVICE(INTEL, PCH_SDIO1, intel_pch_sdio),
	SDHCI_PCI_DEVICE(INTEL, BYT_EMMC,  intel_byt_emmc),
	SDHCI_PCI_SUBDEVICE(INTEL, BYT_SDIO, NI, 7884, ni_byt_sdio),
	SDHCI_PCI_DEVICE(INTEL, BYT_SDIO,  intel_byt_sdio),
	SDHCI_PCI_DEVICE(INTEL, BYT_SD,    intel_byt_sd),
	SDHCI_PCI_DEVICE(INTEL, BYT_EMMC2, intel_byt_emmc),
	SDHCI_PCI_DEVICE(INTEL, BSW_EMMC,  intel_byt_emmc),
	SDHCI_PCI_DEVICE(INTEL, BSW_SDIO,  intel_byt_sdio),
	SDHCI_PCI_DEVICE(INTEL, BSW_SD,    intel_byt_sd),
	SDHCI_PCI_DEVICE(INTEL, CLV_SDIO0, intel_mfd_sd),
	SDHCI_PCI_DEVICE(INTEL, CLV_SDIO1, intel_mfd_sdio),
	SDHCI_PCI_DEVICE(INTEL, CLV_SDIO2, intel_mfd_sdio),
	SDHCI_PCI_DEVICE(INTEL, CLV_EMMC0, intel_mfd_emmc),
	SDHCI_PCI_DEVICE(INTEL, CLV_EMMC1, intel_mfd_emmc),
	SDHCI_PCI_DEVICE(INTEL, MRFLD_MMC, intel_mrfld_mmc),
	SDHCI_PCI_DEVICE(INTEL, SPT_EMMC,  intel_byt_emmc),
	SDHCI_PCI_DEVICE(INTEL, SPT_SDIO,  intel_byt_sdio),
	SDHCI_PCI_DEVICE(INTEL, SPT_SD,    intel_byt_sd),
	SDHCI_PCI_DEVICE(INTEL, DNV_EMMC,  intel_byt_emmc),
1437
	SDHCI_PCI_DEVICE(INTEL, CDF_EMMC,  intel_glk_emmc),
1438 1439 1440 1441 1442 1443 1444 1445 1446
	SDHCI_PCI_DEVICE(INTEL, BXT_EMMC,  intel_byt_emmc),
	SDHCI_PCI_DEVICE(INTEL, BXT_SDIO,  intel_byt_sdio),
	SDHCI_PCI_DEVICE(INTEL, BXT_SD,    intel_byt_sd),
	SDHCI_PCI_DEVICE(INTEL, BXTM_EMMC, intel_byt_emmc),
	SDHCI_PCI_DEVICE(INTEL, BXTM_SDIO, intel_byt_sdio),
	SDHCI_PCI_DEVICE(INTEL, BXTM_SD,   intel_byt_sd),
	SDHCI_PCI_DEVICE(INTEL, APL_EMMC,  intel_byt_emmc),
	SDHCI_PCI_DEVICE(INTEL, APL_SDIO,  intel_byt_sdio),
	SDHCI_PCI_DEVICE(INTEL, APL_SD,    intel_byt_sd),
1447
	SDHCI_PCI_DEVICE(INTEL, GLK_EMMC,  intel_glk_emmc),
1448 1449
	SDHCI_PCI_DEVICE(INTEL, GLK_SDIO,  intel_byt_sdio),
	SDHCI_PCI_DEVICE(INTEL, GLK_SD,    intel_byt_sd),
1450 1451 1452
	SDHCI_PCI_DEVICE(INTEL, CNP_EMMC,  intel_glk_emmc),
	SDHCI_PCI_DEVICE(INTEL, CNP_SD,    intel_byt_sd),
	SDHCI_PCI_DEVICE(INTEL, CNPH_SD,   intel_byt_sd),
1453 1454 1455 1456 1457 1458 1459 1460 1461 1462
	SDHCI_PCI_DEVICE(O2, 8120,     o2),
	SDHCI_PCI_DEVICE(O2, 8220,     o2),
	SDHCI_PCI_DEVICE(O2, 8221,     o2),
	SDHCI_PCI_DEVICE(O2, 8320,     o2),
	SDHCI_PCI_DEVICE(O2, 8321,     o2),
	SDHCI_PCI_DEVICE(O2, FUJIN2,   o2),
	SDHCI_PCI_DEVICE(O2, SDS0,     o2),
	SDHCI_PCI_DEVICE(O2, SDS1,     o2),
	SDHCI_PCI_DEVICE(O2, SEABIRD0, o2),
	SDHCI_PCI_DEVICE(O2, SEABIRD1, o2),
1463
	SDHCI_PCI_DEVICE(ARASAN, PHY_EMMC, arasan),
1464 1465 1466
	SDHCI_PCI_DEVICE_CLASS(AMD, SYSTEM_SDHCI, PCI_CLASS_MASK, amd),
	/* Generic SD host controller */
	{PCI_DEVICE_CLASS(SYSTEM_SDHCI, PCI_CLASS_MASK)},
1467 1468 1469 1470 1471 1472 1473 1474 1475 1476 1477
	{ /* end: all zeroes */ },
};

MODULE_DEVICE_TABLE(pci, pci_ids);

/*****************************************************************************\
 *                                                                           *
 * SDHCI core callbacks                                                      *
 *                                                                           *
\*****************************************************************************/

1478
int sdhci_pci_enable_dma(struct sdhci_host *host)
1479 1480 1481 1482 1483 1484 1485 1486 1487
{
	struct sdhci_pci_slot *slot;
	struct pci_dev *pdev;

	slot = sdhci_priv(host);
	pdev = slot->chip->pdev;

	if (((pdev->class & 0xFFFF00) == (PCI_CLASS_SYSTEM_SDHCI << 8)) &&
		((pdev->class & 0x0000FF) != PCI_SDHCI_IFDMA) &&
1488
		(host->flags & SDHCI_USE_SDMA)) {
1489 1490 1491 1492 1493 1494 1495 1496 1497
		dev_warn(&pdev->dev, "Will use DMA mode even though HW "
			"doesn't fully claim to support it.\n");
	}

	pci_set_master(pdev);

	return 0;
}

1498
static void sdhci_pci_gpio_hw_reset(struct sdhci_host *host)
1499 1500 1501 1502 1503 1504 1505 1506 1507 1508 1509 1510 1511 1512
{
	struct sdhci_pci_slot *slot = sdhci_priv(host);
	int rst_n_gpio = slot->rst_n_gpio;

	if (!gpio_is_valid(rst_n_gpio))
		return;
	gpio_set_value_cansleep(rst_n_gpio, 0);
	/* For eMMC, minimum is 1us but give it 10us for good measure */
	udelay(10);
	gpio_set_value_cansleep(rst_n_gpio, 1);
	/* For eMMC, minimum is 200us but give it 300us for good measure */
	usleep_range(300, 1000);
}

1513 1514 1515 1516 1517 1518 1519 1520
static void sdhci_pci_hw_reset(struct sdhci_host *host)
{
	struct sdhci_pci_slot *slot = sdhci_priv(host);

	if (slot->hw_reset)
		slot->hw_reset(host);
}

1521
static const struct sdhci_ops sdhci_pci_ops = {
1522
	.set_clock	= sdhci_set_clock,
1523
	.enable_dma	= sdhci_pci_enable_dma,
1524
	.set_bus_width	= sdhci_set_bus_width,
1525
	.reset		= sdhci_reset,
1526
	.set_uhs_signaling = sdhci_set_uhs_signaling,
1527
	.hw_reset		= sdhci_pci_hw_reset,
1528 1529 1530 1531 1532 1533 1534 1535
};

/*****************************************************************************\
 *                                                                           *
 * Suspend/resume                                                            *
 *                                                                           *
\*****************************************************************************/

1536
#ifdef CONFIG_PM_SLEEP
1537
static int sdhci_pci_suspend(struct device *dev)
1538
{
1539
	struct pci_dev *pdev = to_pci_dev(dev);
1540
	struct sdhci_pci_chip *chip = pci_get_drvdata(pdev);
1541 1542 1543 1544

	if (!chip)
		return 0;

1545 1546
	if (chip->fixes && chip->fixes->suspend)
		return chip->fixes->suspend(chip);
1547

1548
	return sdhci_pci_suspend_host(chip);
1549 1550
}

1551
static int sdhci_pci_resume(struct device *dev)
1552
{
1553
	struct pci_dev *pdev = to_pci_dev(dev);
1554
	struct sdhci_pci_chip *chip = pci_get_drvdata(pdev);
1555 1556 1557 1558

	if (!chip)
		return 0;

1559 1560
	if (chip->fixes && chip->fixes->resume)
		return chip->fixes->resume(chip);
1561

1562
	return sdhci_pci_resume_host(chip);
1563
}
1564
#endif
1565

1566
#ifdef CONFIG_PM
1567 1568
static int sdhci_pci_runtime_suspend(struct device *dev)
{
1569
	struct pci_dev *pdev = to_pci_dev(dev);
1570
	struct sdhci_pci_chip *chip = pci_get_drvdata(pdev);
1571 1572 1573 1574

	if (!chip)
		return 0;

1575 1576
	if (chip->fixes && chip->fixes->runtime_suspend)
		return chip->fixes->runtime_suspend(chip);
1577

1578
	return sdhci_pci_runtime_suspend_host(chip);
1579 1580 1581 1582
}

static int sdhci_pci_runtime_resume(struct device *dev)
{
1583
	struct pci_dev *pdev = to_pci_dev(dev);
1584
	struct sdhci_pci_chip *chip = pci_get_drvdata(pdev);
1585 1586 1587 1588

	if (!chip)
		return 0;

1589 1590
	if (chip->fixes && chip->fixes->runtime_resume)
		return chip->fixes->runtime_resume(chip);
1591

1592
	return sdhci_pci_runtime_resume_host(chip);
1593
}
1594
#endif
1595 1596

static const struct dev_pm_ops sdhci_pci_pm_ops = {
1597
	SET_SYSTEM_SLEEP_PM_OPS(sdhci_pci_suspend, sdhci_pci_resume)
1598
	SET_RUNTIME_PM_OPS(sdhci_pci_runtime_suspend,
1599
			sdhci_pci_runtime_resume, NULL)
1600 1601
};

1602 1603 1604 1605 1606 1607
/*****************************************************************************\
 *                                                                           *
 * Device probing/removal                                                    *
 *                                                                           *
\*****************************************************************************/

1608
static struct sdhci_pci_slot *sdhci_pci_probe_slot(
1609 1610
	struct pci_dev *pdev, struct sdhci_pci_chip *chip, int first_bar,
	int slotno)
1611 1612 1613
{
	struct sdhci_pci_slot *slot;
	struct sdhci_host *host;
1614
	int ret, bar = first_bar + slotno;
1615
	size_t priv_size = chip->fixes ? chip->fixes->priv_size : 0;
1616 1617 1618 1619 1620 1621

	if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) {
		dev_err(&pdev->dev, "BAR %d is not iomem. Aborting.\n", bar);
		return ERR_PTR(-ENODEV);
	}

1622
	if (pci_resource_len(pdev, bar) < 0x100) {
1623 1624 1625 1626 1627 1628 1629 1630 1631 1632 1633 1634 1635 1636
		dev_err(&pdev->dev, "Invalid iomem size. You may "
			"experience problems.\n");
	}

	if ((pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) {
		dev_err(&pdev->dev, "Vendor specific interface. Aborting.\n");
		return ERR_PTR(-ENODEV);
	}

	if ((pdev->class & 0x0000FF) > PCI_SDHCI_IFVENDOR) {
		dev_err(&pdev->dev, "Unknown interface. Aborting.\n");
		return ERR_PTR(-ENODEV);
	}

1637
	host = sdhci_alloc_host(&pdev->dev, sizeof(*slot) + priv_size);
1638
	if (IS_ERR(host)) {
1639
		dev_err(&pdev->dev, "cannot allocate host\n");
1640
		return ERR_CAST(host);
1641 1642 1643 1644 1645 1646
	}

	slot = sdhci_priv(host);

	slot->chip = chip;
	slot->host = host;
1647
	slot->rst_n_gpio = -EINVAL;
1648
	slot->cd_gpio = -EINVAL;
1649
	slot->cd_idx = -1;
1650

1651 1652 1653 1654 1655 1656 1657 1658 1659 1660 1661 1662
	/* Retrieve platform data if there is any */
	if (*sdhci_pci_get_data)
		slot->data = sdhci_pci_get_data(pdev, slotno);

	if (slot->data) {
		if (slot->data->setup) {
			ret = slot->data->setup(slot->data);
			if (ret) {
				dev_err(&pdev->dev, "platform setup failed\n");
				goto free;
			}
		}
1663 1664
		slot->rst_n_gpio = slot->data->rst_n_gpio;
		slot->cd_gpio = slot->data->cd_gpio;
1665 1666
	}

1667
	host->hw_name = "PCI";
1668 1669 1670
	host->ops = chip->fixes && chip->fixes->ops ?
		    chip->fixes->ops :
		    &sdhci_pci_ops;
1671
	host->quirks = chip->quirks;
1672
	host->quirks2 = chip->quirks2;
1673 1674 1675

	host->irq = pdev->irq;

1676
	ret = pcim_iomap_regions(pdev, BIT(bar), mmc_hostname(host->mmc));
1677 1678
	if (ret) {
		dev_err(&pdev->dev, "cannot request region\n");
1679
		goto cleanup;
1680 1681
	}

1682
	host->ioaddr = pcim_iomap_table(pdev)[bar];
1683

1684 1685 1686
	if (chip->fixes && chip->fixes->probe_slot) {
		ret = chip->fixes->probe_slot(slot);
		if (ret)
1687
			goto cleanup;
1688 1689
	}

1690
	if (gpio_is_valid(slot->rst_n_gpio)) {
1691
		if (!devm_gpio_request(&pdev->dev, slot->rst_n_gpio, "eMMC_reset")) {
1692 1693
			gpio_direction_output(slot->rst_n_gpio, 1);
			slot->host->mmc->caps |= MMC_CAP_HW_RESET;
1694
			slot->hw_reset = sdhci_pci_gpio_hw_reset;
1695 1696 1697 1698 1699 1700
		} else {
			dev_warn(&pdev->dev, "failed to request rst_n_gpio\n");
			slot->rst_n_gpio = -EINVAL;
		}
	}

1701
	host->mmc->pm_caps = MMC_PM_KEEP_POWER | MMC_PM_WAKE_SDIO_IRQ;
1702
	host->mmc->slotno = slotno;
1703
	host->mmc->caps2 |= MMC_CAP2_NO_PRESCAN_POWERUP;
1704

1705
	if (slot->cd_idx >= 0) {
1706
		ret = mmc_gpiod_request_cd(host->mmc, NULL, slot->cd_idx,
1707 1708 1709 1710 1711 1712 1713 1714
					   slot->cd_override_level, 0, NULL);
		if (ret == -EPROBE_DEFER)
			goto remove;

		if (ret) {
			dev_warn(&pdev->dev, "failed to setup card detect gpio\n");
			slot->cd_idx = -1;
		}
1715 1716
	}

1717 1718 1719 1720
	if (chip->fixes && chip->fixes->add_host)
		ret = chip->fixes->add_host(slot);
	else
		ret = sdhci_add_host(host);
1721
	if (ret)
1722
		goto remove;
1723

1724 1725
	sdhci_pci_add_own_cd(slot);

1726 1727 1728 1729 1730
	/*
	 * Check if the chip needs a separate GPIO for card detect to wake up
	 * from runtime suspend.  If it is not there, don't allow runtime PM.
	 * Note sdhci_pci_add_own_cd() sets slot->cd_gpio to -EINVAL on failure.
	 */
1731
	if (chip->fixes && chip->fixes->own_cd_for_runtime_pm &&
1732
	    !gpio_is_valid(slot->cd_gpio) && slot->cd_idx < 0)
1733 1734
		chip->allow_runtime_pm = false;

1735 1736
	return slot;

1737 1738
remove:
	if (chip->fixes && chip->fixes->remove_slot)
P
Pierre Ossman 已提交
1739
		chip->fixes->remove_slot(slot, 0);
1740

1741 1742 1743 1744
cleanup:
	if (slot->data && slot->data->cleanup)
		slot->data->cleanup(slot->data);

1745
free:
1746 1747 1748 1749 1750 1751 1752
	sdhci_free_host(host);

	return ERR_PTR(ret);
}

static void sdhci_pci_remove_slot(struct sdhci_pci_slot *slot)
{
P
Pierre Ossman 已提交
1753 1754 1755
	int dead;
	u32 scratch;

1756 1757
	sdhci_pci_remove_own_cd(slot);

P
Pierre Ossman 已提交
1758 1759 1760 1761 1762 1763
	dead = 0;
	scratch = readl(slot->host->ioaddr + SDHCI_INT_STATUS);
	if (scratch == (u32)-1)
		dead = 1;

	sdhci_remove_host(slot->host, dead);
1764 1765

	if (slot->chip->fixes && slot->chip->fixes->remove_slot)
P
Pierre Ossman 已提交
1766
		slot->chip->fixes->remove_slot(slot, dead);
1767

1768 1769 1770
	if (slot->data && slot->data->cleanup)
		slot->data->cleanup(slot->data);

1771 1772 1773
	sdhci_free_host(slot->host);
}

1774
static void sdhci_pci_runtime_pm_allow(struct device *dev)
1775
{
1776
	pm_suspend_ignore_children(dev, 1);
1777 1778
	pm_runtime_set_autosuspend_delay(dev, 50);
	pm_runtime_use_autosuspend(dev);
1779 1780 1781
	pm_runtime_allow(dev);
	/* Stay active until mmc core scans for a card */
	pm_runtime_put_noidle(dev);
1782 1783
}

1784
static void sdhci_pci_runtime_pm_forbid(struct device *dev)
1785 1786 1787 1788 1789
{
	pm_runtime_forbid(dev);
	pm_runtime_get_noresume(dev);
}

1790
static int sdhci_pci_probe(struct pci_dev *pdev,
1791 1792 1793 1794 1795
				     const struct pci_device_id *ent)
{
	struct sdhci_pci_chip *chip;
	struct sdhci_pci_slot *slot;

1796
	u8 slots, first_bar;
1797 1798 1799 1800 1801 1802
	int ret, i;

	BUG_ON(pdev == NULL);
	BUG_ON(ent == NULL);

	dev_info(&pdev->dev, "SDHCI controller found [%04x:%04x] (rev %x)\n",
1803
		 (int)pdev->vendor, (int)pdev->device, (int)pdev->revision);
1804 1805 1806 1807 1808 1809 1810 1811 1812 1813 1814 1815 1816 1817 1818 1819 1820 1821 1822 1823 1824 1825 1826

	ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &slots);
	if (ret)
		return ret;

	slots = PCI_SLOT_INFO_SLOTS(slots) + 1;
	dev_dbg(&pdev->dev, "found %d slot(s)\n", slots);
	if (slots == 0)
		return -ENODEV;

	BUG_ON(slots > MAX_SLOTS);

	ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &first_bar);
	if (ret)
		return ret;

	first_bar &= PCI_SLOT_INFO_FIRST_BAR_MASK;

	if (first_bar > 5) {
		dev_err(&pdev->dev, "Invalid first BAR. Aborting.\n");
		return -ENODEV;
	}

1827
	ret = pcim_enable_device(pdev);
1828 1829 1830
	if (ret)
		return ret;

1831 1832 1833
	chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL);
	if (!chip)
		return -ENOMEM;
1834 1835

	chip->pdev = pdev;
1836
	chip->fixes = (const struct sdhci_pci_fixes *)ent->driver_data;
1837
	if (chip->fixes) {
1838
		chip->quirks = chip->fixes->quirks;
1839
		chip->quirks2 = chip->fixes->quirks2;
1840 1841
		chip->allow_runtime_pm = chip->fixes->allow_runtime_pm;
	}
1842
	chip->num_slots = slots;
1843 1844
	chip->pm_retune = true;
	chip->rpm_retune = true;
1845 1846 1847

	pci_set_drvdata(pdev, chip);

1848 1849 1850
	if (chip->fixes && chip->fixes->probe) {
		ret = chip->fixes->probe(chip);
		if (ret)
1851
			return ret;
1852 1853
	}

1854 1855
	slots = chip->num_slots;	/* Quirk may have changed this */

1856
	for (i = 0; i < slots; i++) {
1857
		slot = sdhci_pci_probe_slot(pdev, chip, first_bar, i);
1858
		if (IS_ERR(slot)) {
1859
			for (i--; i >= 0; i--)
1860
				sdhci_pci_remove_slot(chip->slots[i]);
1861
			return PTR_ERR(slot);
1862 1863 1864 1865 1866
		}

		chip->slots[i] = slot;
	}

1867 1868
	if (chip->allow_runtime_pm)
		sdhci_pci_runtime_pm_allow(&pdev->dev);
1869

1870 1871 1872
	return 0;
}

1873
static void sdhci_pci_remove(struct pci_dev *pdev)
1874 1875
{
	int i;
1876
	struct sdhci_pci_chip *chip = pci_get_drvdata(pdev);
1877

1878 1879
	if (chip->allow_runtime_pm)
		sdhci_pci_runtime_pm_forbid(&pdev->dev);
1880

1881 1882
	for (i = 0; i < chip->num_slots; i++)
		sdhci_pci_remove_slot(chip->slots[i]);
1883 1884 1885
}

static struct pci_driver sdhci_driver = {
1886
	.name =		"sdhci-pci",
1887
	.id_table =	pci_ids,
1888
	.probe =	sdhci_pci_probe,
1889
	.remove =	sdhci_pci_remove,
1890 1891 1892
	.driver =	{
		.pm =   &sdhci_pci_pm_ops
	},
1893 1894
};

1895
module_pci_driver(sdhci_driver);
1896

1897
MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>");
1898 1899
MODULE_DESCRIPTION("Secure Digital Host Controller Interface PCI driver");
MODULE_LICENSE("GPL");
新手
引导
客服 返回
顶部