tegra20-colibri.dtsi 14.5 KB
Newer Older
1
// SPDX-License-Identifier: GPL-2.0
2
#include "tegra20.dtsi"
3 4

/ {
5
	model = "Toradex Colibri T20 256/512 MB";
6 7
	compatible = "toradex,colibri_t20-512", "nvidia,tegra20";

8
	memory@0 {
9 10 11 12 13 14
		/*
		 * Set memory to 256 MB to be safe as this could be used on
		 * 256 or 512 MB module. It is expected from bootloader
		 * to fix this up for 512 MB version.
		 */
		reg = <0x00000000 0x10000000>;
15 16
	};

17 18
	host1x@50000000 {
		hdmi@54280000 {
19 20 21 22
			vdd-supply = <&hdmi_vdd_reg>;
			pll-supply = <&hdmi_pll_reg>;

			nvidia,ddc-i2c-bus = <&i2c_ddc>;
23 24
			nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7)
				GPIO_ACTIVE_HIGH>;
25 26 27
		};
	};

28
	pinmux@70000014 {
29 30 31 32 33 34 35
		pinctrl-names = "default";
		pinctrl-0 = <&state_default>;

		state_default: pinmux {
			audio_refclk {
				nvidia,pins = "cdev1";
				nvidia,function = "plla_out";
36 37
				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
				nvidia,tristate = <TEGRA_PIN_DISABLE>;
38 39 40 41
			};
			crt {
				nvidia,pins = "crtp";
				nvidia,function = "crt";
42 43
				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
				nvidia,tristate = <TEGRA_PIN_ENABLE>;
44 45 46 47
			};
			dap3 {
				nvidia,pins = "dap3";
				nvidia,function = "dap3";
48 49
				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
				nvidia,tristate = <TEGRA_PIN_DISABLE>;
50 51 52 53 54 55 56 57 58
			};
			displaya {
				nvidia,pins = "ld0", "ld1", "ld2", "ld3",
					"ld4", "ld5", "ld6", "ld7", "ld8",
					"ld9", "ld10", "ld11", "ld12", "ld13",
					"ld14", "ld15", "ld16", "ld17",
					"lhs", "lpw0", "lpw2", "lsc0",
					"lsc1", "lsck", "lsda", "lspi", "lvs";
				nvidia,function = "displaya";
59
				nvidia,tristate = <TEGRA_PIN_ENABLE>;
60 61 62 63
			};
			gpio_dte {
				nvidia,pins = "dte";
				nvidia,function = "rsvd1";
64 65
				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
				nvidia,tristate = <TEGRA_PIN_DISABLE>;
66 67 68 69 70 71
			};
			gpio_gmi {
				nvidia,pins = "ata", "atc", "atd", "ate",
					"dap1", "dap2", "dap4", "gpu", "irrx",
					"irtx", "spia", "spib", "spic";
				nvidia,function = "gmi";
72 73
				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
				nvidia,tristate = <TEGRA_PIN_DISABLE>;
74 75 76 77
			};
			gpio_pta {
				nvidia,pins = "pta";
				nvidia,function = "rsvd4";
78 79
				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
				nvidia,tristate = <TEGRA_PIN_DISABLE>;
80 81 82 83
			};
			gpio_uac {
				nvidia,pins = "uac";
				nvidia,function = "rsvd2";
84 85
				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
				nvidia,tristate = <TEGRA_PIN_DISABLE>;
86 87 88 89
			};
			hdint {
				nvidia,pins = "hdint";
				nvidia,function = "hdmi";
90
				nvidia,tristate = <TEGRA_PIN_ENABLE>;
91 92 93 94
			};
			i2c1 {
				nvidia,pins = "rm";
				nvidia,function = "i2c1";
95 96
				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
				nvidia,tristate = <TEGRA_PIN_ENABLE>;
97 98 99 100
			};
			i2c3 {
				nvidia,pins = "dtf";
				nvidia,function = "i2c3";
101 102
				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
				nvidia,tristate = <TEGRA_PIN_ENABLE>;
103 104 105 106
			};
			i2cddc {
				nvidia,pins = "ddc";
				nvidia,function = "i2c2";
107 108
				nvidia,pull = <TEGRA_PIN_PULL_UP>;
				nvidia,tristate = <TEGRA_PIN_ENABLE>;
109 110 111 112
			};
			i2cp {
				nvidia,pins = "i2cp";
				nvidia,function = "i2cp";
113 114
				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
				nvidia,tristate = <TEGRA_PIN_DISABLE>;
115 116 117 118
			};
			irda {
				nvidia,pins = "uad";
				nvidia,function = "irda";
119 120
				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
				nvidia,tristate = <TEGRA_PIN_ENABLE>;
121 122 123 124 125
			};
			nand {
				nvidia,pins = "kbca", "kbcc", "kbcd",
					"kbce", "kbcf";
				nvidia,function = "nand";
126 127
				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
				nvidia,tristate = <TEGRA_PIN_DISABLE>;
128 129 130 131
			};
			owc {
				nvidia,pins = "owc";
				nvidia,function = "owr";
132 133
				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
				nvidia,tristate = <TEGRA_PIN_ENABLE>;
134 135 136 137
			};
			pmc {
				nvidia,pins = "pmc";
				nvidia,function = "pwr_on";
138
				nvidia,tristate = <TEGRA_PIN_DISABLE>;
139 140 141 142
			};
			pwm {
				nvidia,pins = "sdb", "sdc", "sdd";
				nvidia,function = "pwm";
143
				nvidia,tristate = <TEGRA_PIN_ENABLE>;
144 145 146 147
			};
			sdio4 {
				nvidia,pins = "atb", "gma", "gme";
				nvidia,function = "sdio4";
148 149
				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
				nvidia,tristate = <TEGRA_PIN_ENABLE>;
150 151 152 153
			};
			spi1 {
				nvidia,pins = "spid", "spie", "spif";
				nvidia,function = "spi1";
154 155
				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
				nvidia,tristate = <TEGRA_PIN_ENABLE>;
156 157 158 159
			};
			spi4 {
				nvidia,pins = "slxa", "slxc", "slxd", "slxk";
				nvidia,function = "spi4";
160 161
				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
				nvidia,tristate = <TEGRA_PIN_ENABLE>;
162 163 164 165
			};
			uarta {
				nvidia,pins = "sdio1";
				nvidia,function = "uarta";
166 167
				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
				nvidia,tristate = <TEGRA_PIN_ENABLE>;
168 169 170 171
			};
			uartd {
				nvidia,pins = "gmc";
				nvidia,function = "uartd";
172 173
				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
				nvidia,tristate = <TEGRA_PIN_ENABLE>;
174 175 176 177
			};
			ulpi {
				nvidia,pins = "uaa", "uab", "uda";
				nvidia,function = "ulpi";
178 179
				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
				nvidia,tristate = <TEGRA_PIN_DISABLE>;
180 181 182 183
			};
			ulpi_refclk {
				nvidia,pins = "cdev2";
				nvidia,function = "pllp_out4";
184 185
				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
				nvidia,tristate = <TEGRA_PIN_DISABLE>;
186 187 188 189
			};
			usb_gpio {
				nvidia,pins = "spig", "spih";
				nvidia,function = "spi2_alt";
190 191
				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
				nvidia,tristate = <TEGRA_PIN_DISABLE>;
192 193 194 195
			};
			vi {
				nvidia,pins = "dta", "dtb", "dtc", "dtd";
				nvidia,function = "vi";
196 197
				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
				nvidia,tristate = <TEGRA_PIN_ENABLE>;
198 199 200 201
			};
			vi_sc {
				nvidia,pins = "csus";
				nvidia,function = "vi_sensor_clk";
202 203
				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
				nvidia,tristate = <TEGRA_PIN_ENABLE>;
204 205 206 207
			};
		};
	};

S
Stephen Warren 已提交
208 209 210 211 212 213 214 215
	ac97: ac97@70002000 {
		status = "okay";
		nvidia,codec-reset-gpio = <&gpio TEGRA_GPIO(V, 0)
			GPIO_ACTIVE_HIGH>;
		nvidia,codec-sync-gpio = <&gpio TEGRA_GPIO(P, 0)
			GPIO_ACTIVE_HIGH>;
	};

216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231
	nand-controller@70008000 {
		status = "okay";

		nand@0 {
			reg = <0>;
			#address-cells = <1>;
			#size-cells = <1>;
			nand-bus-width = <8>;
			nand-on-flash-bbt;
			nand-ecc-algo = "bch";
			nand-is-boot-medium;
			nand-ecc-maximize;
			wp-gpios = <&gpio TEGRA_GPIO(S, 0) GPIO_ACTIVE_LOW>;
		};
	};

232 233 234 235
	/*
	 * GEN1_I2C: I2C_SDA/SCL on SODIMM pin 194/196 (e.g. RTC on carrier
	 * board)
	 */
236 237 238 239
	i2c@7000c000 {
		clock-frequency = <400000>;
	};

240
	/* DDC_SCL/SDA on X3 pin 15/16 (e.g. display EDID) */
241
	i2c_ddc: i2c@7000c400 {
242
		clock-frequency = <10000>;
243 244
	};

245
	/* GEN2_I2C: unused */
246

247 248 249
	/* CAM/GEN3_I2C: used as EXT_IO1/2 GPIOs on SODIMM pin 133/127 */

	/* PWR_I2C: power I2C to PMIC and temperature sensor (On-module) */
250 251
	i2c@7000d000 {
		status = "okay";
252
		clock-frequency = <100000>;
253 254 255 256

		pmic: tps6586x@34 {
			compatible = "ti,tps6586x";
			reg = <0x34>;
257
			interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
258 259 260 261 262 263

			ti,system-power-controller;

			#gpio-cells = <2>;
			gpio-controller;

264
			sys-supply = <&vdd_3v3_reg>;
265 266 267 268
			vin-sm0-supply = <&sys_reg>;
			vin-sm1-supply = <&sys_reg>;
			vin-sm2-supply = <&sys_reg>;
			vinldo01-supply = <&sm2_reg>;
269 270 271 272
			vinldo23-supply = <&vdd_3v3_reg>;
			vinldo4-supply = <&vdd_3v3_reg>;
			vinldo678-supply = <&vdd_3v3_reg>;
			vinldo9-supply = <&vdd_3v3_reg>;
273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288

			regulators {
				#address-cells = <1>;
				#size-cells = <0>;

				sys_reg: regulator@0 {
					reg = <0>;
					regulator-compatible = "sys";
					regulator-name = "vdd_sys";
					regulator-always-on;
				};

				regulator@1 {
					reg = <1>;
					regulator-compatible = "sm0";
					regulator-name = "vdd_sm0,vdd_core";
289 290
					regulator-min-microvolt = <1200000>;
					regulator-max-microvolt = <1200000>;
291 292 293 294 295 296 297
					regulator-always-on;
				};

				regulator@2 {
					reg = <2>;
					regulator-compatible = "sm1";
					regulator-name = "vdd_sm1,vdd_cpu";
298 299
					regulator-min-microvolt = <1000000>;
					regulator-max-microvolt = <1000000>;
300 301 302 303 304 305 306
					regulator-always-on;
				};

				sm2_reg: regulator@3 {
					reg = <3>;
					regulator-compatible = "sm2";
					regulator-name = "vdd_sm2,vin_ldo*";
307 308
					regulator-min-microvolt = <1800000>;
					regulator-max-microvolt = <1800000>;
309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354
					regulator-always-on;
				};

				/* LDO0 is not connected to anything */

				regulator@5 {
					reg = <5>;
					regulator-compatible = "ldo1";
					regulator-name = "vdd_ldo1,avdd_pll*";
					regulator-min-microvolt = <1100000>;
					regulator-max-microvolt = <1100000>;
					regulator-always-on;
				};

				regulator@6 {
					reg = <6>;
					regulator-compatible = "ldo2";
					regulator-name = "vdd_ldo2,vdd_rtc";
					regulator-min-microvolt = <1200000>;
					regulator-max-microvolt = <1200000>;
				};

				/* LDO3 is not connected to anything */

				regulator@8 {
					reg = <8>;
					regulator-compatible = "ldo4";
					regulator-name = "vdd_ldo4,avdd_osc,vddio_sys";
					regulator-min-microvolt = <1800000>;
					regulator-max-microvolt = <1800000>;
					regulator-always-on;
				};

				ldo5_reg: regulator@9 {
					reg = <9>;
					regulator-compatible = "ldo5";
					regulator-name = "vdd_ldo5,vdd_fuse";
					regulator-min-microvolt = <3300000>;
					regulator-max-microvolt = <3300000>;
					regulator-always-on;
				};

				regulator@10 {
					reg = <10>;
					regulator-compatible = "ldo6";
					regulator-name = "vdd_ldo6,avdd_vdac,vddio_vi,vddio_cam";
355 356
					regulator-min-microvolt = <2850000>;
					regulator-max-microvolt = <2850000>;
357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400
				};

				hdmi_vdd_reg: regulator@11 {
					reg = <11>;
					regulator-compatible = "ldo7";
					regulator-name = "vdd_ldo7,avdd_hdmi";
					regulator-min-microvolt = <3300000>;
					regulator-max-microvolt = <3300000>;
				};

				hdmi_pll_reg: regulator@12 {
					reg = <12>;
					regulator-compatible = "ldo8";
					regulator-name = "vdd_ldo8,avdd_hdmi_pll";
					regulator-min-microvolt = <1800000>;
					regulator-max-microvolt = <1800000>;
				};

				regulator@13 {
					reg = <13>;
					regulator-compatible = "ldo9";
					regulator-name = "vdd_ldo9,avdd_2v85,vdd_ddr_rx";
					regulator-min-microvolt = <2850000>;
					regulator-max-microvolt = <2850000>;
					regulator-always-on;
				};

				regulator@14 {
					reg = <14>;
					regulator-compatible = "ldo_rtc";
					regulator-name = "vdd_rtc_out,vdd_cell";
					regulator-min-microvolt = <3300000>;
					regulator-max-microvolt = <3300000>;
					regulator-always-on;
				};
			};
		};

		temperature-sensor@4c {
			compatible = "national,lm95245";
			reg = <0x4c>;
		};
	};

401
	pmc@7000e400 {
J
Joseph Lo 已提交
402
		nvidia,suspend-mode = <1>;
403 404 405 406 407 408 409
		nvidia,cpu-pwr-good-time = <5000>;
		nvidia,cpu-pwr-off-time = <5000>;
		nvidia,core-pwr-good-time = <3845 3845>;
		nvidia,core-pwr-off-time = <3875>;
		nvidia,sys-clock-req-active-high;
	};

410 411 412 413 414 415 416 417 418 419 420 421 422 423 424 425 426 427 428 429 430 431 432 433 434 435 436 437 438 439 440 441 442 443 444 445 446 447 448 449 450 451 452 453 454 455 456 457 458 459 460 461 462 463 464 465 466 467 468 469 470 471 472 473 474 475 476 477 478 479 480 481 482
	memory-controller@7000f400 {
		emc-table@83250 {
			reg = <83250>;
			compatible = "nvidia,tegra20-emc-table";
			clock-frequency = <83250>;
			nvidia,emc-registers =   <0x00000005 0x00000011
				0x00000004 0x00000002 0x00000004 0x00000004
				0x00000001 0x0000000a 0x00000002 0x00000002
				0x00000001 0x00000001 0x00000003 0x00000004
				0x00000003 0x00000009 0x0000000c 0x0000025f
				0x00000000 0x00000003 0x00000003 0x00000002
				0x00000002 0x00000001 0x00000008 0x000000c8
				0x00000003 0x00000005 0x00000003 0x0000000c
				0x00000002 0x00000000 0x00000000 0x00000002
				0x00000000 0x00000000 0x00000083 0x00520006
				0x00000010 0x00000008 0x00000000 0x00000000
				0x00000000 0x00000000 0x00000000 0x00000000>;
		};
		emc-table@133200 {
			reg = <133200>;
			compatible = "nvidia,tegra20-emc-table";
			clock-frequency = <133200>;
			nvidia,emc-registers =   <0x00000008 0x00000019
				0x00000006 0x00000002 0x00000004 0x00000004
				0x00000001 0x0000000a 0x00000002 0x00000002
				0x00000002 0x00000001 0x00000003 0x00000004
				0x00000003 0x00000009 0x0000000c 0x0000039f
				0x00000000 0x00000003 0x00000003 0x00000002
				0x00000002 0x00000001 0x00000008 0x000000c8
				0x00000003 0x00000007 0x00000003 0x0000000c
				0x00000002 0x00000000 0x00000000 0x00000002
				0x00000000 0x00000000 0x00000083 0x00510006
				0x00000010 0x00000008 0x00000000 0x00000000
				0x00000000 0x00000000 0x00000000 0x00000000>;
		};
		emc-table@166500 {
			reg = <166500>;
			compatible = "nvidia,tegra20-emc-table";
			clock-frequency = <166500>;
			nvidia,emc-registers =   <0x0000000a 0x00000021
				0x00000008 0x00000003 0x00000004 0x00000004
				0x00000002 0x0000000a 0x00000003 0x00000003
				0x00000002 0x00000001 0x00000003 0x00000004
				0x00000003 0x00000009 0x0000000c 0x000004df
				0x00000000 0x00000003 0x00000003 0x00000003
				0x00000003 0x00000001 0x00000009 0x000000c8
				0x00000003 0x00000009 0x00000004 0x0000000c
				0x00000002 0x00000000 0x00000000 0x00000002
				0x00000000 0x00000000 0x00000083 0x004f0006
				0x00000010 0x00000008 0x00000000 0x00000000
				0x00000000 0x00000000 0x00000000 0x00000000>;
		};
		emc-table@333000 {
			reg = <333000>;
			compatible = "nvidia,tegra20-emc-table";
			clock-frequency = <333000>;
			nvidia,emc-registers =   <0x00000014 0x00000041
				0x0000000f 0x00000005 0x00000004 0x00000005
				0x00000003 0x0000000a 0x00000005 0x00000005
				0x00000004 0x00000001 0x00000003 0x00000004
				0x00000003 0x00000009 0x0000000c 0x000009ff
				0x00000000 0x00000003 0x00000003 0x00000005
				0x00000005 0x00000001 0x0000000e 0x000000c8
				0x00000003 0x00000011 0x00000006 0x0000000c
				0x00000002 0x00000000 0x00000000 0x00000002
				0x00000000 0x00000000 0x00000083 0x00380006
				0x00000010 0x00000008 0x00000000 0x00000000
				0x00000000 0x00000000 0x00000000 0x00000000>;
		};
	};

	usb@c5004000 {
		status = "okay";
483 484
		nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1)
			GPIO_ACTIVE_LOW>;
485 486 487
	};

	usb-phy@c5004000 {
488
		status = "okay";
489 490
		nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1)
			GPIO_ACTIVE_LOW>;
491 492 493
	};

	sdhci@c8000600 {
494
		cd-gpios = <&gpio TEGRA_GPIO(C, 7) GPIO_ACTIVE_LOW>;
495 496
	};

497 498 499 500 501
	clocks {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <0>;

502
		clk32k_in: clock@0 {
503
			compatible = "fixed-clock";
504
			reg = <0>;
505 506 507 508 509
			#clock-cells = <0>;
			clock-frequency = <32768>;
		};
	};

510 511 512 513 514
	regulators {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <0>;

515
		vdd_3v3_reg: regulator@100 {
516 517
			compatible = "regulator-fixed";
			reg = <100>;
518 519 520
			regulator-name = "vdd_3v3";
			regulator-min-microvolt = <3300000>;
			regulator-max-microvolt = <3300000>;
521 522 523 524 525 526 527 528 529 530 531 532
			regulator-always-on;
		};

		regulator@101 {
			compatible = "regulator-fixed";
			reg = <101>;
			regulator-name = "internal_usb";
			regulator-min-microvolt = <5000000>;
			regulator-max-microvolt = <5000000>;
			enable-active-high;
			regulator-boot-on;
			regulator-always-on;
533
			gpio = <&gpio TEGRA_GPIO(BB, 1) GPIO_ACTIVE_HIGH>;
534 535
		};
	};
S
Stephen Warren 已提交
536 537 538 539 540 541 542 543 544 545 546 547 548 549 550 551 552 553 554 555

	sound {
		compatible = "nvidia,tegra-audio-wm9712-colibri_t20",
			         "nvidia,tegra-audio-wm9712";
		nvidia,model = "Colibri T20 AC97 Audio";

		nvidia,audio-routing =
			"Headphone", "HPOUTL",
			"Headphone", "HPOUTR",
			"LineIn", "LINEINL",
			"LineIn", "LINEINR",
			"Mic", "MIC1";

		nvidia,ac97-controller = <&ac97>;

		clocks = <&tegra_car TEGRA20_CLK_PLL_A>,
			 <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
			 <&tegra_car TEGRA20_CLK_CDEV1>;
		clock-names = "pll_a", "pll_a_out0", "mclk";
	};
556
};