sh-sci.c 73.6 KB
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/*
 * SuperH on-chip serial module support.  (SCI with no FIFO / with FIFO)
 *
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 *  Copyright (C) 2002 - 2011  Paul Mundt
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 *  Copyright (C) 2015 Glider bvba
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 *  Modified to support SH7720 SCIF. Markus Brunner, Mark Jonas (Jul 2007).
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 *
 * based off of the old drivers/char/sh-sci.c by:
 *
 *   Copyright (C) 1999, 2000  Niibe Yutaka
 *   Copyright (C) 2000  Sugioka Toshinobu
 *   Modified to support multiple serial ports. Stuart Menefy (May 2000).
 *   Modified to support SecureEdge. David McCullough (2002)
 *   Modified to support SH7300 SCIF. Takashi Kusuda (Jun 2003).
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 *   Removed SH7300 support (Jul 2007).
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 *
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 */
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#if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
#define SUPPORT_SYSRQ
#endif
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#undef DEBUG

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#include <linux/clk.h>
#include <linux/console.h>
#include <linux/ctype.h>
#include <linux/cpufreq.h>
#include <linux/delay.h>
#include <linux/dmaengine.h>
#include <linux/dma-mapping.h>
#include <linux/err.h>
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#include <linux/errno.h>
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#include <linux/init.h>
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#include <linux/interrupt.h>
#include <linux/ioport.h>
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#include <linux/major.h>
#include <linux/module.h>
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#include <linux/mm.h>
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#include <linux/of.h>
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#include <linux/platform_device.h>
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#include <linux/pm_runtime.h>
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#include <linux/scatterlist.h>
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#include <linux/serial.h>
#include <linux/serial_sci.h>
#include <linux/sh_dma.h>
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#include <linux/slab.h>
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#include <linux/string.h>
#include <linux/sysrq.h>
#include <linux/timer.h>
#include <linux/tty.h>
#include <linux/tty_flip.h>
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#ifdef CONFIG_SUPERH
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#include <asm/sh_bios.h>
#endif

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#include "serial_mctrl_gpio.h"
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#include "sh-sci.h"

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/* Offsets into the sci_port->irqs array */
enum {
	SCIx_ERI_IRQ,
	SCIx_RXI_IRQ,
	SCIx_TXI_IRQ,
	SCIx_BRI_IRQ,
	SCIx_NR_IRQS,

	SCIx_MUX_IRQ = SCIx_NR_IRQS,	/* special case */
};

#define SCIx_IRQ_IS_MUXED(port)			\
	((port)->irqs[SCIx_ERI_IRQ] ==	\
	 (port)->irqs[SCIx_RXI_IRQ]) ||	\
	((port)->irqs[SCIx_ERI_IRQ] &&	\
	 ((port)->irqs[SCIx_RXI_IRQ] < 0))

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enum SCI_CLKS {
	SCI_FCK,		/* Functional Clock */
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	SCI_SCK,		/* Optional External Clock */
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	SCI_BRG_INT,		/* Optional BRG Internal Clock Source */
	SCI_SCIF_CLK,		/* Optional BRG External Clock Source */
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	SCI_NUM_CLKS
};

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/* Bit x set means sampling rate x + 1 is supported */
#define SCI_SR(x)		BIT((x) - 1)
#define SCI_SR_RANGE(x, y)	GENMASK((y) - 1, (x) - 1)

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#define SCI_SR_SCIFAB		SCI_SR(5) | SCI_SR(7) | SCI_SR(11) | \
				SCI_SR(13) | SCI_SR(16) | SCI_SR(17) | \
				SCI_SR(19) | SCI_SR(27)

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#define min_sr(_port)		ffs((_port)->sampling_rate_mask)
#define max_sr(_port)		fls((_port)->sampling_rate_mask)

/* Iterate over all supported sampling rates, from high to low */
#define for_each_sr(_sr, _port)						\
	for ((_sr) = max_sr(_port); (_sr) >= min_sr(_port); (_sr)--)	\
		if ((_port)->sampling_rate_mask & SCI_SR((_sr)))

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struct plat_sci_reg {
	u8 offset, size;
};

struct sci_port_params {
	const struct plat_sci_reg regs[SCIx_NR_REGS];
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	unsigned int fifosize;
	unsigned int overrun_reg;
	unsigned int overrun_mask;
	unsigned int sampling_rate_mask;
	unsigned int error_mask;
	unsigned int error_clear;
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};

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struct sci_port {
	struct uart_port	port;

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	/* Platform configuration */
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	const struct sci_port_params *params;
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	const struct plat_sci_port *cfg;
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	unsigned int		sampling_rate_mask;
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	resource_size_t		reg_size;
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	struct mctrl_gpios	*gpios;
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	/* Clocks */
	struct clk		*clks[SCI_NUM_CLKS];
	unsigned long		clk_rates[SCI_NUM_CLKS];
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	int			irqs[SCIx_NR_IRQS];
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	char			*irqstr[SCIx_NR_IRQS];

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	struct dma_chan			*chan_tx;
	struct dma_chan			*chan_rx;
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#ifdef CONFIG_SERIAL_SH_SCI_DMA
	dma_cookie_t			cookie_tx;
	dma_cookie_t			cookie_rx[2];
	dma_cookie_t			active_rx;
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	dma_addr_t			tx_dma_addr;
	unsigned int			tx_dma_len;
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	struct scatterlist		sg_rx[2];
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	void				*rx_buf[2];
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	size_t				buf_len_rx;
	struct work_struct		work_tx;
	struct timer_list		rx_timer;
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	unsigned int			rx_timeout;
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#endif
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	bool has_rtscts;
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	bool autorts;
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};

#define SCI_NPORTS CONFIG_SERIAL_SH_SCI_NR_UARTS
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static struct sci_port sci_ports[SCI_NPORTS];
static struct uart_driver sci_uart_driver;
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static inline struct sci_port *
to_sci_port(struct uart_port *uart)
{
	return container_of(uart, struct sci_port, port);
}

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static const struct sci_port_params sci_port_params[SCIx_NR_REGTYPES] = {
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	/*
	 * Common SCI definitions, dependent on the port's regshift
	 * value.
	 */
	[SCIx_SCI_REGTYPE] = {
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		.regs = {
			[SCSMR]		= { 0x00,  8 },
			[SCBRR]		= { 0x01,  8 },
			[SCSCR]		= { 0x02,  8 },
			[SCxTDR]	= { 0x03,  8 },
			[SCxSR]		= { 0x04,  8 },
			[SCxRDR]	= { 0x05,  8 },
		},
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		.fifosize = 1,
		.overrun_reg = SCxSR,
		.overrun_mask = SCI_ORER,
		.sampling_rate_mask = SCI_SR(32),
		.error_mask = SCI_DEFAULT_ERROR_MASK | SCI_ORER,
		.error_clear = SCI_ERROR_CLEAR & ~SCI_ORER,
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	},

	/*
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	 * Common definitions for legacy IrDA ports.
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	 */
	[SCIx_IRDA_REGTYPE] = {
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		.regs = {
			[SCSMR]		= { 0x00,  8 },
			[SCBRR]		= { 0x02,  8 },
			[SCSCR]		= { 0x04,  8 },
			[SCxTDR]	= { 0x06,  8 },
			[SCxSR]		= { 0x08, 16 },
			[SCxRDR]	= { 0x0a,  8 },
			[SCFCR]		= { 0x0c,  8 },
			[SCFDR]		= { 0x0e, 16 },
		},
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		.fifosize = 1,
		.overrun_reg = SCxSR,
		.overrun_mask = SCI_ORER,
		.sampling_rate_mask = SCI_SR(32),
		.error_mask = SCI_DEFAULT_ERROR_MASK | SCI_ORER,
		.error_clear = SCI_ERROR_CLEAR & ~SCI_ORER,
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	},

	/*
	 * Common SCIFA definitions.
	 */
	[SCIx_SCIFA_REGTYPE] = {
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		.regs = {
			[SCSMR]		= { 0x00, 16 },
			[SCBRR]		= { 0x04,  8 },
			[SCSCR]		= { 0x08, 16 },
			[SCxTDR]	= { 0x20,  8 },
			[SCxSR]		= { 0x14, 16 },
			[SCxRDR]	= { 0x24,  8 },
			[SCFCR]		= { 0x18, 16 },
			[SCFDR]		= { 0x1c, 16 },
			[SCPCR]		= { 0x30, 16 },
			[SCPDR]		= { 0x34, 16 },
		},
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		.fifosize = 64,
		.overrun_reg = SCxSR,
		.overrun_mask = SCIFA_ORER,
		.sampling_rate_mask = SCI_SR_SCIFAB,
		.error_mask = SCIF_DEFAULT_ERROR_MASK | SCIFA_ORER,
		.error_clear = SCIF_ERROR_CLEAR & ~SCIFA_ORER,
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	},

	/*
	 * Common SCIFB definitions.
	 */
	[SCIx_SCIFB_REGTYPE] = {
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		.regs = {
			[SCSMR]		= { 0x00, 16 },
			[SCBRR]		= { 0x04,  8 },
			[SCSCR]		= { 0x08, 16 },
			[SCxTDR]	= { 0x40,  8 },
			[SCxSR]		= { 0x14, 16 },
			[SCxRDR]	= { 0x60,  8 },
			[SCFCR]		= { 0x18, 16 },
			[SCTFDR]	= { 0x38, 16 },
			[SCRFDR]	= { 0x3c, 16 },
			[SCPCR]		= { 0x30, 16 },
			[SCPDR]		= { 0x34, 16 },
		},
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		.fifosize = 256,
		.overrun_reg = SCxSR,
		.overrun_mask = SCIFA_ORER,
		.sampling_rate_mask = SCI_SR_SCIFAB,
		.error_mask = SCIF_DEFAULT_ERROR_MASK | SCIFA_ORER,
		.error_clear = SCIF_ERROR_CLEAR & ~SCIFA_ORER,
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	},

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	/*
	 * Common SH-2(A) SCIF definitions for ports with FIFO data
	 * count registers.
	 */
	[SCIx_SH2_SCIF_FIFODATA_REGTYPE] = {
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		.regs = {
			[SCSMR]		= { 0x00, 16 },
			[SCBRR]		= { 0x04,  8 },
			[SCSCR]		= { 0x08, 16 },
			[SCxTDR]	= { 0x0c,  8 },
			[SCxSR]		= { 0x10, 16 },
			[SCxRDR]	= { 0x14,  8 },
			[SCFCR]		= { 0x18, 16 },
			[SCFDR]		= { 0x1c, 16 },
			[SCSPTR]	= { 0x20, 16 },
			[SCLSR]		= { 0x24, 16 },
		},
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		.fifosize = 16,
		.overrun_reg = SCLSR,
		.overrun_mask = SCLSR_ORER,
		.sampling_rate_mask = SCI_SR(32),
		.error_mask = SCIF_DEFAULT_ERROR_MASK,
		.error_clear = SCIF_ERROR_CLEAR,
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	},

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	/*
	 * Common SH-3 SCIF definitions.
	 */
	[SCIx_SH3_SCIF_REGTYPE] = {
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		.regs = {
			[SCSMR]		= { 0x00,  8 },
			[SCBRR]		= { 0x02,  8 },
			[SCSCR]		= { 0x04,  8 },
			[SCxTDR]	= { 0x06,  8 },
			[SCxSR]		= { 0x08, 16 },
			[SCxRDR]	= { 0x0a,  8 },
			[SCFCR]		= { 0x0c,  8 },
			[SCFDR]		= { 0x0e, 16 },
		},
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		.fifosize = 16,
		.overrun_reg = SCLSR,
		.overrun_mask = SCLSR_ORER,
		.sampling_rate_mask = SCI_SR(32),
		.error_mask = SCIF_DEFAULT_ERROR_MASK,
		.error_clear = SCIF_ERROR_CLEAR,
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	},

	/*
	 * Common SH-4(A) SCIF(B) definitions.
	 */
	[SCIx_SH4_SCIF_REGTYPE] = {
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		.regs = {
			[SCSMR]		= { 0x00, 16 },
			[SCBRR]		= { 0x04,  8 },
			[SCSCR]		= { 0x08, 16 },
			[SCxTDR]	= { 0x0c,  8 },
			[SCxSR]		= { 0x10, 16 },
			[SCxRDR]	= { 0x14,  8 },
			[SCFCR]		= { 0x18, 16 },
			[SCFDR]		= { 0x1c, 16 },
			[SCSPTR]	= { 0x20, 16 },
			[SCLSR]		= { 0x24, 16 },
		},
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		.fifosize = 16,
		.overrun_reg = SCLSR,
		.overrun_mask = SCLSR_ORER,
		.sampling_rate_mask = SCI_SR(32),
		.error_mask = SCIF_DEFAULT_ERROR_MASK,
		.error_clear = SCIF_ERROR_CLEAR,
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	},

	/*
	 * Common SCIF definitions for ports with a Baud Rate Generator for
	 * External Clock (BRG).
	 */
	[SCIx_SH4_SCIF_BRG_REGTYPE] = {
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		.regs = {
			[SCSMR]		= { 0x00, 16 },
			[SCBRR]		= { 0x04,  8 },
			[SCSCR]		= { 0x08, 16 },
			[SCxTDR]	= { 0x0c,  8 },
			[SCxSR]		= { 0x10, 16 },
			[SCxRDR]	= { 0x14,  8 },
			[SCFCR]		= { 0x18, 16 },
			[SCFDR]		= { 0x1c, 16 },
			[SCSPTR]	= { 0x20, 16 },
			[SCLSR]		= { 0x24, 16 },
			[SCDL]		= { 0x30, 16 },
			[SCCKS]		= { 0x34, 16 },
		},
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		.fifosize = 16,
		.overrun_reg = SCLSR,
		.overrun_mask = SCLSR_ORER,
		.sampling_rate_mask = SCI_SR(32),
		.error_mask = SCIF_DEFAULT_ERROR_MASK,
		.error_clear = SCIF_ERROR_CLEAR,
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	},

	/*
	 * Common HSCIF definitions.
	 */
	[SCIx_HSCIF_REGTYPE] = {
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		.regs = {
			[SCSMR]		= { 0x00, 16 },
			[SCBRR]		= { 0x04,  8 },
			[SCSCR]		= { 0x08, 16 },
			[SCxTDR]	= { 0x0c,  8 },
			[SCxSR]		= { 0x10, 16 },
			[SCxRDR]	= { 0x14,  8 },
			[SCFCR]		= { 0x18, 16 },
			[SCFDR]		= { 0x1c, 16 },
			[SCSPTR]	= { 0x20, 16 },
			[SCLSR]		= { 0x24, 16 },
			[HSSRR]		= { 0x40, 16 },
			[SCDL]		= { 0x30, 16 },
			[SCCKS]		= { 0x34, 16 },
		},
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		.fifosize = 128,
		.overrun_reg = SCLSR,
		.overrun_mask = SCLSR_ORER,
		.sampling_rate_mask = SCI_SR_RANGE(8, 32),
		.error_mask = SCIF_DEFAULT_ERROR_MASK,
		.error_clear = SCIF_ERROR_CLEAR,
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	},

	/*
	 * Common SH-4(A) SCIF(B) definitions for ports without an SCSPTR
	 * register.
	 */
	[SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE] = {
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		.regs = {
			[SCSMR]		= { 0x00, 16 },
			[SCBRR]		= { 0x04,  8 },
			[SCSCR]		= { 0x08, 16 },
			[SCxTDR]	= { 0x0c,  8 },
			[SCxSR]		= { 0x10, 16 },
			[SCxRDR]	= { 0x14,  8 },
			[SCFCR]		= { 0x18, 16 },
			[SCFDR]		= { 0x1c, 16 },
			[SCLSR]		= { 0x24, 16 },
		},
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		.fifosize = 16,
		.overrun_reg = SCLSR,
		.overrun_mask = SCLSR_ORER,
		.sampling_rate_mask = SCI_SR(32),
		.error_mask = SCIF_DEFAULT_ERROR_MASK,
		.error_clear = SCIF_ERROR_CLEAR,
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	},

	/*
	 * Common SH-4(A) SCIF(B) definitions for ports with FIFO data
	 * count registers.
	 */
	[SCIx_SH4_SCIF_FIFODATA_REGTYPE] = {
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		.regs = {
			[SCSMR]		= { 0x00, 16 },
			[SCBRR]		= { 0x04,  8 },
			[SCSCR]		= { 0x08, 16 },
			[SCxTDR]	= { 0x0c,  8 },
			[SCxSR]		= { 0x10, 16 },
			[SCxRDR]	= { 0x14,  8 },
			[SCFCR]		= { 0x18, 16 },
			[SCFDR]		= { 0x1c, 16 },
			[SCTFDR]	= { 0x1c, 16 },	/* aliased to SCFDR */
			[SCRFDR]	= { 0x20, 16 },
			[SCSPTR]	= { 0x24, 16 },
			[SCLSR]		= { 0x28, 16 },
		},
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		.fifosize = 16,
		.overrun_reg = SCLSR,
		.overrun_mask = SCLSR_ORER,
		.sampling_rate_mask = SCI_SR(32),
		.error_mask = SCIF_DEFAULT_ERROR_MASK,
		.error_clear = SCIF_ERROR_CLEAR,
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	},

	/*
	 * SH7705-style SCIF(B) ports, lacking both SCSPTR and SCLSR
	 * registers.
	 */
	[SCIx_SH7705_SCIF_REGTYPE] = {
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		.regs = {
			[SCSMR]		= { 0x00, 16 },
			[SCBRR]		= { 0x04,  8 },
			[SCSCR]		= { 0x08, 16 },
			[SCxTDR]	= { 0x20,  8 },
			[SCxSR]		= { 0x14, 16 },
			[SCxRDR]	= { 0x24,  8 },
			[SCFCR]		= { 0x18, 16 },
			[SCFDR]		= { 0x1c, 16 },
		},
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		.fifosize = 16,
		.overrun_reg = SCxSR,
		.overrun_mask = SCIFA_ORER,
		.sampling_rate_mask = SCI_SR(16),
		.error_mask = SCIF_DEFAULT_ERROR_MASK | SCIFA_ORER,
		.error_clear = SCIF_ERROR_CLEAR & ~SCIFA_ORER,
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	},
};

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#define sci_getreg(up, offset)		(&to_sci_port(up)->params->regs[offset])
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/*
 * The "offset" here is rather misleading, in that it refers to an enum
 * value relative to the port mapping rather than the fixed offset
 * itself, which needs to be manually retrieved from the platform's
 * register map for the given port.
 */
static unsigned int sci_serial_in(struct uart_port *p, int offset)
{
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	const struct plat_sci_reg *reg = sci_getreg(p, offset);
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	if (reg->size == 8)
		return ioread8(p->membase + (reg->offset << p->regshift));
	else if (reg->size == 16)
		return ioread16(p->membase + (reg->offset << p->regshift));
	else
		WARN(1, "Invalid register access\n");

	return 0;
}

static void sci_serial_out(struct uart_port *p, int offset, int value)
{
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	const struct plat_sci_reg *reg = sci_getreg(p, offset);
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	if (reg->size == 8)
		iowrite8(value, p->membase + (reg->offset << p->regshift));
	else if (reg->size == 16)
		iowrite16(value, p->membase + (reg->offset << p->regshift));
	else
		WARN(1, "Invalid register access\n");
}

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static void sci_port_enable(struct sci_port *sci_port)
{
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	unsigned int i;

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	if (!sci_port->port.dev)
		return;

	pm_runtime_get_sync(sci_port->port.dev);

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	for (i = 0; i < SCI_NUM_CLKS; i++) {
		clk_prepare_enable(sci_port->clks[i]);
		sci_port->clk_rates[i] = clk_get_rate(sci_port->clks[i]);
	}
	sci_port->port.uartclk = sci_port->clk_rates[SCI_FCK];
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}

static void sci_port_disable(struct sci_port *sci_port)
{
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	unsigned int i;

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	if (!sci_port->port.dev)
		return;

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	for (i = SCI_NUM_CLKS; i-- > 0; )
		clk_disable_unprepare(sci_port->clks[i]);
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	pm_runtime_put_sync(sci_port->port.dev);
}

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static inline unsigned long port_rx_irq_mask(struct uart_port *port)
{
	/*
	 * Not all ports (such as SCIFA) will support REIE. Rather than
	 * special-casing the port type, we check the port initialization
	 * IRQ enable mask to see whether the IRQ is desired at all. If
	 * it's unset, it's logically inferred that there's no point in
	 * testing for it.
	 */
	return SCSCR_RIE | (to_sci_port(port)->cfg->scscr & SCSCR_REIE);
}

static void sci_start_tx(struct uart_port *port)
{
	struct sci_port *s = to_sci_port(port);
	unsigned short ctrl;

#ifdef CONFIG_SERIAL_SH_SCI_DMA
	if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
		u16 new, scr = serial_port_in(port, SCSCR);
		if (s->chan_tx)
			new = scr | SCSCR_TDRQE;
		else
			new = scr & ~SCSCR_TDRQE;
		if (new != scr)
			serial_port_out(port, SCSCR, new);
	}

	if (s->chan_tx && !uart_circ_empty(&s->port.state->xmit) &&
	    dma_submit_error(s->cookie_tx)) {
		s->cookie_tx = 0;
		schedule_work(&s->work_tx);
	}
#endif

	if (!s->chan_tx || port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
		/* Set TIE (Transmit Interrupt Enable) bit in SCSCR */
		ctrl = serial_port_in(port, SCSCR);
		serial_port_out(port, SCSCR, ctrl | SCSCR_TIE);
	}
}

static void sci_stop_tx(struct uart_port *port)
{
	unsigned short ctrl;

	/* Clear TIE (Transmit Interrupt Enable) bit in SCSCR */
	ctrl = serial_port_in(port, SCSCR);

	if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
		ctrl &= ~SCSCR_TDRQE;

	ctrl &= ~SCSCR_TIE;

	serial_port_out(port, SCSCR, ctrl);
}

static void sci_start_rx(struct uart_port *port)
{
	unsigned short ctrl;

	ctrl = serial_port_in(port, SCSCR) | port_rx_irq_mask(port);

	if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
		ctrl &= ~SCSCR_RDRQE;

	serial_port_out(port, SCSCR, ctrl);
}

static void sci_stop_rx(struct uart_port *port)
{
	unsigned short ctrl;

	ctrl = serial_port_in(port, SCSCR);

	if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
		ctrl &= ~SCSCR_RDRQE;

	ctrl &= ~port_rx_irq_mask(port);

	serial_port_out(port, SCSCR, ctrl);
}

606 607 608 609 610
static void sci_clear_SCxSR(struct uart_port *port, unsigned int mask)
{
	if (port->type == PORT_SCI) {
		/* Just store the mask */
		serial_port_out(port, SCxSR, mask);
611
	} else if (to_sci_port(port)->params->overrun_mask == SCIFA_ORER) {
612 613 614 615 616 617 618 619 620 621
		/* SCIFA/SCIFB and SCIF on SH7705/SH7720/SH7721 */
		/* Only clear the status bits we want to clear */
		serial_port_out(port, SCxSR,
				serial_port_in(port, SCxSR) & mask);
	} else {
		/* Store the mask, clear parity/framing errors */
		serial_port_out(port, SCxSR, mask & ~(SCIF_FERC | SCIF_PERC));
	}
}

622 623
#if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_SH_SCI_CONSOLE) || \
    defined(CONFIG_SERIAL_SH_SCI_EARLYCON)
624 625

#ifdef CONFIG_CONSOLE_POLL
626
static int sci_poll_get_char(struct uart_port *port)
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{
	unsigned short status;
	int c;

631
	do {
632
		status = serial_port_in(port, SCxSR);
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633
		if (status & SCxSR_ERRORS(port)) {
634
			sci_clear_SCxSR(port, SCxSR_ERROR_CLEAR(port));
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			continue;
		}
637 638 639 640 641
		break;
	} while (1);

	if (!(status & SCxSR_RDxF(port)))
		return NO_POLL_CHAR;
642

643
	c = serial_port_in(port, SCxRDR);
644

645
	/* Dummy read */
646
	serial_port_in(port, SCxSR);
647
	sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
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648 649 650

	return c;
}
651
#endif
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652

653
static void sci_poll_put_char(struct uart_port *port, unsigned char c)
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654 655 656 657
{
	unsigned short status;

	do {
658
		status = serial_port_in(port, SCxSR);
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	} while (!(status & SCxSR_TDxE(port)));

661
	serial_port_out(port, SCxTDR, c);
662
	sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port) & ~SCxSR_TEND(port));
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}
664 665
#endif /* CONFIG_CONSOLE_POLL || CONFIG_SERIAL_SH_SCI_CONSOLE ||
	  CONFIG_SERIAL_SH_SCI_EARLYCON */
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667
static void sci_init_pins(struct uart_port *port, unsigned int cflag)
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668
{
669
	struct sci_port *s = to_sci_port(port);
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671 672 673 674 675 676
	/*
	 * Use port-specific handler if provided.
	 */
	if (s->cfg->ops && s->cfg->ops->init_pins) {
		s->cfg->ops->init_pins(port, cflag);
		return;
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	}
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679 680 681 682 683
	if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
		u16 ctrl = serial_port_in(port, SCPCR);

		/* Enable RXD and TXD pin functions */
		ctrl &= ~(SCPCR_RXDC | SCPCR_TXDC);
684
		if (to_sci_port(port)->has_rtscts) {
685 686 687 688 689 690 691 692 693
			/* RTS# is output, driven 1 */
			ctrl |= SCPCR_RTSC;
			serial_port_out(port, SCPDR,
				serial_port_in(port, SCPDR) | SCPDR_RTSD);
			/* Enable CTS# pin function */
			ctrl &= ~SCPCR_CTSC;
		}
		serial_port_out(port, SCPCR, ctrl);
	} else if (sci_getreg(port, SCSPTR)->size) {
694 695 696 697 698 699 700
		u16 status = serial_port_in(port, SCSPTR);

		/* RTS# is output, driven 1 */
		status |= SCSPTR_RTSIO | SCSPTR_RTSDT;
		/* CTS# and SCK are inputs */
		status &= ~(SCSPTR_CTSIO | SCSPTR_SCKIO);
		serial_port_out(port, SCSPTR, status);
701
	}
702
}
703

704
static int sci_txfill(struct uart_port *port)
705
{
706 707
	struct sci_port *s = to_sci_port(port);
	unsigned int fifo_mask = (s->params->fifosize << 1) - 1;
708
	const struct plat_sci_reg *reg;
709

710 711
	reg = sci_getreg(port, SCTFDR);
	if (reg->size)
712
		return serial_port_in(port, SCTFDR) & fifo_mask;
713

714 715
	reg = sci_getreg(port, SCFDR);
	if (reg->size)
716
		return serial_port_in(port, SCFDR) >> 8;
717

718
	return !(serial_port_in(port, SCxSR) & SCI_TDRE);
719 720
}

721 722
static int sci_txroom(struct uart_port *port)
{
723
	return port->fifosize - sci_txfill(port);
724 725 726
}

static int sci_rxfill(struct uart_port *port)
727
{
728 729
	struct sci_port *s = to_sci_port(port);
	unsigned int fifo_mask = (s->params->fifosize << 1) - 1;
730
	const struct plat_sci_reg *reg;
731 732 733

	reg = sci_getreg(port, SCRFDR);
	if (reg->size)
734
		return serial_port_in(port, SCRFDR) & fifo_mask;
735 736 737

	reg = sci_getreg(port, SCFDR);
	if (reg->size)
738
		return serial_port_in(port, SCFDR) & fifo_mask;
739

740
	return (serial_port_in(port, SCxSR) & SCxSR_RDxF(port)) != 0;
741 742
}

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/* ********************************************************************** *
 *                   the interrupt related routines                       *
 * ********************************************************************** */

static void sci_transmit_chars(struct uart_port *port)
{
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	struct circ_buf *xmit = &port->state->xmit;
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750 751 752
	unsigned int stopped = uart_tx_stopped(port);
	unsigned short status;
	unsigned short ctrl;
753
	int count;
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755
	status = serial_port_in(port, SCxSR);
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756
	if (!(status & SCxSR_TDxE(port))) {
757
		ctrl = serial_port_in(port, SCSCR);
758
		if (uart_circ_empty(xmit))
759
			ctrl &= ~SCSCR_TIE;
760
		else
761
			ctrl |= SCSCR_TIE;
762
		serial_port_out(port, SCSCR, ctrl);
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763 764 765
		return;
	}

766
	count = sci_txroom(port);
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	do {
		unsigned char c;

		if (port->x_char) {
			c = port->x_char;
			port->x_char = 0;
		} else if (!uart_circ_empty(xmit) && !stopped) {
			c = xmit->buf[xmit->tail];
			xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
		} else {
			break;
		}

781
		serial_port_out(port, SCxTDR, c);
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		port->icount.tx++;
	} while (--count > 0);

786
	sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port));
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	if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
		uart_write_wakeup(port);
	if (uart_circ_empty(xmit)) {
791
		sci_stop_tx(port);
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792
	} else {
793
		ctrl = serial_port_in(port, SCSCR);
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794

795
		if (port->type != PORT_SCI) {
796
			serial_port_in(port, SCxSR); /* Dummy read */
797
			sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port));
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		}

800
		ctrl |= SCSCR_TIE;
801
		serial_port_out(port, SCSCR, ctrl);
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	}
}

/* On SH3, SCIF may read end-of-break as a space->mark char */
806
#define STEPFN(c)  ({int __c = (c); (((__c-1)|(__c)) == -1); })
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807

808
static void sci_receive_chars(struct uart_port *port)
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{
810
	struct tty_port *tport = &port->state->port;
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811 812
	int i, count, copied = 0;
	unsigned short status;
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	unsigned char flag;
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814

815
	status = serial_port_in(port, SCxSR);
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816 817 818 819 820
	if (!(status & SCxSR_RDxF(port)))
		return;

	while (1) {
		/* Don't copy more bytes than there is room for in the buffer */
821
		count = tty_buffer_request_room(tport, sci_rxfill(port));
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822 823 824 825 826 827

		/* If for any reason we can't copy more data, we're done! */
		if (count == 0)
			break;

		if (port->type == PORT_SCI) {
828
			char c = serial_port_in(port, SCxRDR);
829
			if (uart_handle_sysrq_char(port, c))
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830
				count = 0;
831
			else
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				tty_insert_flip_char(tport, c, TTY_NORMAL);
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833
		} else {
834
			for (i = 0; i < count; i++) {
835
				char c = serial_port_in(port, SCxRDR);
836

837
				status = serial_port_in(port, SCxSR);
838
				if (uart_handle_sysrq_char(port, c)) {
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839 840 841 842 843
					count--; i--;
					continue;
				}

				/* Store data and status */
844
				if (status & SCxSR_FER(port)) {
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845
					flag = TTY_FRAME;
846
					port->icount.frame++;
847
					dev_notice(port->dev, "frame error\n");
848
				} else if (status & SCxSR_PER(port)) {
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849
					flag = TTY_PARITY;
850
					port->icount.parity++;
851
					dev_notice(port->dev, "parity error\n");
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852 853
				} else
					flag = TTY_NORMAL;
854

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855
				tty_insert_flip_char(tport, c, flag);
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856 857 858
			}
		}

859
		serial_port_in(port, SCxSR); /* dummy read */
860
		sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
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		copied += count;
		port->icount.rx += count;
	}

	if (copied) {
		/* Tell the rest of the system the news. New characters! */
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		tty_flip_buffer_push(tport);
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869
	} else {
870
		serial_port_in(port, SCxSR); /* dummy read */
871
		sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
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872 873 874
	}
}

875
static int sci_handle_errors(struct uart_port *port)
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876 877
{
	int copied = 0;
878
	unsigned short status = serial_port_in(port, SCxSR);
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879
	struct tty_port *tport = &port->state->port;
880
	struct sci_port *s = to_sci_port(port);
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881

882
	/* Handle overruns */
883
	if (status & s->params->overrun_mask) {
884
		port->icount.overrun++;
885

886 887 888
		/* overrun error */
		if (tty_insert_flip_char(tport, 0, TTY_OVERRUN))
			copied++;
889

890
		dev_notice(port->dev, "overrun error\n");
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891 892
	}

893
	if (status & SCxSR_FER(port)) {
894 895
		/* frame error */
		port->icount.frame++;
896

897 898
		if (tty_insert_flip_char(tport, 0, TTY_FRAME))
			copied++;
899

900
		dev_notice(port->dev, "frame error\n");
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901 902
	}

903
	if (status & SCxSR_PER(port)) {
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904
		/* parity error */
905 906
		port->icount.parity++;

J
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907
		if (tty_insert_flip_char(tport, 0, TTY_PARITY))
908
			copied++;
909

910
		dev_notice(port->dev, "parity error\n");
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911 912
	}

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913
	if (copied)
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914
		tty_flip_buffer_push(tport);
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915 916 917 918

	return copied;
}

919
static int sci_handle_fifo_overrun(struct uart_port *port)
920
{
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921
	struct tty_port *tport = &port->state->port;
922
	struct sci_port *s = to_sci_port(port);
923
	const struct plat_sci_reg *reg;
924
	int copied = 0;
925
	u16 status;
926

927
	reg = sci_getreg(port, s->params->overrun_reg);
928
	if (!reg->size)
929 930
		return 0;

931 932 933 934
	status = serial_port_in(port, s->params->overrun_reg);
	if (status & s->params->overrun_mask) {
		status &= ~s->params->overrun_mask;
		serial_port_out(port, s->params->overrun_reg, status);
935

936 937
		port->icount.overrun++;

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938
		tty_insert_flip_char(tport, 0, TTY_OVERRUN);
J
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939
		tty_flip_buffer_push(tport);
940

941
		dev_dbg(port->dev, "overrun error\n");
942 943 944 945 946 947
		copied++;
	}

	return copied;
}

948
static int sci_handle_breaks(struct uart_port *port)
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949 950
{
	int copied = 0;
951
	unsigned short status = serial_port_in(port, SCxSR);
J
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952
	struct tty_port *tport = &port->state->port;
L
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953

954 955 956
	if (uart_handle_break(port))
		return 0;

957
	if (status & SCxSR_BRK(port)) {
958 959
		port->icount.brk++;

L
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960
		/* Notify of BREAK */
J
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961
		if (tty_insert_flip_char(tport, 0, TTY_BREAK))
A
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962
			copied++;
963 964

		dev_dbg(port->dev, "BREAK detected\n");
L
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965 966
	}

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967
	if (copied)
J
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968
		tty_flip_buffer_push(tport);
969

970 971
	copied += sci_handle_fifo_overrun(port);

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972 973 974
	return copied;
}

975
#ifdef CONFIG_SERIAL_SH_SCI_DMA
976 977 978 979 980 981
static void sci_dma_tx_complete(void *arg)
{
	struct sci_port *s = arg;
	struct uart_port *port = &s->port;
	struct circ_buf *xmit = &port->state->xmit;
	unsigned long flags;
982

983
	dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
984

985
	spin_lock_irqsave(&port->lock, flags);
986

987 988
	xmit->tail += s->tx_dma_len;
	xmit->tail &= UART_XMIT_SIZE - 1;
989

990
	port->icount.tx += s->tx_dma_len;
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991

992 993
	if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
		uart_write_wakeup(port);
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994

995 996 997 998 999 1000 1001 1002 1003 1004
	if (!uart_circ_empty(xmit)) {
		s->cookie_tx = 0;
		schedule_work(&s->work_tx);
	} else {
		s->cookie_tx = -EINVAL;
		if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
			u16 ctrl = serial_port_in(port, SCSCR);
			serial_port_out(port, SCSCR, ctrl & ~SCSCR_TIE);
		}
	}
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1005

1006
	spin_unlock_irqrestore(&port->lock, flags);
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}

1009 1010
/* Locking: called with port lock held */
static int sci_dma_rx_push(struct sci_port *s, void *buf, size_t count)
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1011
{
1012 1013 1014
	struct uart_port *port = &s->port;
	struct tty_port *tport = &port->state->port;
	int copied;
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1015

1016
	copied = tty_insert_flip_string(tport, buf, count);
1017
	if (copied < count)
1018
		port->icount.buf_overrun++;
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1019

1020
	port->icount.rx += copied;
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1021

1022
	return copied;
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1023 1024
}

1025
static int sci_dma_rx_find_active(struct sci_port *s)
L
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1026
{
1027
	unsigned int i;
L
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1028

1029 1030 1031
	for (i = 0; i < ARRAY_SIZE(s->cookie_rx); i++)
		if (s->active_rx == s->cookie_rx[i])
			return i;
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1032

1033
	return -1;
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1034 1035
}

1036
static void sci_rx_dma_release(struct sci_port *s, bool enable_pio)
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Paul Mundt 已提交
1037
{
1038 1039 1040 1041 1042 1043 1044 1045 1046 1047 1048 1049 1050 1051
	struct dma_chan *chan = s->chan_rx;
	struct uart_port *port = &s->port;
	unsigned long flags;

	spin_lock_irqsave(&port->lock, flags);
	s->chan_rx = NULL;
	s->cookie_rx[0] = s->cookie_rx[1] = -EINVAL;
	spin_unlock_irqrestore(&port->lock, flags);
	dmaengine_terminate_all(chan);
	dma_free_coherent(chan->device->dev, s->buf_len_rx * 2, s->rx_buf[0],
			  sg_dma_address(&s->sg_rx[0]));
	dma_release_channel(chan);
	if (enable_pio)
		sci_start_rx(port);
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1052 1053
}

1054
static void sci_dma_rx_complete(void *arg)
L
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1055
{
1056
	struct sci_port *s = arg;
1057
	struct dma_chan *chan = s->chan_rx;
1058
	struct uart_port *port = &s->port;
1059
	struct dma_async_tx_descriptor *desc;
1060 1061
	unsigned long flags;
	int active, count = 0;
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1062

1063 1064
	dev_dbg(port->dev, "%s(%d) active cookie %d\n", __func__, port->line,
		s->active_rx);
1065

1066
	spin_lock_irqsave(&port->lock, flags);
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1067

1068 1069 1070
	active = sci_dma_rx_find_active(s);
	if (active >= 0)
		count = sci_dma_rx_push(s, s->rx_buf[active], s->buf_len_rx);
P
Paul Mundt 已提交
1071

1072
	mod_timer(&s->rx_timer, jiffies + s->rx_timeout);
P
Paul Mundt 已提交
1073

1074 1075
	if (count)
		tty_flip_buffer_push(&port->state->port);
1076

1077 1078 1079 1080 1081 1082 1083 1084 1085 1086 1087 1088 1089 1090
	desc = dmaengine_prep_slave_sg(s->chan_rx, &s->sg_rx[active], 1,
				       DMA_DEV_TO_MEM,
				       DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
	if (!desc)
		goto fail;

	desc->callback = sci_dma_rx_complete;
	desc->callback_param = s;
	s->cookie_rx[active] = dmaengine_submit(desc);
	if (dma_submit_error(s->cookie_rx[active]))
		goto fail;

	s->active_rx = s->cookie_rx[!active];

1091 1092
	dma_async_issue_pending(chan);

1093
	spin_unlock_irqrestore(&port->lock, flags);
1094 1095 1096 1097 1098 1099 1100 1101
	dev_dbg(port->dev, "%s: cookie %d #%d, new active cookie %d\n",
		__func__, s->cookie_rx[active], active, s->active_rx);
	return;

fail:
	spin_unlock_irqrestore(&port->lock, flags);
	dev_warn(port->dev, "Failed submitting Rx DMA descriptor\n");
	sci_rx_dma_release(s, true);
L
Linus Torvalds 已提交
1102 1103
}

1104
static void sci_tx_dma_release(struct sci_port *s, bool enable_pio)
L
Linus Torvalds 已提交
1105
{
1106 1107
	struct dma_chan *chan = s->chan_tx;
	struct uart_port *port = &s->port;
1108
	unsigned long flags;
L
Linus Torvalds 已提交
1109

1110 1111 1112 1113 1114 1115 1116 1117 1118 1119 1120
	spin_lock_irqsave(&port->lock, flags);
	s->chan_tx = NULL;
	s->cookie_tx = -EINVAL;
	spin_unlock_irqrestore(&port->lock, flags);
	dmaengine_terminate_all(chan);
	dma_unmap_single(chan->device->dev, s->tx_dma_addr, UART_XMIT_SIZE,
			 DMA_TO_DEVICE);
	dma_release_channel(chan);
	if (enable_pio)
		sci_start_tx(port);
}
1121

1122 1123 1124 1125
static void sci_submit_rx(struct sci_port *s)
{
	struct dma_chan *chan = s->chan_rx;
	int i;
1126

1127 1128 1129
	for (i = 0; i < 2; i++) {
		struct scatterlist *sg = &s->sg_rx[i];
		struct dma_async_tx_descriptor *desc;
L
Linus Torvalds 已提交
1130

1131 1132 1133 1134 1135
		desc = dmaengine_prep_slave_sg(chan,
			sg, 1, DMA_DEV_TO_MEM,
			DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
		if (!desc)
			goto fail;
1136

1137 1138 1139 1140 1141
		desc->callback = sci_dma_rx_complete;
		desc->callback_param = s;
		s->cookie_rx[i] = dmaengine_submit(desc);
		if (dma_submit_error(s->cookie_rx[i]))
			goto fail;
1142

1143
	}
1144

1145
	s->active_rx = s->cookie_rx[0];
1146

1147 1148
	dma_async_issue_pending(chan);
	return;
1149

1150 1151 1152 1153 1154 1155 1156 1157
fail:
	if (i)
		dmaengine_terminate_all(chan);
	for (i = 0; i < 2; i++)
		s->cookie_rx[i] = -EINVAL;
	s->active_rx = -EINVAL;
	sci_rx_dma_release(s, true);
}
1158

1159
static void work_fn_tx(struct work_struct *work)
L
Linus Torvalds 已提交
1160
{
1161 1162 1163 1164 1165 1166
	struct sci_port *s = container_of(work, struct sci_port, work_tx);
	struct dma_async_tx_descriptor *desc;
	struct dma_chan *chan = s->chan_tx;
	struct uart_port *port = &s->port;
	struct circ_buf *xmit = &port->state->xmit;
	dma_addr_t buf;
L
Linus Torvalds 已提交
1167

1168
	/*
1169 1170 1171 1172 1173
	 * DMA is idle now.
	 * Port xmit buffer is already mapped, and it is one page... Just adjust
	 * offsets and lengths. Since it is a circular buffer, we have to
	 * transmit till the end, and then the rest. Take the port lock to get a
	 * consistent xmit buffer state.
1174
	 */
1175 1176 1177 1178 1179 1180
	spin_lock_irq(&port->lock);
	buf = s->tx_dma_addr + (xmit->tail & (UART_XMIT_SIZE - 1));
	s->tx_dma_len = min_t(unsigned int,
		CIRC_CNT(xmit->head, xmit->tail, UART_XMIT_SIZE),
		CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE));
	spin_unlock_irq(&port->lock);
1181

1182 1183 1184 1185 1186 1187 1188 1189 1190
	desc = dmaengine_prep_slave_single(chan, buf, s->tx_dma_len,
					   DMA_MEM_TO_DEV,
					   DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
	if (!desc) {
		dev_warn(port->dev, "Failed preparing Tx DMA descriptor\n");
		/* switch to PIO */
		sci_tx_dma_release(s, true);
		return;
	}
1191

1192 1193
	dma_sync_single_for_device(chan->device->dev, buf, s->tx_dma_len,
				   DMA_TO_DEVICE);
L
Linus Torvalds 已提交
1194

1195 1196 1197 1198 1199 1200 1201 1202 1203 1204
	spin_lock_irq(&port->lock);
	desc->callback = sci_dma_tx_complete;
	desc->callback_param = s;
	spin_unlock_irq(&port->lock);
	s->cookie_tx = dmaengine_submit(desc);
	if (dma_submit_error(s->cookie_tx)) {
		dev_warn(port->dev, "Failed submitting Tx DMA descriptor\n");
		/* switch to PIO */
		sci_tx_dma_release(s, true);
		return;
L
Linus Torvalds 已提交
1205 1206
	}

1207 1208
	dev_dbg(port->dev, "%s: %p: %d...%d, cookie %d\n",
		__func__, xmit->buf, xmit->tail, xmit->head, s->cookie_tx);
1209

1210
	dma_async_issue_pending(chan);
L
Linus Torvalds 已提交
1211 1212
}

1213
static void rx_timer_fn(unsigned long arg)
L
Linus Torvalds 已提交
1214
{
1215
	struct sci_port *s = (struct sci_port *)arg;
1216
	struct dma_chan *chan = s->chan_rx;
1217
	struct uart_port *port = &s->port;
1218 1219 1220 1221 1222 1223 1224 1225 1226
	struct dma_tx_state state;
	enum dma_status status;
	unsigned long flags;
	unsigned int read;
	int active, count;
	u16 scr;

	dev_dbg(port->dev, "DMA Rx timed out\n");

1227 1228
	spin_lock_irqsave(&port->lock, flags);

1229 1230 1231 1232 1233 1234 1235
	active = sci_dma_rx_find_active(s);
	if (active < 0) {
		spin_unlock_irqrestore(&port->lock, flags);
		return;
	}

	status = dmaengine_tx_status(s->chan_rx, s->active_rx, &state);
1236
	if (status == DMA_COMPLETE) {
1237
		spin_unlock_irqrestore(&port->lock, flags);
1238 1239
		dev_dbg(port->dev, "Cookie %d #%d has already completed\n",
			s->active_rx, active);
1240 1241 1242 1243

		/* Let packet complete handler take care of the packet */
		return;
	}
1244

1245 1246 1247 1248 1249 1250 1251 1252 1253 1254 1255 1256 1257 1258 1259
	dmaengine_pause(chan);

	/*
	 * sometimes DMA transfer doesn't stop even if it is stopped and
	 * data keeps on coming until transaction is complete so check
	 * for DMA_COMPLETE again
	 * Let packet complete handler take care of the packet
	 */
	status = dmaengine_tx_status(s->chan_rx, s->active_rx, &state);
	if (status == DMA_COMPLETE) {
		spin_unlock_irqrestore(&port->lock, flags);
		dev_dbg(port->dev, "Transaction complete after DMA engine was stopped");
		return;
	}

1260 1261 1262 1263 1264 1265 1266 1267 1268 1269
	/* Handle incomplete DMA receive */
	dmaengine_terminate_all(s->chan_rx);
	read = sg_dma_len(&s->sg_rx[active]) - state.residue;

	if (read) {
		count = sci_dma_rx_push(s, s->rx_buf[active], read);
		if (count)
			tty_flip_buffer_push(&port->state->port);
	}

1270 1271
	if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
		sci_submit_rx(s);
1272 1273 1274 1275 1276 1277 1278 1279 1280 1281

	/* Direct new serial port interrupts back to CPU */
	scr = serial_port_in(port, SCSCR);
	if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
		scr &= ~SCSCR_RDRQE;
		enable_irq(s->irqs[SCIx_RXI_IRQ]);
	}
	serial_port_out(port, SCSCR, scr | SCSCR_RIE);

	spin_unlock_irqrestore(&port->lock, flags);
L
Linus Torvalds 已提交
1282 1283
}

1284
static struct dma_chan *sci_request_dma_chan(struct uart_port *port,
1285
					     enum dma_transfer_direction dir)
1286 1287 1288 1289 1290
{
	struct dma_chan *chan;
	struct dma_slave_config cfg;
	int ret;

1291 1292
	chan = dma_request_slave_channel(port->dev,
					 dir == DMA_MEM_TO_DEV ? "tx" : "rx");
1293 1294 1295 1296 1297 1298 1299 1300 1301 1302 1303 1304 1305 1306 1307 1308 1309 1310 1311 1312 1313 1314 1315 1316 1317 1318 1319 1320
	if (!chan) {
		dev_warn(port->dev,
			 "dma_request_slave_channel_compat failed\n");
		return NULL;
	}

	memset(&cfg, 0, sizeof(cfg));
	cfg.direction = dir;
	if (dir == DMA_MEM_TO_DEV) {
		cfg.dst_addr = port->mapbase +
			(sci_getreg(port, SCxTDR)->offset << port->regshift);
		cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
	} else {
		cfg.src_addr = port->mapbase +
			(sci_getreg(port, SCxRDR)->offset << port->regshift);
		cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
	}

	ret = dmaengine_slave_config(chan, &cfg);
	if (ret) {
		dev_warn(port->dev, "dmaengine_slave_config failed %d\n", ret);
		dma_release_channel(chan);
		return NULL;
	}

	return chan;
}

1321
static void sci_request_dma(struct uart_port *port)
1322
{
1323 1324
	struct sci_port *s = to_sci_port(port);
	struct dma_chan *chan;
1325

1326
	dev_dbg(port->dev, "%s: port %d\n", __func__, port->line);
1327

1328
	if (!port->dev->of_node)
1329
		return;
1330

1331
	s->cookie_tx = -EINVAL;
1332
	chan = sci_request_dma_chan(port, DMA_MEM_TO_DEV);
1333 1334 1335 1336 1337 1338 1339 1340 1341 1342 1343 1344 1345 1346 1347 1348
	dev_dbg(port->dev, "%s: TX: got channel %p\n", __func__, chan);
	if (chan) {
		s->chan_tx = chan;
		/* UART circular tx buffer is an aligned page. */
		s->tx_dma_addr = dma_map_single(chan->device->dev,
						port->state->xmit.buf,
						UART_XMIT_SIZE,
						DMA_TO_DEVICE);
		if (dma_mapping_error(chan->device->dev, s->tx_dma_addr)) {
			dev_warn(port->dev, "Failed mapping Tx DMA descriptor\n");
			dma_release_channel(chan);
			s->chan_tx = NULL;
		} else {
			dev_dbg(port->dev, "%s: mapped %lu@%p to %pad\n",
				__func__, UART_XMIT_SIZE,
				port->state->xmit.buf, &s->tx_dma_addr);
1349
		}
1350 1351

		INIT_WORK(&s->work_tx, work_fn_tx);
1352 1353
	}

1354
	chan = sci_request_dma_chan(port, DMA_DEV_TO_MEM);
1355 1356 1357 1358 1359
	dev_dbg(port->dev, "%s: RX: got channel %p\n", __func__, chan);
	if (chan) {
		unsigned int i;
		dma_addr_t dma;
		void *buf;
1360

1361
		s->chan_rx = chan;
1362

1363 1364 1365 1366 1367 1368 1369 1370 1371 1372
		s->buf_len_rx = 2 * max_t(size_t, 16, port->fifosize);
		buf = dma_alloc_coherent(chan->device->dev, s->buf_len_rx * 2,
					 &dma, GFP_KERNEL);
		if (!buf) {
			dev_warn(port->dev,
				 "Failed to allocate Rx dma buffer, using PIO\n");
			dma_release_channel(chan);
			s->chan_rx = NULL;
			return;
		}
1373

1374 1375
		for (i = 0; i < 2; i++) {
			struct scatterlist *sg = &s->sg_rx[i];
1376

1377 1378 1379
			sg_init_table(sg, 1);
			s->rx_buf[i] = buf;
			sg_dma_address(sg) = dma;
1380
			sg_dma_len(sg) = s->buf_len_rx;
1381

1382 1383 1384 1385 1386 1387
			buf += s->buf_len_rx;
			dma += s->buf_len_rx;
		}

		setup_timer(&s->rx_timer, rx_timer_fn, (unsigned long)s);

1388 1389
		if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
			sci_submit_rx(s);
1390
	}
1391 1392
}

1393
static void sci_free_dma(struct uart_port *port)
1394
{
1395
	struct sci_port *s = to_sci_port(port);
1396

1397 1398 1399 1400 1401 1402 1403 1404 1405
	if (s->chan_tx)
		sci_tx_dma_release(s, false);
	if (s->chan_rx)
		sci_rx_dma_release(s, false);
}
#else
static inline void sci_request_dma(struct uart_port *port)
{
}
1406

1407 1408 1409 1410
static inline void sci_free_dma(struct uart_port *port)
{
}
#endif
1411

1412 1413 1414 1415 1416
static irqreturn_t sci_rx_interrupt(int irq, void *ptr)
{
#ifdef CONFIG_SERIAL_SH_SCI_DMA
	struct uart_port *port = ptr;
	struct sci_port *s = to_sci_port(port);
1417

1418 1419 1420
	if (s->chan_rx) {
		u16 scr = serial_port_in(port, SCSCR);
		u16 ssr = serial_port_in(port, SCxSR);
1421

1422 1423 1424 1425 1426 1427
		/* Disable future Rx interrupts */
		if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
			disable_irq_nosync(irq);
			scr |= SCSCR_RDRQE;
		} else {
			scr &= ~SCSCR_RIE;
1428
			sci_submit_rx(s);
1429 1430 1431 1432 1433 1434 1435 1436
		}
		serial_port_out(port, SCSCR, scr);
		/* Clear current interrupt */
		serial_port_out(port, SCxSR,
				ssr & ~(SCIF_DR | SCxSR_RDxF(port)));
		dev_dbg(port->dev, "Rx IRQ %lu: setup t-out in %u jiffies\n",
			jiffies, s->rx_timeout);
		mod_timer(&s->rx_timer, jiffies + s->rx_timeout);
1437

1438 1439 1440
		return IRQ_HANDLED;
	}
#endif
1441

1442 1443 1444 1445 1446 1447 1448
	/* I think sci_receive_chars has to be called irrespective
	 * of whether the I_IXOFF is set, otherwise, how is the interrupt
	 * to be disabled?
	 */
	sci_receive_chars(ptr);

	return IRQ_HANDLED;
1449 1450
}

1451
static irqreturn_t sci_tx_interrupt(int irq, void *ptr)
1452
{
1453
	struct uart_port *port = ptr;
1454
	unsigned long flags;
1455

1456
	spin_lock_irqsave(&port->lock, flags);
1457
	sci_transmit_chars(port);
1458
	spin_unlock_irqrestore(&port->lock, flags);
1459 1460

	return IRQ_HANDLED;
1461 1462
}

1463
static irqreturn_t sci_er_interrupt(int irq, void *ptr)
1464
{
1465 1466
	struct uart_port *port = ptr;
	struct sci_port *s = to_sci_port(port);
1467

1468 1469 1470 1471 1472 1473 1474 1475 1476 1477 1478 1479 1480 1481 1482 1483 1484 1485 1486 1487
	/* Handle errors */
	if (port->type == PORT_SCI) {
		if (sci_handle_errors(port)) {
			/* discard character in rx buffer */
			serial_port_in(port, SCxSR);
			sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
		}
	} else {
		sci_handle_fifo_overrun(port);
		if (!s->chan_rx)
			sci_receive_chars(ptr);
	}

	sci_clear_SCxSR(port, SCxSR_ERROR_CLEAR(port));

	/* Kick the transmission */
	if (!s->chan_tx)
		sci_tx_interrupt(irq, ptr);

	return IRQ_HANDLED;
1488 1489
}

1490
static irqreturn_t sci_br_interrupt(int irq, void *ptr)
1491
{
1492
	struct uart_port *port = ptr;
1493

1494 1495 1496
	/* Handle BREAKs */
	sci_handle_breaks(port);
	sci_clear_SCxSR(port, SCxSR_BREAK_CLEAR(port));
1497

1498 1499
	return IRQ_HANDLED;
}
1500

1501 1502 1503 1504 1505 1506
static irqreturn_t sci_mpxed_interrupt(int irq, void *ptr)
{
	unsigned short ssr_status, scr_status, err_enabled, orer_status = 0;
	struct uart_port *port = ptr;
	struct sci_port *s = to_sci_port(port);
	irqreturn_t ret = IRQ_NONE;
1507

1508 1509
	ssr_status = serial_port_in(port, SCxSR);
	scr_status = serial_port_in(port, SCSCR);
1510
	if (s->params->overrun_reg == SCxSR)
1511
		orer_status = ssr_status;
1512 1513
	else if (sci_getreg(port, s->params->overrun_reg)->size)
		orer_status = serial_port_in(port, s->params->overrun_reg);
1514

1515
	err_enabled = scr_status & port_rx_irq_mask(port);
1516

1517 1518 1519 1520
	/* Tx Interrupt */
	if ((ssr_status & SCxSR_TDxE(port)) && (scr_status & SCSCR_TIE) &&
	    !s->chan_tx)
		ret = sci_tx_interrupt(irq, ptr);
1521

1522 1523 1524 1525 1526 1527 1528
	/*
	 * Rx Interrupt: if we're using DMA, the DMA controller clears RDF /
	 * DR flags
	 */
	if (((ssr_status & SCxSR_RDxF(port)) || s->chan_rx) &&
	    (scr_status & SCSCR_RIE))
		ret = sci_rx_interrupt(irq, ptr);
1529

1530 1531 1532
	/* Error Interrupt */
	if ((ssr_status & SCxSR_ERRORS(port)) && err_enabled)
		ret = sci_er_interrupt(irq, ptr);
1533

1534 1535 1536 1537 1538
	/* Break Interrupt */
	if ((ssr_status & SCxSR_BRK(port)) && err_enabled)
		ret = sci_br_interrupt(irq, ptr);

	/* Overrun Interrupt */
1539
	if (orer_status & s->params->overrun_mask) {
1540 1541
		sci_handle_fifo_overrun(port);
		ret = IRQ_HANDLED;
1542 1543
	}

1544 1545
	return ret;
}
1546

1547 1548 1549 1550 1551 1552 1553 1554 1555 1556 1557
static const struct sci_irq_desc {
	const char	*desc;
	irq_handler_t	handler;
} sci_irq_desc[] = {
	/*
	 * Split out handlers, the default case.
	 */
	[SCIx_ERI_IRQ] = {
		.desc = "rx err",
		.handler = sci_er_interrupt,
	},
1558

1559 1560 1561 1562
	[SCIx_RXI_IRQ] = {
		.desc = "rx full",
		.handler = sci_rx_interrupt,
	},
1563

1564 1565 1566 1567
	[SCIx_TXI_IRQ] = {
		.desc = "tx empty",
		.handler = sci_tx_interrupt,
	},
1568

1569 1570 1571 1572
	[SCIx_BRI_IRQ] = {
		.desc = "break",
		.handler = sci_br_interrupt,
	},
1573 1574

	/*
1575
	 * Special muxed handler.
1576
	 */
1577 1578 1579 1580 1581
	[SCIx_MUX_IRQ] = {
		.desc = "mux",
		.handler = sci_mpxed_interrupt,
	},
};
1582

1583 1584 1585 1586
static int sci_request_irq(struct sci_port *port)
{
	struct uart_port *up = &port->port;
	int i, j, ret = 0;
1587

1588 1589 1590
	for (i = j = 0; i < SCIx_NR_IRQS; i++, j++) {
		const struct sci_irq_desc *desc;
		int irq;
1591

1592 1593 1594 1595 1596 1597 1598 1599 1600 1601 1602 1603 1604 1605 1606 1607 1608
		if (SCIx_IRQ_IS_MUXED(port)) {
			i = SCIx_MUX_IRQ;
			irq = up->irq;
		} else {
			irq = port->irqs[i];

			/*
			 * Certain port types won't support all of the
			 * available interrupt sources.
			 */
			if (unlikely(irq < 0))
				continue;
		}

		desc = sci_irq_desc + i;
		port->irqstr[j] = kasprintf(GFP_KERNEL, "%s:%s",
					    dev_name(up->dev), desc->desc);
1609 1610
		if (!port->irqstr[j]) {
			ret = -ENOMEM;
1611
			goto out_nomem;
1612
		}
1613 1614 1615 1616 1617 1618 1619

		ret = request_irq(irq, desc->handler, up->irqflags,
				  port->irqstr[j], port);
		if (unlikely(ret)) {
			dev_err(up->dev, "Can't allocate %s IRQ\n", desc->desc);
			goto out_noirq;
		}
1620 1621
	}

1622
	return 0;
L
Linus Torvalds 已提交
1623

1624 1625 1626
out_noirq:
	while (--i >= 0)
		free_irq(port->irqs[i], port);
P
Paul Mundt 已提交
1627

1628 1629 1630
out_nomem:
	while (--j >= 0)
		kfree(port->irqstr[j]);
P
Paul Mundt 已提交
1631

1632
	return ret;
L
Linus Torvalds 已提交
1633 1634
}

1635
static void sci_free_irq(struct sci_port *port)
L
Linus Torvalds 已提交
1636
{
1637
	int i;
L
Linus Torvalds 已提交
1638

1639 1640 1641 1642 1643 1644
	/*
	 * Intentionally in reverse order so we iterate over the muxed
	 * IRQ first.
	 */
	for (i = 0; i < SCIx_NR_IRQS; i++) {
		int irq = port->irqs[i];
P
Paul Mundt 已提交
1645

1646 1647 1648 1649 1650 1651
		/*
		 * Certain port types won't support all of the available
		 * interrupt sources.
		 */
		if (unlikely(irq < 0))
			continue;
P
Paul Mundt 已提交
1652

1653 1654
		free_irq(port->irqs[i], port);
		kfree(port->irqstr[i]);
P
Paul Mundt 已提交
1655

1656 1657 1658 1659 1660
		if (SCIx_IRQ_IS_MUXED(port)) {
			/* If there's only one IRQ, we're done. */
			return;
		}
	}
L
Linus Torvalds 已提交
1661 1662
}

1663
static unsigned int sci_tx_empty(struct uart_port *port)
L
Linus Torvalds 已提交
1664
{
1665 1666
	unsigned short status = serial_port_in(port, SCxSR);
	unsigned short in_tx_fifo = sci_txfill(port);
P
Paul Mundt 已提交
1667

1668
	return (status & SCxSR_TEND(port)) && !in_tx_fifo ? TIOCSER_TEMT : 0;
L
Linus Torvalds 已提交
1669 1670
}

1671 1672 1673 1674 1675 1676 1677 1678 1679 1680 1681 1682 1683 1684 1685 1686 1687 1688 1689 1690 1691 1692 1693 1694 1695 1696 1697 1698 1699 1700 1701 1702 1703 1704 1705 1706 1707 1708 1709 1710
static void sci_set_rts(struct uart_port *port, bool state)
{
	if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
		u16 data = serial_port_in(port, SCPDR);

		/* Active low */
		if (state)
			data &= ~SCPDR_RTSD;
		else
			data |= SCPDR_RTSD;
		serial_port_out(port, SCPDR, data);

		/* RTS# is output */
		serial_port_out(port, SCPCR,
				serial_port_in(port, SCPCR) | SCPCR_RTSC);
	} else if (sci_getreg(port, SCSPTR)->size) {
		u16 ctrl = serial_port_in(port, SCSPTR);

		/* Active low */
		if (state)
			ctrl &= ~SCSPTR_RTSDT;
		else
			ctrl |= SCSPTR_RTSDT;
		serial_port_out(port, SCSPTR, ctrl);
	}
}

static bool sci_get_cts(struct uart_port *port)
{
	if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
		/* Active low */
		return !(serial_port_in(port, SCPDR) & SCPDR_CTSD);
	} else if (sci_getreg(port, SCSPTR)->size) {
		/* Active low */
		return !(serial_port_in(port, SCSPTR) & SCSPTR_CTSDT);
	}

	return true;
}

1711 1712 1713 1714 1715 1716 1717 1718 1719 1720 1721 1722 1723
/*
 * Modem control is a bit of a mixed bag for SCI(F) ports. Generally
 * CTS/RTS is supported in hardware by at least one port and controlled
 * via SCSPTR (SCxPCR for SCIFA/B parts), or external pins (presently
 * handled via the ->init_pins() op, which is a bit of a one-way street,
 * lacking any ability to defer pin control -- this will later be
 * converted over to the GPIO framework).
 *
 * Other modes (such as loopback) are supported generically on certain
 * port types, but not others. For these it's sufficient to test for the
 * existence of the support register and simply ignore the port type.
 */
static void sci_set_mctrl(struct uart_port *port, unsigned int mctrl)
L
Linus Torvalds 已提交
1724
{
1725 1726
	struct sci_port *s = to_sci_port(port);

1727 1728
	if (mctrl & TIOCM_LOOP) {
		const struct plat_sci_reg *reg;
P
Paul Mundt 已提交
1729

1730 1731 1732 1733 1734 1735 1736 1737 1738
		/*
		 * Standard loopback mode for SCFCR ports.
		 */
		reg = sci_getreg(port, SCFCR);
		if (reg->size)
			serial_port_out(port, SCFCR,
					serial_port_in(port, SCFCR) |
					SCFCR_LOOP);
	}
1739 1740

	mctrl_gpio_set(s->gpios, mctrl);
1741

1742
	if (!s->has_rtscts)
1743 1744 1745 1746 1747 1748 1749 1750 1751 1752 1753 1754 1755 1756 1757 1758 1759 1760 1761 1762 1763 1764 1765
		return;

	if (!(mctrl & TIOCM_RTS)) {
		/* Disable Auto RTS */
		serial_port_out(port, SCFCR,
				serial_port_in(port, SCFCR) & ~SCFCR_MCE);

		/* Clear RTS */
		sci_set_rts(port, 0);
	} else if (s->autorts) {
		if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
			/* Enable RTS# pin function */
			serial_port_out(port, SCPCR,
				serial_port_in(port, SCPCR) & ~SCPCR_RTSC);
		}

		/* Enable Auto RTS */
		serial_port_out(port, SCFCR,
				serial_port_in(port, SCFCR) | SCFCR_MCE);
	} else {
		/* Set RTS */
		sci_set_rts(port, 1);
	}
1766
}
P
Paul Mundt 已提交
1767

1768 1769
static unsigned int sci_get_mctrl(struct uart_port *port)
{
1770 1771 1772 1773 1774 1775
	struct sci_port *s = to_sci_port(port);
	struct mctrl_gpios *gpios = s->gpios;
	unsigned int mctrl = 0;

	mctrl_gpio_get(gpios, &mctrl);

1776 1777
	/*
	 * CTS/RTS is handled in hardware when supported, while nothing
1778
	 * else is wired up.
1779
	 */
1780 1781 1782 1783
	if (s->autorts) {
		if (sci_get_cts(port))
			mctrl |= TIOCM_CTS;
	} else if (IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(gpios, UART_GPIO_CTS))) {
1784
		mctrl |= TIOCM_CTS;
1785
	}
1786 1787 1788 1789 1790 1791 1792 1793 1794 1795 1796
	if (IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(gpios, UART_GPIO_DSR)))
		mctrl |= TIOCM_DSR;
	if (IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(gpios, UART_GPIO_DCD)))
		mctrl |= TIOCM_CAR;

	return mctrl;
}

static void sci_enable_ms(struct uart_port *port)
{
	mctrl_gpio_enable_ms(to_sci_port(port)->gpios);
L
Linus Torvalds 已提交
1797 1798 1799 1800
}

static void sci_break_ctl(struct uart_port *port, int break_state)
{
1801 1802
	unsigned short scscr, scsptr;

1803
	/* check wheter the port has SCSPTR */
1804
	if (!sci_getreg(port, SCSPTR)->size) {
1805 1806 1807 1808
		/*
		 * Not supported by hardware. Most parts couple break and rx
		 * interrupts together, with break detection always enabled.
		 */
1809
		return;
1810
	}
1811 1812 1813 1814 1815 1816 1817 1818 1819 1820 1821 1822 1823 1824

	scsptr = serial_port_in(port, SCSPTR);
	scscr = serial_port_in(port, SCSCR);

	if (break_state == -1) {
		scsptr = (scsptr | SCSPTR_SPB2IO) & ~SCSPTR_SPB2DT;
		scscr &= ~SCSCR_TE;
	} else {
		scsptr = (scsptr | SCSPTR_SPB2DT) & ~SCSPTR_SPB2IO;
		scscr |= SCSCR_TE;
	}

	serial_port_out(port, SCSPTR, scsptr);
	serial_port_out(port, SCSCR, scscr);
L
Linus Torvalds 已提交
1825 1826 1827 1828
}

static int sci_startup(struct uart_port *port)
{
1829
	struct sci_port *s = to_sci_port(port);
1830
	int ret;
L
Linus Torvalds 已提交
1831

1832 1833
	dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);

1834 1835 1836 1837
	ret = sci_request_irq(s);
	if (unlikely(ret < 0))
		return ret;

1838
	sci_request_dma(port);
1839

L
Linus Torvalds 已提交
1840 1841 1842 1843 1844
	return 0;
}

static void sci_shutdown(struct uart_port *port)
{
1845
	struct sci_port *s = to_sci_port(port);
1846
	unsigned long flags;
1847
	u16 scr;
L
Linus Torvalds 已提交
1848

1849 1850
	dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);

1851
	s->autorts = false;
1852 1853
	mctrl_gpio_disable_ms(to_sci_port(port)->gpios);

1854
	spin_lock_irqsave(&port->lock, flags);
L
Linus Torvalds 已提交
1855
	sci_stop_rx(port);
1856
	sci_stop_tx(port);
1857 1858 1859
	/* Stop RX and TX, disable related interrupts, keep clock source */
	scr = serial_port_in(port, SCSCR);
	serial_port_out(port, SCSCR, scr & (SCSCR_CKE1 | SCSCR_CKE0));
1860
	spin_unlock_irqrestore(&port->lock, flags);
1861

1862 1863 1864 1865 1866 1867 1868 1869
#ifdef CONFIG_SERIAL_SH_SCI_DMA
	if (s->chan_rx) {
		dev_dbg(port->dev, "%s(%d) deleting rx_timer\n", __func__,
			port->line);
		del_timer_sync(&s->rx_timer);
	}
#endif

1870
	sci_free_dma(port);
L
Linus Torvalds 已提交
1871 1872 1873
	sci_free_irq(s);
}

1874 1875
static int sci_sck_calc(struct sci_port *s, unsigned int bps,
			unsigned int *srr)
1876
{
1877 1878
	unsigned long freq = s->clk_rates[SCI_SCK];
	int err, min_err = INT_MAX;
1879
	unsigned int sr;
1880

1881 1882
	if (s->port.type != PORT_HSCIF)
		freq *= 2;
1883

1884
	for_each_sr(sr, s) {
1885 1886 1887 1888 1889 1890
		err = DIV_ROUND_CLOSEST(freq, sr) - bps;
		if (abs(err) >= abs(min_err))
			continue;

		min_err = err;
		*srr = sr - 1;
1891

1892 1893 1894
		if (!err)
			break;
	}
1895

1896 1897 1898
	dev_dbg(s->port.dev, "SCK: %u%+d bps using SR %u\n", bps, min_err,
		*srr + 1);
	return min_err;
1899 1900
}

1901 1902 1903
static int sci_brg_calc(struct sci_port *s, unsigned int bps,
			unsigned long freq, unsigned int *dlr,
			unsigned int *srr)
1904
{
1905
	int err, min_err = INT_MAX;
1906
	unsigned int sr, dl;
1907

1908 1909
	if (s->port.type != PORT_HSCIF)
		freq *= 2;
1910

1911
	for_each_sr(sr, s) {
1912 1913 1914 1915 1916 1917 1918 1919 1920 1921 1922 1923 1924 1925
		dl = DIV_ROUND_CLOSEST(freq, sr * bps);
		dl = clamp(dl, 1U, 65535U);

		err = DIV_ROUND_CLOSEST(freq, sr * dl) - bps;
		if (abs(err) >= abs(min_err))
			continue;

		min_err = err;
		*dlr = dl;
		*srr = sr - 1;

		if (!err)
			break;
	}
1926

1927 1928 1929 1930
	dev_dbg(s->port.dev, "BRG: %u%+d bps using DL %u SR %u\n", bps,
		min_err, *dlr, *srr + 1);
	return min_err;
}
1931

1932
/* calculate sample rate, BRR, and clock select */
1933 1934 1935
static int sci_scbrr_calc(struct sci_port *s, unsigned int bps,
			  unsigned int *brr, unsigned int *srr,
			  unsigned int *cks)
U
Ulrich Hecht 已提交
1936
{
1937
	unsigned long freq = s->clk_rates[SCI_FCK];
1938
	unsigned int sr, br, prediv, scrate, c;
1939
	int err, min_err = INT_MAX;
U
Ulrich Hecht 已提交
1940

1941 1942
	if (s->port.type != PORT_HSCIF)
		freq *= 2;
1943

1944 1945 1946 1947 1948 1949 1950 1951 1952 1953 1954 1955 1956 1957 1958
	/*
	 * Find the combination of sample rate and clock select with the
	 * smallest deviation from the desired baud rate.
	 * Prefer high sample rates to maximise the receive margin.
	 *
	 * M: Receive margin (%)
	 * N: Ratio of bit rate to clock (N = sampling rate)
	 * D: Clock duty (D = 0 to 1.0)
	 * L: Frame length (L = 9 to 12)
	 * F: Absolute value of clock frequency deviation
	 *
	 *  M = |(0.5 - 1 / 2 * N) - ((L - 0.5) * F) -
	 *      (|D - 0.5| / N * (1 + F))|
	 *  NOTE: Usually, treat D for 0.5, F is 0 by this calculation.
	 */
1959
	for_each_sr(sr, s) {
U
Ulrich Hecht 已提交
1960 1961
		for (c = 0; c <= 3; c++) {
			/* integerized formulas from HSCIF documentation */
1962
			prediv = sr * (1 << (2 * c + 1));
1963 1964 1965 1966 1967

			/*
			 * We need to calculate:
			 *
			 *     br = freq / (prediv * bps) clamped to [1..256]
1968
			 *     err = freq / (br * prediv) - bps
1969
			 *
1970 1971
			 * Watch out for overflow when calculating the desired
			 * sampling clock rate!
1972
			 */
1973 1974 1975 1976 1977
			if (bps > UINT_MAX / prediv)
				break;

			scrate = prediv * bps;
			br = DIV_ROUND_CLOSEST(freq, scrate);
1978
			br = clamp(br, 1U, 256U);
1979

1980
			err = DIV_ROUND_CLOSEST(freq, br * prediv) - bps;
1981
			if (abs(err) >= abs(min_err))
1982 1983
				continue;

1984
			min_err = err;
1985
			*brr = br - 1;
1986 1987
			*srr = sr - 1;
			*cks = c;
1988 1989 1990

			if (!err)
				goto found;
U
Ulrich Hecht 已提交
1991 1992 1993
		}
	}

1994
found:
1995 1996
	dev_dbg(s->port.dev, "BRR: %u%+d bps using N %u SR %u cks %u\n", bps,
		min_err, *brr, *srr + 1, *cks);
1997
	return min_err;
U
Ulrich Hecht 已提交
1998 1999
}

2000 2001
static void sci_reset(struct uart_port *port)
{
2002
	const struct plat_sci_reg *reg;
2003 2004 2005
	unsigned int status;

	do {
2006
		status = serial_port_in(port, SCxSR);
2007 2008
	} while (!(status & SCxSR_TEND(port)));

2009
	serial_port_out(port, SCSCR, 0x00);	/* TE=0, RE=0, CKE1=0 */
2010

2011 2012
	reg = sci_getreg(port, SCFCR);
	if (reg->size)
2013
		serial_port_out(port, SCFCR, SCFCR_RFRST | SCFCR_TFRST);
2014 2015 2016 2017

	sci_clear_SCxSR(port,
			SCxSR_RDxF_CLEAR(port) & SCxSR_ERROR_CLEAR(port) &
			SCxSR_BREAK_CLEAR(port));
2018 2019 2020 2021 2022
	if (sci_getreg(port, SCLSR)->size) {
		status = serial_port_in(port, SCLSR);
		status &= ~(SCLSR_TO | SCLSR_ORER);
		serial_port_out(port, SCLSR, status);
	}
2023 2024
}

A
Alan Cox 已提交
2025 2026
static void sci_set_termios(struct uart_port *port, struct ktermios *termios,
			    struct ktermios *old)
L
Linus Torvalds 已提交
2027
{
2028
	unsigned int baud, smr_val = SCSMR_ASYNC, scr_val = 0, i;
2029 2030
	unsigned int brr = 255, cks = 0, srr = 15, dl = 0, sccks = 0;
	unsigned int brr1 = 255, cks1 = 0, srr1 = 15, dl1 = 0;
2031
	struct sci_port *s = to_sci_port(port);
2032
	const struct plat_sci_reg *reg;
2033 2034 2035
	int min_err = INT_MAX, err;
	unsigned long max_freq = 0;
	int best_clk = -1;
L
Linus Torvalds 已提交
2036

2037 2038 2039 2040 2041 2042 2043 2044 2045
	if ((termios->c_cflag & CSIZE) == CS7)
		smr_val |= SCSMR_CHR;
	if (termios->c_cflag & PARENB)
		smr_val |= SCSMR_PE;
	if (termios->c_cflag & PARODD)
		smr_val |= SCSMR_PE | SCSMR_ODD;
	if (termios->c_cflag & CSTOPB)
		smr_val |= SCSMR_STOP;

2046 2047 2048 2049 2050 2051 2052 2053
	/*
	 * earlyprintk comes here early on with port->uartclk set to zero.
	 * the clock framework is not up and running at this point so here
	 * we assume that 115200 is the maximum baud rate. please note that
	 * the baud rate is not programmed during earlyprintk - it is assumed
	 * that the previous boot loader has enabled required clocks and
	 * setup the baud rate generator hardware for us already.
	 */
2054 2055 2056 2057
	if (!port->uartclk) {
		baud = uart_get_baud_rate(port, termios, old, 0, 115200);
		goto done;
	}
L
Linus Torvalds 已提交
2058

2059 2060 2061
	for (i = 0; i < SCI_NUM_CLKS; i++)
		max_freq = max(max_freq, s->clk_rates[i]);

2062
	baud = uart_get_baud_rate(port, termios, old, 0, max_freq / min_sr(s));
2063 2064 2065 2066 2067 2068 2069 2070
	if (!baud)
		goto done;

	/*
	 * There can be multiple sources for the sampling clock.  Find the one
	 * that gives us the smallest deviation from the desired baud rate.
	 */

2071 2072 2073 2074 2075 2076 2077 2078 2079 2080 2081 2082 2083 2084 2085
	/* Optional Undivided External Clock */
	if (s->clk_rates[SCI_SCK] && port->type != PORT_SCIFA &&
	    port->type != PORT_SCIFB) {
		err = sci_sck_calc(s, baud, &srr1);
		if (abs(err) < abs(min_err)) {
			best_clk = SCI_SCK;
			scr_val = SCSCR_CKE1;
			sccks = SCCKS_CKS;
			min_err = err;
			srr = srr1;
			if (!err)
				goto done;
		}
	}

2086 2087 2088 2089 2090 2091 2092 2093 2094 2095 2096 2097 2098 2099 2100 2101 2102 2103 2104 2105 2106 2107 2108 2109 2110 2111 2112 2113 2114
	/* Optional BRG Frequency Divided External Clock */
	if (s->clk_rates[SCI_SCIF_CLK] && sci_getreg(port, SCDL)->size) {
		err = sci_brg_calc(s, baud, s->clk_rates[SCI_SCIF_CLK], &dl1,
				   &srr1);
		if (abs(err) < abs(min_err)) {
			best_clk = SCI_SCIF_CLK;
			scr_val = SCSCR_CKE1;
			sccks = 0;
			min_err = err;
			dl = dl1;
			srr = srr1;
			if (!err)
				goto done;
		}
	}

	/* Optional BRG Frequency Divided Internal Clock */
	if (s->clk_rates[SCI_BRG_INT] && sci_getreg(port, SCDL)->size) {
		err = sci_brg_calc(s, baud, s->clk_rates[SCI_BRG_INT], &dl1,
				   &srr1);
		if (abs(err) < abs(min_err)) {
			best_clk = SCI_BRG_INT;
			scr_val = SCSCR_CKE1;
			sccks = SCCKS_XIN;
			min_err = err;
			dl = dl1;
			srr = srr1;
			if (!min_err)
				goto done;
U
Ulrich Hecht 已提交
2115 2116
		}
	}
2117

2118 2119 2120 2121
	/* Divided Functional Clock using standard Bit Rate Register */
	err = sci_scbrr_calc(s, baud, &brr1, &srr1, &cks1);
	if (abs(err) < abs(min_err)) {
		best_clk = SCI_FCK;
2122
		scr_val = 0;
2123 2124 2125 2126 2127 2128 2129 2130 2131 2132
		min_err = err;
		brr = brr1;
		srr = srr1;
		cks = cks1;
	}

done:
	if (best_clk >= 0)
		dev_dbg(port->dev, "Using clk %pC for %u%+d bps\n",
			s->clks[best_clk], baud, min_err);
2133

2134
	sci_port_enable(s);
2135

2136 2137 2138 2139
	/*
	 * Program the optional External Baud Rate Generator (BRG) first.
	 * It controls the mux to select (H)SCK or frequency divided clock.
	 */
2140 2141
	if (best_clk >= 0 && sci_getreg(port, SCCKS)->size) {
		serial_port_out(port, SCDL, dl);
2142
		serial_port_out(port, SCCKS, sccks);
2143
	}
L
Linus Torvalds 已提交
2144

2145
	sci_reset(port);
L
Linus Torvalds 已提交
2146 2147 2148

	uart_update_timeout(port, termios->c_cflag, baud);

2149
	if (best_clk >= 0) {
2150 2151 2152 2153 2154 2155 2156 2157 2158 2159 2160
		if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
			switch (srr + 1) {
			case 5:  smr_val |= SCSMR_SRC_5;  break;
			case 7:  smr_val |= SCSMR_SRC_7;  break;
			case 11: smr_val |= SCSMR_SRC_11; break;
			case 13: smr_val |= SCSMR_SRC_13; break;
			case 16: smr_val |= SCSMR_SRC_16; break;
			case 17: smr_val |= SCSMR_SRC_17; break;
			case 19: smr_val |= SCSMR_SRC_19; break;
			case 27: smr_val |= SCSMR_SRC_27; break;
			}
2161
		smr_val |= cks;
2162
		dev_dbg(port->dev,
2163 2164
			 "SCR 0x%x SMR 0x%x BRR %u CKS 0x%x DL %u SRR %u\n",
			 scr_val, smr_val, brr, sccks, dl, srr);
2165
		serial_port_out(port, SCSCR, scr_val);
2166 2167 2168
		serial_port_out(port, SCSMR, smr_val);
		serial_port_out(port, SCBRR, brr);
		if (sci_getreg(port, HSSRR)->size)
U
Ulrich Hecht 已提交
2169
			serial_port_out(port, HSSRR, srr | HSCIF_SRE);
2170 2171 2172 2173 2174 2175

		/* Wait one bit interval */
		udelay((1000000 + (baud - 1)) / baud);
	} else {
		/* Don't touch the bit rate configuration */
		scr_val = s->cfg->scscr & (SCSCR_CKE1 | SCSCR_CKE0);
2176 2177
		smr_val |= serial_port_in(port, SCSMR) &
			   (SCSMR_CKEDG | SCSMR_SRC_MASK | SCSMR_CKS);
2178 2179
		dev_dbg(port->dev, "SCR 0x%x SMR 0x%x\n", scr_val, smr_val);
		serial_port_out(port, SCSCR, scr_val);
2180
		serial_port_out(port, SCSMR, smr_val);
2181
	}
L
Linus Torvalds 已提交
2182

2183
	sci_init_pins(port, termios->c_cflag);
2184

2185 2186
	port->status &= ~UPSTAT_AUTOCTS;
	s->autorts = false;
2187 2188
	reg = sci_getreg(port, SCFCR);
	if (reg->size) {
2189
		unsigned short ctrl = serial_port_in(port, SCFCR);
2190

2191 2192 2193 2194 2195 2196
		if ((port->flags & UPF_HARD_FLOW) &&
		    (termios->c_cflag & CRTSCTS)) {
			/* There is no CTS interrupt to restart the hardware */
			port->status |= UPSTAT_AUTOCTS;
			/* MCE is enabled when RTS is raised */
			s->autorts = true;
2197
		}
2198 2199 2200 2201 2202 2203 2204 2205

		/*
		 * As we've done a sci_reset() above, ensure we don't
		 * interfere with the FIFOs while toggling MCE. As the
		 * reset values could still be set, simply mask them out.
		 */
		ctrl &= ~(SCFCR_RFRST | SCFCR_TFRST);

2206
		serial_port_out(port, SCFCR, ctrl);
2207
	}
2208

2209 2210
	scr_val |= SCSCR_RE | SCSCR_TE |
		   (s->cfg->scscr & ~(SCSCR_CKE1 | SCSCR_CKE0));
2211 2212
	dev_dbg(port->dev, "SCSCR 0x%x\n", scr_val);
	serial_port_out(port, SCSCR, scr_val);
2213 2214 2215 2216 2217 2218 2219 2220 2221 2222
	if ((srr + 1 == 5) &&
	    (port->type == PORT_SCIFA || port->type == PORT_SCIFB)) {
		/*
		 * In asynchronous mode, when the sampling rate is 1/5, first
		 * received data may become invalid on some SCIFA and SCIFB.
		 * To avoid this problem wait more than 1 serial data time (1
		 * bit time x serial data number) after setting SCSCR.RE = 1.
		 */
		udelay(DIV_ROUND_UP(10 * 1000000, baud));
	}
L
Linus Torvalds 已提交
2223

2224 2225
#ifdef CONFIG_SERIAL_SH_SCI_DMA
	/*
2226
	 * Calculate delay for 2 DMA buffers (4 FIFO).
2227 2228 2229 2230 2231 2232 2233
	 * See serial_core.c::uart_update_timeout().
	 * With 10 bits (CS8), 250Hz, 115200 baud and 64 bytes FIFO, the above
	 * function calculates 1 jiffie for the data plus 5 jiffies for the
	 * "slop(e)." Then below we calculate 5 jiffies (20ms) for 2 DMA
	 * buffers (4 FIFO sizes), but when performing a faster transfer, the
	 * value obtained by this formula is too small. Therefore, if the value
	 * is smaller than 20ms, use 20ms as the timeout value for DMA.
2234 2235
	 */
	if (s->chan_rx) {
2236 2237 2238 2239 2240 2241 2242 2243 2244 2245 2246 2247 2248 2249 2250 2251 2252 2253 2254 2255 2256 2257 2258 2259
		unsigned int bits;

		/* byte size and parity */
		switch (termios->c_cflag & CSIZE) {
		case CS5:
			bits = 7;
			break;
		case CS6:
			bits = 8;
			break;
		case CS7:
			bits = 9;
			break;
		default:
			bits = 10;
			break;
		}

		if (termios->c_cflag & CSTOPB)
			bits++;
		if (termios->c_cflag & PARENB)
			bits++;
		s->rx_timeout = DIV_ROUND_UP((s->buf_len_rx * 2 * bits * HZ) /
					     (baud / 10), 10);
2260
		dev_dbg(port->dev, "DMA Rx t-out %ums, tty t-out %u jiffies\n",
2261 2262 2263 2264 2265 2266
			s->rx_timeout * 1000 / HZ, port->timeout);
		if (s->rx_timeout < msecs_to_jiffies(20))
			s->rx_timeout = msecs_to_jiffies(20);
	}
#endif

L
Linus Torvalds 已提交
2267
	if ((termios->c_cflag & CREAD) != 0)
2268
		sci_start_rx(port);
2269

2270
	sci_port_disable(s);
2271 2272 2273

	if (UART_ENABLE_MS(port, termios->c_cflag))
		sci_enable_ms(port);
L
Linus Torvalds 已提交
2274 2275
}

2276 2277 2278 2279 2280 2281
static void sci_pm(struct uart_port *port, unsigned int state,
		   unsigned int oldstate)
{
	struct sci_port *sci_port = to_sci_port(port);

	switch (state) {
2282
	case UART_PM_STATE_OFF:
2283 2284 2285 2286 2287 2288 2289 2290
		sci_port_disable(sci_port);
		break;
	default:
		sci_port_enable(sci_port);
		break;
	}
}

L
Linus Torvalds 已提交
2291 2292 2293
static const char *sci_type(struct uart_port *port)
{
	switch (port->type) {
2294 2295 2296 2297 2298 2299 2300 2301
	case PORT_IRDA:
		return "irda";
	case PORT_SCI:
		return "sci";
	case PORT_SCIF:
		return "scif";
	case PORT_SCIFA:
		return "scifa";
2302 2303
	case PORT_SCIFB:
		return "scifb";
U
Ulrich Hecht 已提交
2304 2305
	case PORT_HSCIF:
		return "hscif";
L
Linus Torvalds 已提交
2306 2307
	}

P
Paul Mundt 已提交
2308
	return NULL;
L
Linus Torvalds 已提交
2309 2310
}

2311 2312
static int sci_remap_port(struct uart_port *port)
{
2313
	struct sci_port *sport = to_sci_port(port);
2314 2315 2316 2317 2318 2319 2320

	/*
	 * Nothing to do if there's already an established membase.
	 */
	if (port->membase)
		return 0;

2321
	if (port->dev->of_node || (port->flags & UPF_IOREMAP)) {
2322
		port->membase = ioremap_nocache(port->mapbase, sport->reg_size);
2323 2324 2325 2326 2327 2328 2329 2330 2331 2332
		if (unlikely(!port->membase)) {
			dev_err(port->dev, "can't remap port#%d\n", port->line);
			return -ENXIO;
		}
	} else {
		/*
		 * For the simple (and majority of) cases where we don't
		 * need to do any remapping, just cast the cookie
		 * directly.
		 */
J
Jingoo Han 已提交
2333
		port->membase = (void __iomem *)(uintptr_t)port->mapbase;
2334 2335 2336 2337 2338
	}

	return 0;
}

2339
static void sci_release_port(struct uart_port *port)
L
Linus Torvalds 已提交
2340
{
2341 2342
	struct sci_port *sport = to_sci_port(port);

2343
	if (port->dev->of_node || (port->flags & UPF_IOREMAP)) {
2344 2345 2346 2347
		iounmap(port->membase);
		port->membase = NULL;
	}

2348
	release_mem_region(port->mapbase, sport->reg_size);
L
Linus Torvalds 已提交
2349 2350
}

2351
static int sci_request_port(struct uart_port *port)
L
Linus Torvalds 已提交
2352
{
2353
	struct resource *res;
2354
	struct sci_port *sport = to_sci_port(port);
2355
	int ret;
L
Linus Torvalds 已提交
2356

2357 2358 2359 2360
	res = request_mem_region(port->mapbase, sport->reg_size,
				 dev_name(port->dev));
	if (unlikely(res == NULL)) {
		dev_err(port->dev, "request_mem_region failed.");
2361
		return -EBUSY;
2362
	}
L
Linus Torvalds 已提交
2363

2364 2365 2366 2367
	ret = sci_remap_port(port);
	if (unlikely(ret != 0)) {
		release_resource(res);
		return ret;
2368
	}
2369 2370 2371 2372 2373 2374 2375 2376 2377 2378 2379 2380

	return 0;
}

static void sci_config_port(struct uart_port *port, int flags)
{
	if (flags & UART_CONFIG_TYPE) {
		struct sci_port *sport = to_sci_port(port);

		port->type = sport->cfg->type;
		sci_request_port(port);
	}
L
Linus Torvalds 已提交
2381 2382 2383 2384 2385 2386 2387 2388 2389 2390 2391
}

static int sci_verify_port(struct uart_port *port, struct serial_struct *ser)
{
	if (ser->baud_base < 2400)
		/* No paper tape reader for Mitch.. */
		return -EINVAL;

	return 0;
}

2392
static const struct uart_ops sci_uart_ops = {
L
Linus Torvalds 已提交
2393 2394 2395 2396 2397 2398
	.tx_empty	= sci_tx_empty,
	.set_mctrl	= sci_set_mctrl,
	.get_mctrl	= sci_get_mctrl,
	.start_tx	= sci_start_tx,
	.stop_tx	= sci_stop_tx,
	.stop_rx	= sci_stop_rx,
2399
	.enable_ms	= sci_enable_ms,
L
Linus Torvalds 已提交
2400 2401 2402 2403
	.break_ctl	= sci_break_ctl,
	.startup	= sci_startup,
	.shutdown	= sci_shutdown,
	.set_termios	= sci_set_termios,
2404
	.pm		= sci_pm,
L
Linus Torvalds 已提交
2405 2406 2407 2408 2409
	.type		= sci_type,
	.release_port	= sci_release_port,
	.request_port	= sci_request_port,
	.config_port	= sci_config_port,
	.verify_port	= sci_verify_port,
2410 2411 2412 2413
#ifdef CONFIG_CONSOLE_POLL
	.poll_get_char	= sci_poll_get_char,
	.poll_put_char	= sci_poll_put_char,
#endif
L
Linus Torvalds 已提交
2414 2415
};

2416 2417
static int sci_init_clocks(struct sci_port *sci_port, struct device *dev)
{
2418 2419
	const char *clk_names[] = {
		[SCI_FCK] = "fck",
2420
		[SCI_SCK] = "sck",
2421 2422
		[SCI_BRG_INT] = "brg_int",
		[SCI_SCIF_CLK] = "scif_clk",
2423 2424 2425
	};
	struct clk *clk;
	unsigned int i;
2426

2427 2428 2429
	if (sci_port->cfg->type == PORT_HSCIF)
		clk_names[SCI_SCK] = "hsck";

2430 2431 2432 2433
	for (i = 0; i < SCI_NUM_CLKS; i++) {
		clk = devm_clk_get(dev, clk_names[i]);
		if (PTR_ERR(clk) == -EPROBE_DEFER)
			return -EPROBE_DEFER;
2434

2435 2436 2437 2438 2439 2440 2441 2442
		if (IS_ERR(clk) && i == SCI_FCK) {
			/*
			 * "fck" used to be called "sci_ick", and we need to
			 * maintain DT backward compatibility.
			 */
			clk = devm_clk_get(dev, "sci_ick");
			if (PTR_ERR(clk) == -EPROBE_DEFER)
				return -EPROBE_DEFER;
2443

2444 2445
			if (!IS_ERR(clk))
				goto found;
2446

2447 2448 2449 2450 2451 2452 2453 2454 2455 2456 2457 2458 2459 2460 2461 2462 2463 2464 2465 2466 2467 2468 2469 2470
			/*
			 * Not all SH platforms declare a clock lookup entry
			 * for SCI devices, in which case we need to get the
			 * global "peripheral_clk" clock.
			 */
			clk = devm_clk_get(dev, "peripheral_clk");
			if (!IS_ERR(clk))
				goto found;

			dev_err(dev, "failed to get %s (%ld)\n", clk_names[i],
				PTR_ERR(clk));
			return PTR_ERR(clk);
		}

found:
		if (IS_ERR(clk))
			dev_dbg(dev, "failed to get %s (%ld)\n", clk_names[i],
				PTR_ERR(clk));
		else
			dev_dbg(dev, "clk %s is %pC rate %pCr\n", clk_names[i],
				clk, clk);
		sci_port->clks[i] = IS_ERR(clk) ? NULL : clk;
	}
	return 0;
2471 2472
}

2473 2474 2475 2476 2477 2478 2479 2480 2481 2482 2483 2484 2485 2486 2487 2488 2489 2490 2491 2492 2493 2494 2495 2496 2497 2498 2499 2500 2501 2502 2503 2504 2505 2506 2507 2508 2509 2510 2511 2512 2513
static const struct sci_port_params *
sci_probe_regmap(const struct plat_sci_port *cfg)
{
	unsigned int regtype;

	if (cfg->regtype != SCIx_PROBE_REGTYPE)
		return &sci_port_params[cfg->regtype];

	switch (cfg->type) {
	case PORT_SCI:
		regtype = SCIx_SCI_REGTYPE;
		break;
	case PORT_IRDA:
		regtype = SCIx_IRDA_REGTYPE;
		break;
	case PORT_SCIFA:
		regtype = SCIx_SCIFA_REGTYPE;
		break;
	case PORT_SCIFB:
		regtype = SCIx_SCIFB_REGTYPE;
		break;
	case PORT_SCIF:
		/*
		 * The SH-4 is a bit of a misnomer here, although that's
		 * where this particular port layout originated. This
		 * configuration (or some slight variation thereof)
		 * remains the dominant model for all SCIFs.
		 */
		regtype = SCIx_SH4_SCIF_REGTYPE;
		break;
	case PORT_HSCIF:
		regtype = SCIx_HSCIF_REGTYPE;
		break;
	default:
		pr_err("Can't probe register map for given port\n");
		return NULL;
	}

	return &sci_port_params[regtype];
}

B
Bill Pemberton 已提交
2514
static int sci_init_single(struct platform_device *dev,
2515
			   struct sci_port *sci_port, unsigned int index,
2516
			   const struct plat_sci_port *p, bool early)
2517
{
2518
	struct uart_port *port = &sci_port->port;
2519 2520
	const struct resource *res;
	unsigned int i;
2521
	int ret;
2522

2523 2524
	sci_port->cfg	= p;

2525 2526 2527
	port->ops	= &sci_uart_ops;
	port->iotype	= UPIO_MEM;
	port->line	= index;
2528

2529 2530 2531
	res = platform_get_resource(dev, IORESOURCE_MEM, 0);
	if (res == NULL)
		return -ENOMEM;
2532

2533
	port->mapbase = res->start;
2534
	sci_port->reg_size = resource_size(res);
2535

2536 2537
	for (i = 0; i < ARRAY_SIZE(sci_port->irqs); ++i)
		sci_port->irqs[i] = platform_get_irq(dev, i);
2538

2539 2540 2541 2542 2543 2544 2545
	/* The SCI generates several interrupts. They can be muxed together or
	 * connected to different interrupt lines. In the muxed case only one
	 * interrupt resource is specified. In the non-muxed case three or four
	 * interrupt resources are specified, as the BRI interrupt is optional.
	 */
	if (sci_port->irqs[0] < 0)
		return -ENXIO;
2546

2547 2548 2549 2550
	if (sci_port->irqs[1] < 0) {
		sci_port->irqs[1] = sci_port->irqs[0];
		sci_port->irqs[2] = sci_port->irqs[0];
		sci_port->irqs[3] = sci_port->irqs[0];
2551 2552
	}

2553 2554 2555
	sci_port->params = sci_probe_regmap(p);
	if (unlikely(sci_port->params == NULL))
		return -EINVAL;
2556

2557 2558 2559
	/* SCIFA on sh7723 and sh7724 need a custom sampling rate that doesn't
	 * match the SoC datasheet, this should be investigated. Let platform
	 * data override the sampling rate for now.
2560
	 */
2561 2562 2563
	sci_port->sampling_rate_mask = p->sampling_rate
				     ? SCI_SR(p->sampling_rate)
				     : sci_port->params->sampling_rate_mask;
2564

2565
	if (!early) {
2566 2567 2568
		ret = sci_init_clocks(sci_port, &dev->dev);
		if (ret < 0)
			return ret;
2569

2570
		port->dev = &dev->dev;
M
Magnus Damm 已提交
2571 2572

		pm_runtime_enable(&dev->dev);
2573
	}
2574

2575
	port->type		= p->type;
2576
	port->flags		= UPF_FIXED_PORT | UPF_BOOT_AUTOCONF | p->flags;
2577
	port->fifosize		= sci_port->params->fifosize;
2578

2579 2580 2581 2582 2583 2584 2585
	if (port->type == PORT_SCI) {
		if (sci_port->reg_size >= 0x20)
			port->regshift = 2;
		else
			port->regshift = 1;
	}

2586
	/*
2587
	 * The UART port needs an IRQ value, so we peg this to the RX IRQ
2588 2589 2590 2591 2592
	 * for the multi-IRQ ports, which is where we are primarily
	 * concerned with the shutdown path synchronization.
	 *
	 * For the muxed case there's nothing more to do.
	 */
2593
	port->irq		= sci_port->irqs[SCIx_RXI_IRQ];
Y
Yong Zhang 已提交
2594
	port->irqflags		= 0;
2595

2596 2597 2598
	port->serial_in		= sci_serial_in;
	port->serial_out	= sci_serial_out;

2599
	return 0;
2600 2601
}

2602 2603 2604 2605 2606
static void sci_cleanup_single(struct sci_port *port)
{
	pm_runtime_disable(port->port.dev);
}

2607 2608
#if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) || \
    defined(CONFIG_SERIAL_SH_SCI_EARLYCON)
2609 2610 2611 2612 2613
static void serial_console_putchar(struct uart_port *port, int ch)
{
	sci_poll_put_char(port, ch);
}

L
Linus Torvalds 已提交
2614 2615 2616 2617 2618 2619 2620
/*
 *	Print a string to the serial port trying not to disturb
 *	any possible real use of the port...
 */
static void serial_console_write(struct console *co, const char *s,
				 unsigned count)
{
2621 2622
	struct sci_port *sci_port = &sci_ports[co->index];
	struct uart_port *port = &sci_port->port;
2623
	unsigned short bits, ctrl, ctrl_temp;
2624 2625 2626 2627
	unsigned long flags;
	int locked = 1;

	local_irq_save(flags);
2628
#if defined(SUPPORT_SYSRQ)
2629 2630
	if (port->sysrq)
		locked = 0;
2631 2632 2633
	else
#endif
	if (oops_in_progress)
2634 2635 2636 2637
		locked = spin_trylock(&port->lock);
	else
		spin_lock(&port->lock);

2638
	/* first save SCSCR then disable interrupts, keep clock source */
2639
	ctrl = serial_port_in(port, SCSCR);
2640 2641
	ctrl_temp = SCSCR_RE | SCSCR_TE |
		    (sci_port->cfg->scscr & ~(SCSCR_CKE1 | SCSCR_CKE0)) |
2642 2643
		    (ctrl & (SCSCR_CKE1 | SCSCR_CKE0));
	serial_port_out(port, SCSCR, ctrl_temp);
2644

2645
	uart_console_write(port, s, count, serial_console_putchar);
M
Magnus Damm 已提交
2646 2647 2648

	/* wait until fifo is empty and last bit has been transmitted */
	bits = SCxSR_TDxE(port) | SCxSR_TEND(port);
2649
	while ((serial_port_in(port, SCxSR) & bits) != bits)
M
Magnus Damm 已提交
2650
		cpu_relax();
2651 2652 2653 2654 2655 2656 2657

	/* restore the SCSCR */
	serial_port_out(port, SCSCR, ctrl);

	if (locked)
		spin_unlock(&port->lock);
	local_irq_restore(flags);
L
Linus Torvalds 已提交
2658 2659
}

B
Bill Pemberton 已提交
2660
static int serial_console_setup(struct console *co, char *options)
L
Linus Torvalds 已提交
2661
{
2662
	struct sci_port *sci_port;
L
Linus Torvalds 已提交
2663 2664 2665 2666 2667 2668 2669
	struct uart_port *port;
	int baud = 115200;
	int bits = 8;
	int parity = 'n';
	int flow = 'n';
	int ret;

2670
	/*
2671
	 * Refuse to handle any bogus ports.
L
Linus Torvalds 已提交
2672
	 */
2673
	if (co->index < 0 || co->index >= SCI_NPORTS)
2674 2675
		return -ENODEV;

2676 2677 2678
	sci_port = &sci_ports[co->index];
	port = &sci_port->port;

2679 2680 2681 2682 2683 2684
	/*
	 * Refuse to handle uninitialized ports.
	 */
	if (!port->ops)
		return -ENODEV;

2685 2686 2687
	ret = sci_remap_port(port);
	if (unlikely(ret != 0))
		return ret;
2688

L
Linus Torvalds 已提交
2689 2690 2691
	if (options)
		uart_parse_options(options, &baud, &parity, &bits, &flow);

2692
	return uart_set_options(port, co, baud, parity, bits, flow);
L
Linus Torvalds 已提交
2693 2694 2695 2696
}

static struct console serial_console = {
	.name		= "ttySC",
2697
	.device		= uart_console_device,
L
Linus Torvalds 已提交
2698 2699
	.write		= serial_console_write,
	.setup		= serial_console_setup,
P
Paul Mundt 已提交
2700
	.flags		= CON_PRINTBUFFER,
L
Linus Torvalds 已提交
2701
	.index		= -1,
2702
	.data		= &sci_uart_driver,
L
Linus Torvalds 已提交
2703 2704
};

2705 2706 2707 2708
static struct console early_serial_console = {
	.name           = "early_ttySC",
	.write          = serial_console_write,
	.flags          = CON_PRINTBUFFER,
2709
	.index		= -1,
2710
};
2711

2712 2713
static char early_serial_buf[32];

B
Bill Pemberton 已提交
2714
static int sci_probe_earlyprintk(struct platform_device *pdev)
2715
{
2716
	const struct plat_sci_port *cfg = dev_get_platdata(&pdev->dev);
2717 2718 2719 2720 2721 2722

	if (early_serial_console.data)
		return -EEXIST;

	early_serial_console.index = pdev->id;

2723
	sci_init_single(pdev, &sci_ports[pdev->id], pdev->id, cfg, true);
2724 2725 2726 2727 2728 2729 2730 2731 2732

	serial_console_setup(&early_serial_console, early_serial_buf);

	if (!strstr(early_serial_buf, "keep"))
		early_serial_console.flags |= CON_BOOT;

	register_console(&early_serial_console);
	return 0;
}
2733 2734 2735

#define SCI_CONSOLE	(&serial_console)

2736
#else
B
Bill Pemberton 已提交
2737
static inline int sci_probe_earlyprintk(struct platform_device *pdev)
2738 2739 2740
{
	return -EINVAL;
}
L
Linus Torvalds 已提交
2741

2742 2743
#define SCI_CONSOLE	NULL

2744
#endif /* CONFIG_SERIAL_SH_SCI_CONSOLE || CONFIG_SERIAL_SH_SCI_EARLYCON */
L
Linus Torvalds 已提交
2745

2746
static const char banner[] __initconst = "SuperH (H)SCI(F) driver initialized";
L
Linus Torvalds 已提交
2747 2748 2749 2750 2751 2752 2753

static struct uart_driver sci_uart_driver = {
	.owner		= THIS_MODULE,
	.driver_name	= "sci",
	.dev_name	= "ttySC",
	.major		= SCI_MAJOR,
	.minor		= SCI_MINOR_START,
2754
	.nr		= SCI_NPORTS,
L
Linus Torvalds 已提交
2755 2756 2757
	.cons		= SCI_CONSOLE,
};

2758
static int sci_remove(struct platform_device *dev)
2759
{
2760
	struct sci_port *port = platform_get_drvdata(dev);
2761

2762 2763
	uart_remove_one_port(&sci_uart_driver, &port->port);

2764
	sci_cleanup_single(port);
2765 2766 2767 2768

	return 0;
}

2769 2770 2771 2772

#define SCI_OF_DATA(type, regtype)	(void *)((type) << 16 | (regtype))
#define SCI_OF_TYPE(data)		((unsigned long)(data) >> 16)
#define SCI_OF_REGTYPE(data)		((unsigned long)(data) & 0xffff)
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Bastian Hecht 已提交
2773 2774

static const struct of_device_id of_sci_match[] = {
2775 2776 2777 2778 2779
	/* SoC-specific types */
	{
		.compatible = "renesas,scif-r7s72100",
		.data = SCI_OF_DATA(PORT_SCIF, SCIx_SH2_SCIF_FIFODATA_REGTYPE),
	},
2780 2781 2782 2783 2784 2785 2786 2787 2788 2789 2790
	/* Family-specific types */
	{
		.compatible = "renesas,rcar-gen1-scif",
		.data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE),
	}, {
		.compatible = "renesas,rcar-gen2-scif",
		.data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE),
	}, {
		.compatible = "renesas,rcar-gen3-scif",
		.data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE),
	},
2791
	/* Generic types */
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Bastian Hecht 已提交
2792 2793
	{
		.compatible = "renesas,scif",
2794
		.data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_REGTYPE),
B
Bastian Hecht 已提交
2795 2796
	}, {
		.compatible = "renesas,scifa",
2797
		.data = SCI_OF_DATA(PORT_SCIFA, SCIx_SCIFA_REGTYPE),
B
Bastian Hecht 已提交
2798 2799
	}, {
		.compatible = "renesas,scifb",
2800
		.data = SCI_OF_DATA(PORT_SCIFB, SCIx_SCIFB_REGTYPE),
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Bastian Hecht 已提交
2801 2802
	}, {
		.compatible = "renesas,hscif",
2803
		.data = SCI_OF_DATA(PORT_HSCIF, SCIx_HSCIF_REGTYPE),
Y
Yoshinori Sato 已提交
2804 2805
	}, {
		.compatible = "renesas,sci",
2806
		.data = SCI_OF_DATA(PORT_SCI, SCIx_SCI_REGTYPE),
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Bastian Hecht 已提交
2807 2808 2809 2810 2811 2812
	}, {
		/* Terminator */
	},
};
MODULE_DEVICE_TABLE(of, of_sci_match);

2813 2814
static struct plat_sci_port *sci_parse_dt(struct platform_device *pdev,
					  unsigned int *dev_id)
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Bastian Hecht 已提交
2815 2816 2817 2818
{
	struct device_node *np = pdev->dev.of_node;
	const struct of_device_id *match;
	struct plat_sci_port *p;
2819
	struct sci_port *sp;
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Bastian Hecht 已提交
2820 2821 2822 2823 2824
	int id;

	if (!IS_ENABLED(CONFIG_OF) || !np)
		return NULL;

2825
	match = of_match_node(of_sci_match, np);
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2826 2827 2828 2829
	if (!match)
		return NULL;

	p = devm_kzalloc(&pdev->dev, sizeof(struct plat_sci_port), GFP_KERNEL);
2830
	if (!p)
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Bastian Hecht 已提交
2831 2832
		return NULL;

2833
	/* Get the line number from the aliases node. */
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2834 2835 2836 2837 2838 2839
	id = of_alias_get_id(np, "serial");
	if (id < 0) {
		dev_err(&pdev->dev, "failed to get alias id (%d)\n", id);
		return NULL;
	}

2840
	sp = &sci_ports[id];
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Bastian Hecht 已提交
2841 2842
	*dev_id = id;

2843 2844
	p->type = SCI_OF_TYPE(match->data);
	p->regtype = SCI_OF_REGTYPE(match->data);
B
Bastian Hecht 已提交
2845

2846
	if (of_find_property(np, "uart-has-rtscts", NULL))
2847
		sp->has_rtscts = true;
2848

B
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2849 2850 2851
	return p;
}

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2852
static int sci_probe_single(struct platform_device *dev,
2853 2854 2855 2856 2857 2858 2859 2860
				      unsigned int index,
				      struct plat_sci_port *p,
				      struct sci_port *sciport)
{
	int ret;

	/* Sanity check */
	if (unlikely(index >= SCI_NPORTS)) {
2861
		dev_notice(&dev->dev, "Attempting to register port %d when only %d are available\n",
2862
			   index+1, SCI_NPORTS);
2863
		dev_notice(&dev->dev, "Consider bumping CONFIG_SERIAL_SH_SCI_NR_UARTS!\n");
2864
		return -EINVAL;
2865 2866
	}

2867
	ret = sci_init_single(dev, sciport, index, p, false);
2868 2869
	if (ret)
		return ret;
2870

2871 2872 2873 2874
	sciport->gpios = mctrl_gpio_init(&sciport->port, 0);
	if (IS_ERR(sciport->gpios) && PTR_ERR(sciport->gpios) != -ENOSYS)
		return PTR_ERR(sciport->gpios);

2875
	if (sciport->has_rtscts) {
2876 2877 2878 2879 2880 2881 2882
		if (!IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(sciport->gpios,
							UART_GPIO_CTS)) ||
		    !IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(sciport->gpios,
							UART_GPIO_RTS))) {
			dev_err(&dev->dev, "Conflicting RTS/CTS config\n");
			return -EINVAL;
		}
2883
		sciport->port.flags |= UPF_HARD_FLOW;
2884 2885
	}

2886 2887 2888 2889 2890 2891 2892
	ret = uart_add_one_port(&sci_uart_driver, &sciport->port);
	if (ret) {
		sci_cleanup_single(sciport);
		return ret;
	}

	return 0;
2893 2894
}

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2895
static int sci_probe(struct platform_device *dev)
L
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2896
{
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2897 2898 2899
	struct plat_sci_port *p;
	struct sci_port *sp;
	unsigned int dev_id;
2900
	int ret;
2901

2902 2903 2904 2905 2906 2907 2908
	/*
	 * If we've come here via earlyprintk initialization, head off to
	 * the special early probe. We don't have sufficient device state
	 * to make it beyond this yet.
	 */
	if (is_early_platform_device(dev))
		return sci_probe_earlyprintk(dev);
2909

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2910 2911 2912 2913 2914 2915 2916 2917 2918 2919 2920 2921 2922 2923 2924
	if (dev->dev.of_node) {
		p = sci_parse_dt(dev, &dev_id);
		if (p == NULL)
			return -EINVAL;
	} else {
		p = dev->dev.platform_data;
		if (p == NULL) {
			dev_err(&dev->dev, "no platform data supplied\n");
			return -EINVAL;
		}

		dev_id = dev->id;
	}

	sp = &sci_ports[dev_id];
2925
	platform_set_drvdata(dev, sp);
2926

B
Bastian Hecht 已提交
2927
	ret = sci_probe_single(dev, dev_id, p, sp);
2928
	if (ret)
2929
		return ret;
2930

L
Linus Torvalds 已提交
2931 2932 2933 2934
#ifdef CONFIG_SH_STANDARD_BIOS
	sh_bios_gdb_detach();
#endif

2935
	return 0;
L
Linus Torvalds 已提交
2936 2937
}

S
Sergei Shtylyov 已提交
2938
static __maybe_unused int sci_suspend(struct device *dev)
L
Linus Torvalds 已提交
2939
{
2940
	struct sci_port *sport = dev_get_drvdata(dev);
2941

2942 2943
	if (sport)
		uart_suspend_port(&sci_uart_driver, &sport->port);
L
Linus Torvalds 已提交
2944

2945 2946
	return 0;
}
L
Linus Torvalds 已提交
2947

S
Sergei Shtylyov 已提交
2948
static __maybe_unused int sci_resume(struct device *dev)
2949
{
2950
	struct sci_port *sport = dev_get_drvdata(dev);
2951

2952 2953
	if (sport)
		uart_resume_port(&sci_uart_driver, &sport->port);
2954 2955 2956 2957

	return 0;
}

S
Sergei Shtylyov 已提交
2958
static SIMPLE_DEV_PM_OPS(sci_dev_pm_ops, sci_suspend, sci_resume);
2959

2960 2961
static struct platform_driver sci_driver = {
	.probe		= sci_probe,
2962
	.remove		= sci_remove,
2963 2964
	.driver		= {
		.name	= "sh-sci",
2965
		.pm	= &sci_dev_pm_ops,
B
Bastian Hecht 已提交
2966
		.of_match_table = of_match_ptr(of_sci_match),
2967 2968 2969 2970 2971 2972 2973
	},
};

static int __init sci_init(void)
{
	int ret;

2974
	pr_info("%s\n", banner);
2975 2976 2977 2978 2979 2980 2981 2982 2983 2984 2985 2986 2987 2988

	ret = uart_register_driver(&sci_uart_driver);
	if (likely(ret == 0)) {
		ret = platform_driver_register(&sci_driver);
		if (unlikely(ret))
			uart_unregister_driver(&sci_uart_driver);
	}

	return ret;
}

static void __exit sci_exit(void)
{
	platform_driver_unregister(&sci_driver);
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Linus Torvalds 已提交
2989 2990 2991
	uart_unregister_driver(&sci_uart_driver);
}

2992 2993 2994 2995
#ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
early_platform_init_buffer("earlyprintk", &sci_driver,
			   early_serial_buf, ARRAY_SIZE(early_serial_buf));
#endif
2996 2997 2998 2999 3000 3001 3002 3003 3004 3005 3006 3007 3008
#ifdef CONFIG_SERIAL_SH_SCI_EARLYCON
static struct __init plat_sci_port port_cfg;

static int __init early_console_setup(struct earlycon_device *device,
				      int type)
{
	if (!device->port.membase)
		return -ENODEV;

	device->port.serial_in = sci_serial_in;
	device->port.serial_out	= sci_serial_out;
	device->port.type = type;
	memcpy(&sci_ports[0].port, &device->port, sizeof(struct uart_port));
3009
	port_cfg.type = type;
3010
	sci_ports[0].cfg = &port_cfg;
3011
	sci_ports[0].params = sci_probe_regmap(&port_cfg);
3012 3013 3014
	port_cfg.scscr = sci_serial_in(&sci_ports[0].port, SCSCR);
	sci_serial_out(&sci_ports[0].port, SCSCR,
		       SCSCR_RE | SCSCR_TE | port_cfg.scscr);
3015 3016 3017 3018 3019 3020 3021 3022 3023 3024 3025 3026 3027 3028 3029 3030 3031 3032 3033 3034 3035 3036 3037 3038 3039 3040 3041 3042 3043 3044 3045 3046 3047 3048 3049 3050 3051

	device->con->write = serial_console_write;
	return 0;
}
static int __init sci_early_console_setup(struct earlycon_device *device,
					  const char *opt)
{
	return early_console_setup(device, PORT_SCI);
}
static int __init scif_early_console_setup(struct earlycon_device *device,
					  const char *opt)
{
	return early_console_setup(device, PORT_SCIF);
}
static int __init scifa_early_console_setup(struct earlycon_device *device,
					  const char *opt)
{
	return early_console_setup(device, PORT_SCIFA);
}
static int __init scifb_early_console_setup(struct earlycon_device *device,
					  const char *opt)
{
	return early_console_setup(device, PORT_SCIFB);
}
static int __init hscif_early_console_setup(struct earlycon_device *device,
					  const char *opt)
{
	return early_console_setup(device, PORT_HSCIF);
}

OF_EARLYCON_DECLARE(sci, "renesas,sci", sci_early_console_setup);
OF_EARLYCON_DECLARE(scif, "renesas,scif", scif_early_console_setup);
OF_EARLYCON_DECLARE(scifa, "renesas,scifa", scifa_early_console_setup);
OF_EARLYCON_DECLARE(scifb, "renesas,scifb", scifb_early_console_setup);
OF_EARLYCON_DECLARE(hscif, "renesas,hscif", hscif_early_console_setup);
#endif /* CONFIG_SERIAL_SH_SCI_EARLYCON */

L
Linus Torvalds 已提交
3052 3053 3054
module_init(sci_init);
module_exit(sci_exit);

3055
MODULE_LICENSE("GPL");
3056
MODULE_ALIAS("platform:sh-sci");
3057
MODULE_AUTHOR("Paul Mundt");
U
Ulrich Hecht 已提交
3058
MODULE_DESCRIPTION("SuperH (H)SCI(F) serial driver");