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提交 e095ee6b 编写于 作者: L Laurent Pinchart 提交者： Greg Kroah-Hartman
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serial: sh-sci: Replace regmap array with port parameters 

Turn the regmap two-dimensional array to an array of port parameters and
store a pointer to the port parameters in the sci_port structure. This
will allow handling additional port type dependent parameters.
Signed-off-by: NLaurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Reviewed-by: NGeert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>
上级 40b34ddb
隐藏空白更改
内联 并排
Showing with 155 addition and 123 deletion
drivers/tty/serial/sh-sci.c
浏览文件 @ e095ee6b
...@@ -101,10 +101,19 @@ enum SCI_CLKS { ...@@ -101,10 +101,19 @@ enum SCI_CLKS {
for ((_sr) = max_sr(_port); (_sr) >= min_sr(_port); (_sr)--) \ for ((_sr) = max_sr(_port); (_sr) >= min_sr(_port); (_sr)--) \
if ((_port)->sampling_rate_mask & SCI_SR((_sr))) if ((_port)->sampling_rate_mask & SCI_SR((_sr)))
struct plat_sci_reg {
u8 offset, size;
};
struct sci_port_params {
const struct plat_sci_reg regs[SCIx_NR_REGS];
};
struct sci_port { struct sci_port {
struct uart_port port; struct uart_port port;
/* Platform configuration */ /* Platform configuration */
const struct sci_port_params *params;
struct plat_sci_port *cfg; struct plat_sci_port *cfg;
unsigned int overrun_reg; unsigned int overrun_reg;
unsigned int overrun_mask; unsigned int overrun_mask;
...@@ -156,69 +165,73 @@ to_sci_port(struct uart_port *uart) ...@@ -156,69 +165,73 @@ to_sci_port(struct uart_port *uart)
return container_of(uart, struct sci_port, port); return container_of(uart, struct sci_port, port);
} }
struct plat_sci_reg { static const struct sci_port_params sci_port_params[SCIx_NR_REGTYPES] = {
u8 offset, size;
};
static const struct plat_sci_reg sci_regmap[SCIx_NR_REGTYPES][SCIx_NR_REGS] = {
/* /*
* Common SCI definitions, dependent on the port's regshift * Common SCI definitions, dependent on the port's regshift
* value. * value.
*/ */
[SCIx_SCI_REGTYPE] = { [SCIx_SCI_REGTYPE] = {
[SCSMR] = { 0x00, 8 }, .regs = {
[SCBRR] = { 0x01, 8 }, [SCSMR] = { 0x00, 8 },
[SCSCR] = { 0x02, 8 }, [SCBRR] = { 0x01, 8 },
[SCxTDR] = { 0x03, 8 }, [SCSCR] = { 0x02, 8 },
[SCxSR] = { 0x04, 8 }, [SCxTDR] = { 0x03, 8 },
[SCxRDR] = { 0x05, 8 }, [SCxSR] = { 0x04, 8 },
[SCxRDR] = { 0x05, 8 },
},
}, },
/* /*
* Common definitions for legacy IrDA ports. * Common definitions for legacy IrDA ports.
*/ */
[SCIx_IRDA_REGTYPE] = { [SCIx_IRDA_REGTYPE] = {
[SCSMR] = { 0x00, 8 }, .regs = {
[SCBRR] = { 0x02, 8 }, [SCSMR] = { 0x00, 8 },
[SCSCR] = { 0x04, 8 }, [SCBRR] = { 0x02, 8 },
[SCxTDR] = { 0x06, 8 }, [SCSCR] = { 0x04, 8 },
[SCxSR] = { 0x08, 16 }, [SCxTDR] = { 0x06, 8 },
[SCxRDR] = { 0x0a, 8 }, [SCxSR] = { 0x08, 16 },
[SCFCR] = { 0x0c, 8 }, [SCxRDR] = { 0x0a, 8 },
[SCFDR] = { 0x0e, 16 }, [SCFCR] = { 0x0c, 8 },
[SCFDR] = { 0x0e, 16 },
},
}, },
/* /*
* Common SCIFA definitions. * Common SCIFA definitions.
*/ */
[SCIx_SCIFA_REGTYPE] = { [SCIx_SCIFA_REGTYPE] = {
[SCSMR] = { 0x00, 16 }, .regs = {
[SCBRR] = { 0x04, 8 }, [SCSMR] = { 0x00, 16 },
[SCSCR] = { 0x08, 16 }, [SCBRR] = { 0x04, 8 },
[SCxTDR] = { 0x20, 8 }, [SCSCR] = { 0x08, 16 },
[SCxSR] = { 0x14, 16 }, [SCxTDR] = { 0x20, 8 },
[SCxRDR] = { 0x24, 8 }, [SCxSR] = { 0x14, 16 },
[SCFCR] = { 0x18, 16 }, [SCxRDR] = { 0x24, 8 },
[SCFDR] = { 0x1c, 16 }, [SCFCR] = { 0x18, 16 },
[SCPCR] = { 0x30, 16 }, [SCFDR] = { 0x1c, 16 },
[SCPDR] = { 0x34, 16 }, [SCPCR] = { 0x30, 16 },
[SCPDR] = { 0x34, 16 },
},
}, },
/* /*
* Common SCIFB definitions. * Common SCIFB definitions.
*/ */
[SCIx_SCIFB_REGTYPE] = { [SCIx_SCIFB_REGTYPE] = {
[SCSMR] = { 0x00, 16 }, .regs = {
[SCBRR] = { 0x04, 8 }, [SCSMR] = { 0x00, 16 },
[SCSCR] = { 0x08, 16 }, [SCBRR] = { 0x04, 8 },
[SCxTDR] = { 0x40, 8 }, [SCSCR] = { 0x08, 16 },
[SCxSR] = { 0x14, 16 }, [SCxTDR] = { 0x40, 8 },
[SCxRDR] = { 0x60, 8 }, [SCxSR] = { 0x14, 16 },
[SCFCR] = { 0x18, 16 }, [SCxRDR] = { 0x60, 8 },
[SCTFDR] = { 0x38, 16 }, [SCFCR] = { 0x18, 16 },
[SCRFDR] = { 0x3c, 16 }, [SCTFDR] = { 0x38, 16 },
[SCPCR] = { 0x30, 16 }, [SCRFDR] = { 0x3c, 16 },
[SCPDR] = { 0x34, 16 }, [SCPCR] = { 0x30, 16 },
[SCPDR] = { 0x34, 16 },
},
}, },
/* /*
...@@ -226,46 +239,52 @@ static const struct plat_sci_reg sci_regmap[SCIx_NR_REGTYPES][SCIx_NR_REGS] = { ...@@ -226,46 +239,52 @@ static const struct plat_sci_reg sci_regmap[SCIx_NR_REGTYPES][SCIx_NR_REGS] = {
* count registers. * count registers.
*/ */
[SCIx_SH2_SCIF_FIFODATA_REGTYPE] = { [SCIx_SH2_SCIF_FIFODATA_REGTYPE] = {
[SCSMR] = { 0x00, 16 }, .regs = {
[SCBRR] = { 0x04, 8 }, [SCSMR] = { 0x00, 16 },
[SCSCR] = { 0x08, 16 }, [SCBRR] = { 0x04, 8 },
[SCxTDR] = { 0x0c, 8 }, [SCSCR] = { 0x08, 16 },
[SCxSR] = { 0x10, 16 }, [SCxTDR] = { 0x0c, 8 },
[SCxRDR] = { 0x14, 8 }, [SCxSR] = { 0x10, 16 },
[SCFCR] = { 0x18, 16 }, [SCxRDR] = { 0x14, 8 },
[SCFDR] = { 0x1c, 16 }, [SCFCR] = { 0x18, 16 },
[SCSPTR] = { 0x20, 16 }, [SCFDR] = { 0x1c, 16 },
[SCLSR] = { 0x24, 16 }, [SCSPTR] = { 0x20, 16 },
[SCLSR] = { 0x24, 16 },
},
}, },
/* /*
* Common SH-3 SCIF definitions. * Common SH-3 SCIF definitions.
*/ */
[SCIx_SH3_SCIF_REGTYPE] = { [SCIx_SH3_SCIF_REGTYPE] = {
[SCSMR] = { 0x00, 8 }, .regs = {
[SCBRR] = { 0x02, 8 }, [SCSMR] = { 0x00, 8 },
[SCSCR] = { 0x04, 8 }, [SCBRR] = { 0x02, 8 },
[SCxTDR] = { 0x06, 8 }, [SCSCR] = { 0x04, 8 },
[SCxSR] = { 0x08, 16 }, [SCxTDR] = { 0x06, 8 },
[SCxRDR] = { 0x0a, 8 }, [SCxSR] = { 0x08, 16 },
[SCFCR] = { 0x0c, 8 }, [SCxRDR] = { 0x0a, 8 },
[SCFDR] = { 0x0e, 16 }, [SCFCR] = { 0x0c, 8 },
[SCFDR] = { 0x0e, 16 },
},
}, },
/* /*
* Common SH-4(A) SCIF(B) definitions. * Common SH-4(A) SCIF(B) definitions.
*/ */
[SCIx_SH4_SCIF_REGTYPE] = { [SCIx_SH4_SCIF_REGTYPE] = {
[SCSMR] = { 0x00, 16 }, .regs = {
[SCBRR] = { 0x04, 8 }, [SCSMR] = { 0x00, 16 },
[SCSCR] = { 0x08, 16 }, [SCBRR] = { 0x04, 8 },
[SCxTDR] = { 0x0c, 8 }, [SCSCR] = { 0x08, 16 },
[SCxSR] = { 0x10, 16 }, [SCxTDR] = { 0x0c, 8 },
[SCxRDR] = { 0x14, 8 }, [SCxSR] = { 0x10, 16 },
[SCFCR] = { 0x18, 16 }, [SCxRDR] = { 0x14, 8 },
[SCFDR] = { 0x1c, 16 }, [SCFCR] = { 0x18, 16 },
[SCSPTR] = { 0x20, 16 }, [SCFDR] = { 0x1c, 16 },
[SCLSR] = { 0x24, 16 }, [SCSPTR] = { 0x20, 16 },
[SCLSR] = { 0x24, 16 },
},
}, },
/* /*
...@@ -273,37 +292,41 @@ static const struct plat_sci_reg sci_regmap[SCIx_NR_REGTYPES][SCIx_NR_REGS] = { ...@@ -273,37 +292,41 @@ static const struct plat_sci_reg sci_regmap[SCIx_NR_REGTYPES][SCIx_NR_REGS] = {
* External Clock (BRG). * External Clock (BRG).
*/ */
[SCIx_SH4_SCIF_BRG_REGTYPE] = { [SCIx_SH4_SCIF_BRG_REGTYPE] = {
[SCSMR] = { 0x00, 16 }, .regs = {
[SCBRR] = { 0x04, 8 }, [SCSMR] = { 0x00, 16 },
[SCSCR] = { 0x08, 16 }, [SCBRR] = { 0x04, 8 },
[SCxTDR] = { 0x0c, 8 }, [SCSCR] = { 0x08, 16 },
[SCxSR] = { 0x10, 16 }, [SCxTDR] = { 0x0c, 8 },
[SCxRDR] = { 0x14, 8 }, [SCxSR] = { 0x10, 16 },
[SCFCR] = { 0x18, 16 }, [SCxRDR] = { 0x14, 8 },
[SCFDR] = { 0x1c, 16 }, [SCFCR] = { 0x18, 16 },
[SCSPTR] = { 0x20, 16 }, [SCFDR] = { 0x1c, 16 },
[SCLSR] = { 0x24, 16 }, [SCSPTR] = { 0x20, 16 },
[SCDL] = { 0x30, 16 }, [SCLSR] = { 0x24, 16 },
[SCCKS] = { 0x34, 16 }, [SCDL] = { 0x30, 16 },
[SCCKS] = { 0x34, 16 },
},
}, },
/* /*
* Common HSCIF definitions. * Common HSCIF definitions.
*/ */
[SCIx_HSCIF_REGTYPE] = { [SCIx_HSCIF_REGTYPE] = {
[SCSMR] = { 0x00, 16 }, .regs = {
[SCBRR] = { 0x04, 8 }, [SCSMR] = { 0x00, 16 },
[SCSCR] = { 0x08, 16 }, [SCBRR] = { 0x04, 8 },
[SCxTDR] = { 0x0c, 8 }, [SCSCR] = { 0x08, 16 },
[SCxSR] = { 0x10, 16 }, [SCxTDR] = { 0x0c, 8 },
[SCxRDR] = { 0x14, 8 }, [SCxSR] = { 0x10, 16 },
[SCFCR] = { 0x18, 16 }, [SCxRDR] = { 0x14, 8 },
[SCFDR] = { 0x1c, 16 }, [SCFCR] = { 0x18, 16 },
[SCSPTR] = { 0x20, 16 }, [SCFDR] = { 0x1c, 16 },
[SCLSR] = { 0x24, 16 }, [SCSPTR] = { 0x20, 16 },
[HSSRR] = { 0x40, 16 }, [SCLSR] = { 0x24, 16 },
[SCDL] = { 0x30, 16 }, [HSSRR] = { 0x40, 16 },
[SCCKS] = { 0x34, 16 }, [SCDL] = { 0x30, 16 },
[SCCKS] = { 0x34, 16 },
},
}, },
/* /*
...@@ -311,15 +334,17 @@ static const struct plat_sci_reg sci_regmap[SCIx_NR_REGTYPES][SCIx_NR_REGS] = { ...@@ -311,15 +334,17 @@ static const struct plat_sci_reg sci_regmap[SCIx_NR_REGTYPES][SCIx_NR_REGS] = {
* register. * register.
*/ */
[SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE] = { [SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE] = {
[SCSMR] = { 0x00, 16 }, .regs = {
[SCBRR] = { 0x04, 8 }, [SCSMR] = { 0x00, 16 },
[SCSCR] = { 0x08, 16 }, [SCBRR] = { 0x04, 8 },
[SCxTDR] = { 0x0c, 8 }, [SCSCR] = { 0x08, 16 },
[SCxSR] = { 0x10, 16 }, [SCxTDR] = { 0x0c, 8 },
[SCxRDR] = { 0x14, 8 }, [SCxSR] = { 0x10, 16 },
[SCFCR] = { 0x18, 16 }, [SCxRDR] = { 0x14, 8 },
[SCFDR] = { 0x1c, 16 }, [SCFCR] = { 0x18, 16 },
[SCLSR] = { 0x24, 16 }, [SCFDR] = { 0x1c, 16 },
[SCLSR] = { 0x24, 16 },
},
}, },
/* /*
...@@ -327,18 +352,20 @@ static const struct plat_sci_reg sci_regmap[SCIx_NR_REGTYPES][SCIx_NR_REGS] = { ...@@ -327,18 +352,20 @@ static const struct plat_sci_reg sci_regmap[SCIx_NR_REGTYPES][SCIx_NR_REGS] = {
* count registers. * count registers.
*/ */
[SCIx_SH4_SCIF_FIFODATA_REGTYPE] = { [SCIx_SH4_SCIF_FIFODATA_REGTYPE] = {
[SCSMR] = { 0x00, 16 }, .regs = {
[SCBRR] = { 0x04, 8 }, [SCSMR] = { 0x00, 16 },
[SCSCR] = { 0x08, 16 }, [SCBRR] = { 0x04, 8 },
[SCxTDR] = { 0x0c, 8 }, [SCSCR] = { 0x08, 16 },
[SCxSR] = { 0x10, 16 }, [SCxTDR] = { 0x0c, 8 },
[SCxRDR] = { 0x14, 8 }, [SCxSR] = { 0x10, 16 },
[SCFCR] = { 0x18, 16 }, [SCxRDR] = { 0x14, 8 },
[SCFDR] = { 0x1c, 16 }, [SCFCR] = { 0x18, 16 },
[SCTFDR] = { 0x1c, 16 }, /* aliased to SCFDR */ [SCFDR] = { 0x1c, 16 },
[SCRFDR] = { 0x20, 16 }, [SCTFDR] = { 0x1c, 16 }, /* aliased to SCFDR */
[SCSPTR] = { 0x24, 16 }, [SCRFDR] = { 0x20, 16 },
[SCLSR] = { 0x28, 16 }, [SCSPTR] = { 0x24, 16 },
[SCLSR] = { 0x28, 16 },
},
}, },
/* /*
...@@ -346,18 +373,20 @@ static const struct plat_sci_reg sci_regmap[SCIx_NR_REGTYPES][SCIx_NR_REGS] = { ...@@ -346,18 +373,20 @@ static const struct plat_sci_reg sci_regmap[SCIx_NR_REGTYPES][SCIx_NR_REGS] = {
* registers. * registers.
*/ */
[SCIx_SH7705_SCIF_REGTYPE] = { [SCIx_SH7705_SCIF_REGTYPE] = {
[SCSMR] = { 0x00, 16 }, .regs = {
[SCBRR] = { 0x04, 8 }, [SCSMR] = { 0x00, 16 },
[SCSCR] = { 0x08, 16 }, [SCBRR] = { 0x04, 8 },
[SCxTDR] = { 0x20, 8 }, [SCSCR] = { 0x08, 16 },
[SCxSR] = { 0x14, 16 }, [SCxTDR] = { 0x20, 8 },
[SCxRDR] = { 0x24, 8 }, [SCxSR] = { 0x14, 16 },
[SCFCR] = { 0x18, 16 }, [SCxRDR] = { 0x24, 8 },
[SCFDR] = { 0x1c, 16 }, [SCFCR] = { 0x18, 16 },
[SCFDR] = { 0x1c, 16 },
},
}, },
}; };
#define sci_getreg(up, offset) (sci_regmap[to_sci_port(up)->cfg->regtype] + offset) #define sci_getreg(up, offset) (&to_sci_port(up)->params->regs[offset])
/* /*
* The "offset" here is rather misleading, in that it refers to an enum * The "offset" here is rather misleading, in that it refers to an enum
...@@ -2557,6 +2586,8 @@ static int sci_init_single(struct platform_device *dev, ...@@ -2557,6 +2586,8 @@ static int sci_init_single(struct platform_device *dev,
return ret; return ret;
} }
sci_port->params = &sci_port_params[p->regtype];
switch (p->type) { switch (p->type) {
case PORT_SCIFB: case PORT_SCIFB:
port->fifosize = 256; port->fifosize = 256;
...@@ -3069,6 +3100,7 @@ static int __init early_console_setup(struct earlycon_device *device, ...@@ -3069,6 +3100,7 @@ static int __init early_console_setup(struct earlycon_device *device,
sci_ports[0].cfg = &port_cfg; sci_ports[0].cfg = &port_cfg;
sci_ports[0].cfg->type = type; sci_ports[0].cfg->type = type;
sci_probe_regmap(sci_ports[0].cfg); sci_probe_regmap(sci_ports[0].cfg);
sci_ports[0].params = &sci_port_params[sci_ports[0].cfg->regtype];
port_cfg.scscr = sci_serial_in(&sci_ports[0].port, SCSCR); port_cfg.scscr = sci_serial_in(&sci_ports[0].port, SCSCR);
sci_serial_out(&sci_ports[0].port, SCSCR, sci_serial_out(&sci_ports[0].port, SCSCR,
SCSCR_RE | SCSCR_TE | port_cfg.scscr); SCSCR_RE | SCSCR_TE | port_cfg.scscr);
......
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