Summary: Added missing UseSSE42 check. Also added missing avx2 assert for vpermq instruction.
Reviewed-by: roland, twisti

Summary: Rename INCLUDE_ALTERNATE_GCS to INCLUDE_ALL_GCS and replace SERIALGC with INCLUDE_ALL_GCS.
Reviewed-by: coleenp, stefank

Summary: Use SSE4.2 and AVX2 instructions for encodeArray intrinsic.
Reviewed-by: roland

Summary: use 256bit vpxor,vptest instructions in String.compareTo() and equals() intrinsics.
Reviewed-by: twisti

Reviewed-by: jrose, kvn, twisti
Contributed-by: NMorris Meyer <morris.meyer@oracle.com>

Summary: Use YMM registers in arraycopy and array_fill stubs.
Reviewed-by: roland, twisti

Summary: use 'rep stosb' instead of 'rep stosq' when fast-string operations are available.
Reviewed-by: twisti, roland

Reviewed-by: jrose, kvn, twisti
Contributed-by: NMorris Meyer <morris.meyer@oracle.com>

Summary: Enable AES intrinsics on non-AVX cpus, group together aes instructions in crypto stubs.
Reviewed-by: roland, twisti

Reviewed-by: jrose, kvn, twisti
Contributed-by: NMorris Meyer <morris.meyer@oracle.com>

Reviewed-by: kvn

Reviewed-by: twisti, kvn
Contributed-by: NBharadwaj Yadavalli <bharadwaj.yadavalli@oracle.com>

Summary: Use new x86 AES instructions for AESCrypt.
Reviewed-by: twisti, kvn, roland
Contributed-by: tom.deneau@amd.com

Summary: support of compress class pointers in the compilers.
Reviewed-by: kvn, twisti

Summary: Remove buggy experimental option
Reviewed-by: acorn, coleenp
Contributed-by: harold.seigel@oracle.com

Summary: Capitalize these metadata types (and objArrayKlass)
Reviewed-by: stefank, twisti, kvn

Summary: Remove PermGen, allocate meta-data in metaspace linked to class loaders, rewrite GC walking, rewrite and rename metadata to be C++ classes
Reviewed-by: jmasa, stefank, never, coleenp, kvn, brutisso, mgerdin, dholmes, jrose, twisti, roland
Contributed-by: Njmasa &lt;jon.masamitsu@oracle.com&gt;, stefank &lt;stefan.karlsson@oracle.com&gt;, mgerdin &lt;mikael.gerdin@oracle.com&gt;, never <tom.rodriguez@oracle.com>

Summary: Added asm encoding and mach nodes for vector arithmetic instructions on x86.
Reviewed-by: roland

6984705: JSR 292 method handle creation should not go through JNI
Summary: remove assembly code for JDK 7 chained method handles
Reviewed-by: jrose, twisti, kvn, mhaupt
Contributed-by: NJohn Rose &lt;john.r.rose@oracle.com&gt;, Christian Thalinger &lt;christian.thalinger@oracle.com&gt;, Michael Haupt <michael.haupt@oracle.com>

Summary: renamed mach nodes which use scalar AVX instructions, added integer vectors shuffling instructions
Reviewed-by: twisti

Summary: Increase vector size up to 256-bits for YMM AVX registers on x86.
Reviewed-by: never, twisti, roland

Summary: increase precision on x86 for the steps of the computation of exp and pow.
Reviewed-by: kvn

Summary: bad test for parity of y in pow(x,y) (c1, interpreter)
Reviewed-by: kvn, twisti

Summary: use x87 instructions to implement exp() and pow() in interpreter/c1/c2.
Reviewed-by: kvn, never, twisti

Reviewed-by: kvn, iveresov

Summary: Save whole XMM/YMM registers in safepoint interrupt handler.
Reviewed-by: roland, twisti

Summary: For C2 moved saving EBP after ESP adjustment. For C1 generated 5 byte nop instruction first if needed.
Reviewed-by: never, twisti, azeemj

Summary: Setup thread register in MacroAssembler::incr_allocated_bytes() on x64
Reviewed-by: kvn

Summary: Distance is too large for one short branch in string_indexofC8().
Reviewed-by: iveresov

Summary: Disable verify_heapbase on sparc if TraceBytecodes because the latter uses r12 as a temp register
Reviewed-by: coleenp, phh
Contributed-by: NVolker Simonis <volker.simonis@gmail.com>

Summary: Moved sizeof(klassOopDesc), changed the return type to ByteSize and removed the _in_bytes suffix.
Reviewed-by: never, bdelsart, coleenp, jrose

Summary: Use 3-operands SIMD instructions in C2 generated code for machines with AVX.
Reviewed-by: never

Summary: Added support for AVX extension to the x86 instruction set.
Reviewed-by: never

7110489: C1: 64-bit tiered with ForceUnreachable: assert(reachable(src)) failed: Address should be reachable
Reviewed-by: kvn, iveresov, twisti

Reviewed-by: jrose, twisti, kvn, coleenp

Summary: fix assert, prefetchnta is supported since SSE not SSE2.
Reviewed-by: never

Reviewed-by: kvn, iveresov, never

Summary: on T4 2 BIS instructions should be issued to prefetch 64 bytes
Reviewed-by: iveresov, phh, twisti

Summary: Use new short branch instruction in C2 generated code.
Reviewed-by: never

Summary: code was using andq reg, imm instead of addq addr, imm
Reviewed-by: kvn, jrose, twisti