Summary: For C2 moved saving EBP after ESP adjustment. For C1 generated 5 byte nop instruction first if needed.
Reviewed-by: never, twisti, azeemj

Summary: Nested locks elimination done before lock nodes expansion by looking for outer locks of the same object.
Reviewed-by: never, twisti

Summary: adds store store barrier after initialization of header and body of objects.
Reviewed-by: never, kvn

Summary: Use 3-operands SIMD instructions in C2 generated code for machines with AVX.
Reviewed-by: never

Summary: Added support for AVX extension to the x86 instruction set.
Reviewed-by: never

Summary: allow reg_class definition as a function.
Reviewed-by: kvn, never

Summary: Avoid CMove in a loop if possible. May generate CMove if it could be moved outside a loop.
Reviewed-by: never

Reviewed-by: kvn, never, bdelsart

Summary: on T4 2 BIS instructions should be issued to prefetch 64 bytes
Reviewed-by: iveresov, phh, twisti

Summary: Use new short branch instruction in C2 generated code.
Reviewed-by: never

Summary: replace MemBarAcquire/MemBarRelease nodes on the monitor enter/exit code paths with new MemBarAcquireLock/MemBarReleaseLock nodes
Reviewed-by: kvn, twisti

Summary: Remove flags which duplicate information in Node::NodeClasses.
Reviewed-by: never

Summary: Add new short branch instruction to Hotspot sparc assembler.
Reviewed-by: never, twisti, jrose

Summary: Fix integer overflow problem in the code generated by loop optimizer.
Reviewed-by: never

Summary: The upcoming processors from AMD are the first that support 3dnow prefetch without supporting the 3dnow instruction set.
Reviewed-by: kvn
Contributed-by: tom.deneau@amd.com

Summary: Enables cross building of a c2 VM. Support masking of shift counts when the processor architecture mandates it.
Reviewed-by: kvn, never

Summary: copy small (<8) strings on stack if str+16 crosses a page boundary and load from stack into XMM. Back up pointer when loading string's tail.
Reviewed-by: never

Reviewed-by: kvn

Summary: oops should be loaded from the constant table of an nmethod instead of materializing them with a long code sequence.
Reviewed-by: never, kvn

Summary: use unsigned DIV instruction
Reviewed-by: never

Summary: Use hardware DIV instruction for long division by constant when it is faster than code with multiply.
Reviewed-by: never

Summary: This is the renaming part of 6961697 to keep the actual changes small for review.
Reviewed-by: kvn, never

Reviewed-by: kvn

Summary: Hoist DecodeN instruction above null check
Reviewed-by: never, twisti

Summary: Change all the Sun copyrights to Oracle copyright
Reviewed-by: ohair

Summary: C2 for SPARC needs to support JSR 292.
Reviewed-by: kvn, never

Reviewed-by: never, twisti
Contributed-by: NHiroshi Yamauchi <yamauchi@google.com>

Summary: Matcher::float_in_double should be true only when FPU is used for floats.
Reviewed-by: never, twisti

Reviewed-by: never, twisti, kvn, rasbold
Contributed-by: NHiroshi Yamauchi <yamauchi@google.com>

Summary: C2 implementation for invokedynamic support.
Reviewed-by: kvn, never

Summary: Make a special root-list for those few nmethods which might contain non-perm oops.
Reviewed-by: twisti, kvn, never, jmasa, ysr

6875866: Intrinsic for String.indexOf() is broken on x86 with SSE4.2
Summary: Modify String intrinsic methods to pass char[] pointers instead of string oops.
Reviewed-by: never

Summary: The optimizer should be told to normalize (AndL (ConvI2L x) 0xFF) to (ConvI2L (AndI x 0xFF)), and then the existing matcher rule will work for free.
Reviewed-by: kvn

Summary: 6797305 handles load widening but no shortening which should be covered here.
Reviewed-by: never, kvn

Summary: These methods can be instrinsified by using bit scan, bit test, and population count instructions.
Reviewed-by: kvn, never

Summary: Use SSE 4.2 in intrinsics for String.{compareTo/equals/indexOf} and Arrays.equals.
Reviewed-by: kvn, never, jrose

Reviewed-by: kvn, phh

Summary: Code in interp_masm, stubGenerator, c1_LIRAssembler, and AD files moved into MacroAssembler.
Reviewed-by: kvn

Summary: bitCount() should use POPC on SPARC processors where POPC is implemented directly in hardware.
Reviewed-by: kvn, never

Summary: Update copyright for files that have been modified in 2009, up to 03/09
Reviewed-by: katleman, tbell, ohair