Merge

src/cpu/x86/vm/x86_64.ad

@@ -8075,6 +8075,18 @@ instruct mulL_mem_imm(rRegL dst, memory src, immL32 imm, rFlagsReg cr)
   ins_pipe(ialu_reg_mem_alu0);
 %}
 
+instruct mulHiL_rReg(rdx_RegL dst, no_rax_RegL src, rax_RegL rax, rFlagsReg cr)
+%{
+  match(Set dst (MulHiL src rax));
+  effect(USE_KILL rax, KILL cr);
+
+  ins_cost(300);
+  format %{ "imulq   RDX:RAX, RAX, $src\t# mulhi" %}
+  opcode(0xF7, 0x5); /* Opcode F7 /5 */
+  ins_encode(REX_reg_wide(src), OpcP, reg_opc(src));
+  ins_pipe(ialu_reg_reg_alu0);
+%}
+
 instruct divI_rReg(rax_RegI rax, rdx_RegI rdx, no_rax_rdx_RegI div,
                    rFlagsReg cr)
 %{

src/share/vm/opto/classes.hpp

@@ -164,6 +164,7 @@ macro(MoveL2D)
 macro(MoveD2L)
 macro(MulD)
 macro(MulF)
+macro(MulHiL)
 macro(MulI)
 macro(MulL)
 macro(Multi)

src/share/vm/opto/mulnode.cpp

@@ -364,6 +364,25 @@ const Type *MulDNode::mul_ring(const Type *t0, const Type *t1) const {
   return TypeD::make( t0->getd() * t1->getd() );
 }
 
+//=============================================================================
+//------------------------------Value------------------------------------------
+const Type *MulHiLNode::Value( PhaseTransform *phase ) const {
+  // Either input is TOP ==> the result is TOP
+  const Type *t1 = phase->type( in(1) );
+  const Type *t2 = phase->type( in(2) );
+  if( t1 == Type::TOP ) return Type::TOP;
+  if( t2 == Type::TOP ) return Type::TOP;
+
+  // Either input is BOTTOM ==> the result is the local BOTTOM
+  const Type *bot = bottom_type();
+  if( (t1 == bot) || (t2 == bot) ||
+      (t1 == Type::BOTTOM) || (t2 == Type::BOTTOM) )
+    return bot;
+
+  // It is not worth trying to constant fold this stuff!
+  return TypeLong::LONG;
+}
+
 //=============================================================================
 //------------------------------mul_ring---------------------------------------
 // Supplied function returns the product of the inputs IN THE CURRENT RING.

src/share/vm/opto/mulnode.hpp

@@ -133,6 +133,16 @@ public:
   virtual uint ideal_reg() const { return Op_RegD; }
 };
 
+//-------------------------------MulHiLNode------------------------------------
+// Upper 64 bits of a 64 bit by 64 bit multiply
+class MulHiLNode : public Node {
+public:
+  MulHiLNode( Node *in1, Node *in2 ) : Node(0,in1,in2) {}
+  virtual int Opcode() const;
+  virtual const Type *Value( PhaseTransform *phase ) const;
+  const Type *bottom_type() const { return TypeLong::LONG; }
+  virtual uint ideal_reg() const { return Op_RegL; }
+};
 
 //------------------------------AndINode---------------------------------------
 // Logically AND 2 integers.  Included with the MUL nodes because it inherits

src/share/vm/opto/type.hpp

@@ -442,6 +442,7 @@ public:
 
   // Check for single integer
   int is_con() const { return _lo==_hi; }
+  bool is_con(int i) const { return is_con() && _lo == i; }
   jlong get_con() const { assert( is_con(), "" ); return _lo; }
 
   virtual bool        is_finite() const;  // Has a finite value

src/share/vm/utilities/globalDefinitions.hpp

@@ -890,7 +890,7 @@ inline int log2_long(jlong x) {
     i++; p *= 2;
   }
   // p = 2^(i+1) && x < p (i.e., 2^i <= x < 2^(i+1))
-  // (if p = 0 then overflow occured and i = 31)
+  // (if p = 0 then overflow occured and i = 63)
   return i;
 }