1. 18 11月, 2014 1 次提交
    • J
      mfd/axp20x: avoid irq numbering collision · ff3bbc5c
      Jacob Pan 提交于
      IRQ numbers in axp20x devices are defined with high-order bit first
      in each IRQ enable/status registers. On Intel platforms it is more
      common to number IRQs with least significant bit first. Therefore,
      sharing IRQ# between the two is very difficult. Since AXP288 is a
      customized PMIC for Intel platform and the amount of shared IRQs are
      very small, we use separate IRQ numbering. This also fixes collision
      and a duplicate in WBTO interrupt.
      
      e.g. For the 16 interrupts controlled in IRQ enabled registers 1 & 2,
      on axp20x for ARM, the PMIC local IRQ numbers and register bits are
      mapped as:
      IRQ#:  0  1  2  3  4  5  6  7      8  9 10 11 12 13 14 15
      ---------------------------------------------------------
      ARM:   7  6  5  4  3  2  1  0      7  6  5  4  3  2  1  0
      Intel: 0  1  2  3  4  5  6  7      0  1  2  3  4  5  6  7
      Signed-off-by: NTodd Brandt <todd.e.brandt@linux.intel.com>
      Signed-off-by: NJacob Pan <jacob.jun.pan@linux.intel.com>
      Acked-by: NJonathan Cameron <jic23@kernel.org>
      Signed-off-by: NLee Jones <lee.jones@linaro.org>
      ff3bbc5c
  2. 07 10月, 2014 1 次提交
  3. 03 6月, 2014 1 次提交