- 02 4月, 2015 5 次提交
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由 Stephane Viau 提交于
Some upcoming targets have more bits to set in CTL_FLUSH registers. Example: msm8x16 needs to set TIMING1 bit so that some of the INTF1's interface registers get flushed. Signed-off-by: NStephane Viau <sviau@codeaurora.org> Signed-off-by: NRob Clark <robdclark@gmail.com>
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由 Stephane Viau 提交于
This patch contains the generated header file of the following change "drm/msm/mdp5: Get SMP client list from mdp5_cfg". Signed-off-by: NStephane Viau <sviau@codeaurora.org> Signed-off-by: NRob Clark <robdclark@gmail.com>
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由 Stephane Viau 提交于
This change contains the generated header file for the following change "drm/msm/mdp5: Separate MDP5 domain from MDSS domain". Signed-off-by: NStephane Viau <sviau@codeaurora.org> Signed-off-by: NRob Clark <robdclark@gmail.com>
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由 Hai Li 提交于
This change adds the registers in mdp5 ping pong blocks and split display control registers. Signed-off-by: NHai Li <hali@codeaurora.org> Signed-off-by: NRob Clark <robdclark@gmail.com>
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由 Stephane Viau 提交于
Prepare for pipeline operation mode configuration, in particular for DSI and WB modes. Signed-off-by: NStephane Viau <sviau@codeaurora.org> [Throw in a #define temporarily to keep things bisectable -Rob] Signed-off-by: NRob Clark <robdclark@gmail.com>
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- 05 3月, 2015 1 次提交
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由 Stephane Viau 提交于
Some target have up to 6 layer mixers (LM). Let the header file access the last LM's base address. Signed-off-by: NStephane Viau <sviau@codeaurora.org> Signed-off-by: NRob Clark <robdclark@gmail.com>
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- 02 2月, 2015 1 次提交
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由 Rob Clark 提交于
Resync from rnndb database, to pull in register defines for: * eDP * HDMI/HDCP * mdp4/mdp5 YUV support * mdp5 hw cursor support Signed-off-by: NRob Clark <robdclark@gmail.com>
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- 17 11月, 2014 1 次提交
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由 Rob Clark 提交于
Signed-off-by: NRob Clark <robdclark@gmail.com>
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- 04 8月, 2014 2 次提交
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由 Stephane Viau 提交于
MDP5 has several functional blocks (ie: VIG/RGB pipes, LMs, ...). From one revision to another, these blocks' base addresses might change due to the number of instances present in the MDP5 hw. A way of dealing with these offset changes is to introduce dynamic offsets 'per block'. This change adds support for the new revision of MDP5: v1.3. The idea is to define one hw config per MDP version and select either one of them at runtime, after reading the MDP5 version. Once the MDP version is known, 'per block' dynamic offsets are initialized through a global pointer, which is then used for read/write register access. Signed-off-by: NStephane Viau <sviau@codeaurora.org> Signed-off-by: NRob Clark <robdclark@gmail.com>
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由 Rob Clark 提交于
Signed-off-by: NRob Clark <robdclark@gmail.com>
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- 10 1月, 2014 1 次提交
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由 Rob Clark 提交于
resync to latest envytools db, add mdp5 registers Signed-off-by: NRob Clark <robdclark@gmail.com>
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