1. 17 4月, 2012 1 次提交
  2. 25 1月, 2012 1 次提交
  3. 07 1月, 2012 1 次提交
  4. 09 11月, 2011 1 次提交
  5. 15 9月, 2011 1 次提交
  6. 21 7月, 2011 1 次提交
  7. 08 4月, 2011 1 次提交
  8. 25 3月, 2011 1 次提交
  9. 01 2月, 2011 1 次提交
    • W
      iwlagn: add IQ inversion support for 2000 series devices · 52e6b85f
      Wey-Yi Guy 提交于
      The I/Q swapping is extremely important and should be dealt with extra care.
      It will affects OFDM and CCK differently.
      
      For 6000/6005/6030 series devices, the I/Q were swapped, and for 2000 series
      devices, it is in non-swapped status (but its swapped with respected to 6000/6005/6030).
      so the CSR_GP_DRIVER_REG_BIT_RADIO_IQ_INVER register need to be set to support
      the correct behavior.
      Signed-off-by: NWey-Yi Guy <wey-yi.w.guy@intel.com>
      52e6b85f
  10. 22 1月, 2011 2 次提交
  11. 16 11月, 2010 1 次提交
  12. 29 9月, 2010 1 次提交
  13. 10 7月, 2010 1 次提交
  14. 17 4月, 2010 1 次提交
  15. 20 2月, 2010 1 次提交
  16. 20 1月, 2010 1 次提交
  17. 22 12月, 2009 1 次提交
    • R
      iwlwifi: power up all devices for EEPROM read · f8701fe3
      Reinette Chatre 提交于
      Recent commits "iwlwifi: remove power-wasting calls to apm_ops.init()" and
      "iwlagn: power up device before initializing EEPROM" had the goal of
      reducing device power consumption from the time the module is loaded until
      the interface is brought up and the device's power saving mechanisms kick
      in. The idea is that once the module is loaded there is no need for the
      device to consume power until the interface is brought up.
      
      With the current solution the device is only powered up during EEPROM read,
      and then so also only if the EEPROM type is OTP. We have found that on
      certain platforms even non-OTP devices require power to be up during EEPROM
      read. On these platforms the driver never loads and the system log contains
      the following:
      
      iwlagn 0000:03:00.0: MAC is in deep sleep!.  CSR_GP_CNTRL = 0x080403D8
      
      We thus now power up all devices during EEPROM read.
      Signed-off-by: NReinette Chatre <reinette.chatre@intel.com>
      Signed-off-by: NJohn W. Linville <linville@tuxdriver.com>
      f8701fe3
  18. 24 11月, 2009 1 次提交
    • B
      iwlagn: Use iwl_write8() for CSR_INT_COALESCING register · 74ba67ed
      Ben Cahill 提交于
      CSR_INT_COALESCING previously had only one, but now has two single-byte fields.
      With only one single-byte field (lowest order byte) it was okay to write via
      iwl_write32(), but now with two, an iwl_write32() to the lower order field
      clobbers the other field (odd-address CSR_INT_PERIODIC_REG, offset 0x5), and an
      iwl_write32() to CSR_INT_PERIODIC_REG could clobber the lowest byte of the
      next-higher register (CSR_INT, offset 0x8).
      
      Fortunately, no bad side effects have been produced by the iwl_write32()
      usage, due to order of execution (low order byte was always written before
      higher order byte), and the fact that writing "0" to the low byte of the
      next higher register has no effect (only action is when writing "1"s).
      
      Nonetheless, this cleans up the accesses so no bad side effects might occur
      in the future, if execution order changes, or more bit fields get added to
      CSR_INT_COALESCING.
      
      Add some comments regarding periodic interrupt usage.
      Signed-off-by: NBen Cahill <ben.m.cahill@intel.com>
      Signed-off-by: NReinette Chatre <reinette.chatre@intel.com>
      Signed-off-by: NJohn W. Linville <linville@tuxdriver.com>
      74ba67ed
  19. 19 11月, 2009 1 次提交
  20. 28 10月, 2009 2 次提交
  21. 08 10月, 2009 1 次提交
  22. 05 8月, 2009 1 次提交
  23. 23 5月, 2009 4 次提交
  24. 22 4月, 2009 1 次提交
  25. 17 3月, 2009 1 次提交
  26. 10 2月, 2009 1 次提交
  27. 30 1月, 2009 1 次提交
  28. 13 12月, 2008 2 次提交
  29. 01 11月, 2008 1 次提交
  30. 01 10月, 2008 1 次提交
  31. 05 8月, 2008 1 次提交
  32. 04 6月, 2008 1 次提交
  33. 08 5月, 2008 2 次提交