While the supported UHS mode can be obtained from CAPA2
register, SD Host Controller Standard Specification
doesn't define bits for MMC's HS200 and DDR mode capability.
Add properties to indicate MMC HS200 and DDR speed mode capability in
dt node.
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>

Use sdhci-omap programming model based on the generic sdhci
library for programming the eMMC/SD/SDIO controller.
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>

The "cooling-min-level" and "cooling-max-level" properties are not
parsed by any part of the kernel currently and the max cooling state of
a CPU cooling device is found by referring to the cpufreq table instead.

Remove the unused properties from the CPU nodes.
Signed-off-by: NViresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: NTony Lindgren <tony@atomide.com>

On dra7, as per TRM, the HW shutdown (TSHUT) temperature is hardcoded
to 123C and cannot be modified by SW. This means that when the temperature
reaches 123C HW asserts TSHUT output which signals a warm reset.
The reset is held until the temperature goes below the TSHUT low (105C).

While in SW, the thermal driver continuously monitors current temperature
and takes decisions based on whether it reached an alert or a critical point.
The intention of setting a SW critical point is to prevent force reset by HW
and instead do an orderly_poweroff(). But if the SW critical temperature is
greater than or equal to that of HW then it defeats the purpose. To address
this and let SW take action before HW does keep the SW critical temperature
less than HW TSHUT value.

The value for SW critical temperature was chosen as 120C just to ensure
we give SW sometime before HW catches up.

Document reference
SPRUI30C – DRA75x, DRA74x Technical Reference Manual - November 2016
SPRUHZ6H - AM572x Technical Reference Manual - November 2016

Tested on:
DRA75x PG 2.0 Rev H EVM
Signed-off-by: NRavikumar Kattekola <rk@ti.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>

Let's update the existing users with features and clock data as
specified in the binding. This is currently the smartreflex for most
part, and also few omap4 modules with no child device driver like
mcasp, abe iss and gfx.

Note that we had few mistakes that did not get noticed as we're still
probing the SmartReflex driver with legacy platform data and using
"ti,hwmods" legacy property for ti-sysc driver.

So let's fix the omap4 and dra7 smartreflex registers as there is no
no revision register.

And on omap4, the mcasp module has a revision register according to
the TRM.

And for omap34xx we need a different configuration compared to 36xx.
And the smartreflex on 3517 we've always kept disabled so let's
remove any references to it.
Signed-off-by: NTony Lindgren <tony@atomide.com>

This reverts commit 4ece93c0.

The device tree binding for these is still being discussed.
Signed-off-by: NTony Lindgren <tony@atomide.com>

After ti-opp-supply driver is in place to provide AVS Class0 and abb
regulator scaling support let's enable 1.5GHz for the cpu.
Signed-off-by: NDave Gerlach <d-gerlach@ti.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>

Add the OPP supply node for the MPU voltage rail to provide the
information needed by the ti-opp-supply driver to enable AVS Class 0.
Signed-off-by: NDave Gerlach <d-gerlach@ti.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>

Add a vbb-supply phandle to the cpus node and also add an additional
triplet of voltages for each OPP in the operating-points-v2 table to
make use of the multi regulator support in the OPP core and provide the
vbb regulator for use by the ti-opp-supply driver.
Signed-off-by: NDave Gerlach <d-gerlach@ti.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>

Otherwise we cannot use generic OF_DEV_AUXDATA match without listing
all the compatibles separately for OF_DEV_AUXDATA. Let's also update the
binding accordingly.

Let's also fix omap4.dtsi to use "ti,sysc-omap4-sr" compatible as we
have documented in the binding. This was not noticed earlier as we're
still probing SmartReflex driver with platform data.
Reviewed-by: NRob Herring <robh@kernel.org>
Signed-off-by: NTony Lindgren <tony@atomide.com>

Since SoC specific compatible strings are used for PCIe in
dra74x.dtsi and dra72x.dtsi, remove the compatible property
from dra7.dtsi which uses the deprecated compatible string.
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: NSekhar Nori <nsekhar@ti.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>

Use dra74 specific compatible string for PCIe while preserving
the older compatible. While at that add a new label for the
2nd instance of pcie.
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: NSekhar Nori <nsekhar@ti.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>

ti,syscon-lane-sel and ti,syscon-lane-conf properties specific to enable
PCIe x2 lane mode are added here.
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: NSekhar Nori <nsekhar@ti.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>

Improve the DTS files by removing all the leading "0x" and zeros to fix the
following dtc warnings:

Warning (unit_address_format): Node /XXX unit name should not have
leading "0x"

and

Warning (unit_address_format): Node /XXX unit name should not have
leading 0s

Converted using the following command:

$ find . -type f \( -iname *.dts -o -iname *.dtsi \) -exec \
sed -i -e "s/@\([0-9a-fA-FxX\.;:#]+\)\s*{/@\L\1 {/g" \
-e "s/@0x\(.*\) {/@\1 {/g" -e "s/@0+\(.*\) {/@\1 {/g" {} +^C

For simplicity, two sed expressions were used to solve each warnings
separately.

To make the regex expression more robust a few other issues were resolved,
namely setting unit-address to lower case, and adding a whitespace before
the the opening curly brace:

https://elinux.org/Device_Tree_Linux#Linux_conventions

This will solve as a side effect warning:

Warning (simple_bus_reg): Node /XXX@<UPPER> simple-bus unit address format
error, expected "<lower>"

This is a follow up to commit 4c9847b7 ("dt-bindings: Remove leading
0x from bindings notation")
Reported-by: NDavid Daney <ddaney@caviumnetworks.com>
Suggested-by: NRob Herring <robh@kernel.org>
Signed-off-by: NMathieu Malaterre <malat@debian.org>
Signed-off-by: NTony Lindgren <tony@atomide.com>

The audio DMA request for hdmi is crossbar 76 and we use sDMA
to handle the data transfer.
Signed-off-by: NPeter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>

The metastability workaround causes Erratic errors [1]
on the HighSpeed USB PHY which can cause upto 2 seconds
delay in enumerating to a USB host while in Gadget mode.

Disable the Run/Stop metastability workaround to avoid this
ill effect. We are aware that this opens up the opportunity
for Run/Stop metastability, however this issue has never been
observed in TI releases so we think that Run/Stop metastability
is a lesser evil than the PHY Erratic errors. So disable it.

[1] USB controller trace during gadget enumeration
    irq/90-dwc3-969   [000] d...    52.323145: dwc3_event: event
    (00000901): Erratic Error [U0]
    irq/90-dwc3-969   [000] d...    52.560646: dwc3_event: event
    (00000901): Erratic Error [U0]
    irq/90-dwc3-969   [000] d...    52.798144: dwc3_event: event
    (00000901): Erratic Error [U0]
Signed-off-by: NRoger Quadros <rogerq@ti.com>
Acked-by: NFelipe Balbi <felipe.balbi@linux/intel.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>

Add clkctrl nodes for DRA7 SoC. These are going to be acting as
replacement for part of the existing clock data and the existing
clkctrl hooks under hwmod data.

This patch also removes any obsolete clock nodes, and reroutes all users
for these to use the new clkctrl clocks instead.
Signed-off-by: NTero Kristo <t-kristo@ti.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>

Add simple-bus compatibility and ranges properties to cm1, cm2 and prm
nodes. This is done in preparation of adding the support for clkctrl
nodes.

SPLIT: timer1 fck setup
Signed-off-by: NTero Kristo <t-kristo@ti.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>

Add the functional clock definition for timer1. This is needed so that
the clock rate calculations continue to function properly once dra7
transitions away from hwmod data and towards the clkctrl clocks.
Signed-off-by: NTero Kristo <t-kristo@ti.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>

As per recent TRM, PBIAS cell on dra7 devices supports
3.3v and not 3.0v as documented earlier.

Update PBIAS regulator max voltage to match this.

Document reference:
SPRUI30C – DRA75x, DRA74x Technical reference manual- November 2016

Tested on:
DRA75x PG 2.0 REV H EVM
Signed-off-by: NRavikumar Kattekola <rk@ti.com>
Signed-off-by: NSekhar Nori <nsekhar@ti.com>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>

The TRM has marked dra7 SmartReflex as reserved and we should not
touch those registers as pointed out by Nishanth Menon <nm@ti.com>.
We do still want to idle the related interconnect target modules on
init though.

Let's do this by only configuring the generic interconnect target modules
and not add the child SmartReflex devices.

Cc: Lokesh Vutla <lokeshvutla@ti.com>
Cc: Nishanth Menon <nm@ti.com>
Cc: Paul Walmsley <paul@pwsan.com>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Tero Kristo <t-kristo@ti.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>

On dra7 we're missing two "ti,hwmods" properties that the SoC
interconnect code needs. For hdq 1-wire, we need to add the
node for that.

Note that this will only show up as a bug with "doesn't have
mpu register target base" boot errors when the legacy platform
data is removed.

Cc: Nishanth Menon <nm@ti.com>
Cc: Tero Kristo <t-kristo@ti.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>

Add pcie1 dt node in order for the controller to operate in
endpoint mode. However since none of the dra7 based boards have
slots configured to operate in endpoint mode, keep EP mode
disabled.
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>

Add dra7 iodelay configuration.
Signed-off-by: NTony Lindgren <tony@atomide.com>
Signed-off-by: NNishanth Menon <nm@ti.com>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

Add "max-frequency" property to MMC dt nodes and set the
maximum frequency to 192MHz for MMC1/MMC2, 64MHz for MMC3
and 192MHz for MMC4. pdata quirks must be utilized to
detect presence of rev 1.1/1.0 of silicon and adjust
maximum frequencies as per restrictions documented in i843.
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: NSekhar Nori <nsekhar@ti.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>

On dra7, as per TRM, the HW shutdown (TSHUT) temperature is hardcoded
to 123C and cannot be modified by SW. This means when the temperature
reaches 123C HW asserts TSHUT output which signals a warm reset.
This reset is held until the temperature goes below the TSHUT low (105C).

While in SW, the thermal driver continuously monitors current temperature
and takes decisions based on whether it reached an alert or a critical point.
The intention of setting a SW critical point is to prevent force reset by HW
and instead do an orderly_poweroff(). But if the SW critical temperature is
greater than or equal to that of HW then it defeats the purpose. To address
this and let SW take action before HW does keep the SW critical temperature
less than HW TSHUT value.

The value for SW critical temperature was chosen as 120C just to ensure
we give SW sometime before HW catches up.

Document reference
SPRUI30C – DRA75x, DRA74x Technical Reference Manual - November 2016
SPRUHZ6H - AM572x Technical Reference Manual - November 2016

Tested on:
DRA75x PG 2.0 Rev H EVM
Signed-off-by: NRavikumar Kattekola <rk@ti.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>

Compiling the DT file with W=1, DTC warns like follows:

Warning (unit_address_vs_reg): Node /opp_table0/opp@1000000000 has a
unit name, but no reg property

Fix this by replacing '@' with '-' as the OPP nodes will never have a
"reg" property.
Reported-by: NKrzysztof Kozlowski <krzk@kernel.org>
Reported-by: NMasahiro Yamada <yamada.masahiro@socionext.com>
Suggested-by: NMark Rutland <mark.rutland@arm.com>
Signed-off-by: NViresh Kumar <viresh.kumar@linaro.org>
Acked-by: NRob Herring <robh@kernel.org>
Acked-by: NTony Lindgren <tony@atomide.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>

Currently the slope and offset values for calculating the
hot spot temperature of a particular thermal zone is part
of driver data. Pass them here instead and obtain the values
while of node parsing.
Signed-off-by: NKeerthy <j-keerthy@ti.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>

After the ti-cpufreq driver has been added, we can now drop the
operating-points table present in dra7.dtsi for the cpu and add an
operating-points-v2 table with all OPPs available for all silicon
revisions. Also add necessary data for use by ti-cpufreq to selectively
enable the appropriate OPPs at runtime as part of the operating-points
table.

As we now need to define voltage ranges for each OPP, we define the
minimum and maximum voltage to match the ranges possible for AVS class0
voltage as defined by the DRA7/AM57 Data Manual, with the exception of
using a range for OPP_OD based on historical data to ensure that SoCs
from older lots still continue to boot, even though more optimal voltages
are now the standard. Once an AVS Class0 driver is in place it will be
possible for these OPP voltages to be adjusted to any voltage within the
provided range.

Information from SPRS953, Revised December 2015.
Signed-off-by: NDave Gerlach <d-gerlach@ti.com>
eviewed-by: NLukasz Majewski <lukma@denx.de>
Acked-by: NViresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: NTony Lindgren <tony@atomide.com>

dtc recently added PCI bus checks. Fix these warnings.
Signed-off-by: NRob Herring <robh@kernel.org>
Cc: "Benoît Cousson" <bcousson@baylibre.com>
Cc: Tony Lindgren <tony@atomide.com>
Cc: linux-omap@vger.kernel.org
Signed-off-by: NTony Lindgren <tony@atomide.com>

Since everybody copied my own mistake from the DT binding example,
let's address all the offenders in one swift go.

Most of them got the CPU interface size wrong (4kB, while it should
be 8kB), except for both keystone platforms which got the control
interface wrong (4kB instead of 8kB).

In a few cases where I knew for sure what implementation was used,
I've added the "arm,gic-400" compatible string. I'm 99% sure that
this is what everyone is using, but short of having the TRM for
all the other SoCs, I've left them alone.
Acked-by: NShawn Guo <shawnguo@kernel.org>
Acked-by: NTony Lindgren <tony@atomide.com>
Acked-by: NSantosh Shilimkar <ssantosh@kernel.org>
Acked-by: NKrzysztof Kozlowski <krzk@kernel.org>
Acked-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: NAntoine Tenart <antoine.tenart@free-electrons.com>
Acked-by: NArnd Bergmann <arnd@arndb.de>
Acked-by: NMatthias Brugger <matthias.bgg@gmail.com>
Acked-by: NHeiko Stuebner <heiko@sntech.de>
Reviewed-by: NJavier Martinez Canillas <javier@osg.samsung.com>
Signed-off-by: NMarc Zyngier <marc.zyngier@arm.com>
Signed-off-by: NArnd Bergmann <arnd@arndb.de>

AHCI provides the register PORTS_IMPL to let the software know which port
is supported. The register must be initialized by the bootloader. However
in some cases u-boot doesn't properly initialize this value (if it is not
compiled with SATA support for example or if the SATA initialization fails).
The DTS entry "ports-implemented" can be used to override the value in
PORTS_IMPL.

Without this patch the SATA will not work in the following two cases:

* if there has been a failure to initialize SATA in u-boot.

* if ahci_platform module has been removed and re-inserted. The reason is
  that the content of PORTS_IMPL is lost after the module is removed.
  I suspect that it's because the controller is reset by the hwmod.

Cc: <stable@vger.kernel.org> # v4.6+
Signed-off-by: NJean-Jacques Hiblot <jjhiblot@ti.com>
Acked-by: NRoger Quadros <rogerq@ti.com>
[tony@atomide.com: updated comments with what goes wrong]
Signed-off-by: NTony Lindgren <tony@atomide.com>

Even if no_bd_ram property is described in TI CPSW bindings the support for
it has never been introduced in CPSW driver, so there are no real users of
it. Hence, remove no_bd_ram property from documentation and DT files.

Cc: 'Rob Herring <robh+dt@kernel.org>'
Signed-off-by: NGrygorii Strashko <grygorii.strashko@ti.com>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>

Commit 55871eb6 ("ARM: dts: dra7: Remove skeleton.dtsi usage")
removed the skeleton.dtsi usage since we want to get rid of it.

But this can cause issues when booting a kernel with a boot-loader
that doesn't create a chosen node if this isn't present in the DTB
since the decompressor relies on a pre-existing chosen node to be
available to insert the command line and merge other ATAGS info.

Fixes: 55871eb6 ("ARM: dts: dra7: Remove skeleton.dtsi usage")
Reported-by: NPali Rohar <pali.rohar@gmail.com>
Signed-off-by: NJavier Martinez Canillas <javier@osg.samsung.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>

Drivers using pinctrl-single,pins have #pinctrl-cells = <1>, while
pinctrl-single,bits need #pinctrl-cells = <2>.

Note that this patch can be optionally applied separately from the
driver changes as the driver supports also the legacy binding without
#pinctrl-cells.
Acked-by: NRob Herring <robh@kernel.org>
Reviewed-by: NLinus Walleij <linus.walleij@linaro.org>
Signed-off-by: NTony Lindgren <tony@atomide.com>

This reverts commit f80bc97f.

The original commit updated the cpufreq operating points tables for
dra7xx but was merged before the driver making use of the node was
merged, which breaks the existing cpufreq implementation on the system,
so revert the patch until the ti-cpufreq driver is merged.
Signed-off-by: NDave Gerlach <d-gerlach@ti.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>

The skeleton.dtsi file was removed in ARM64 for different reasons as
explained in commit ("3ebee5a2 arm64: dts: kill skeleton.dtsi").

These also applies to ARM and it will also allow to get rid of the
following DTC warnings in the future:

"Node /memory has a reg or ranges property, but no unit name"

The disassembled DTB are almost the same besides an empty chosen
node being removed and nodes reordered, so it should not have
functional changes.
Signed-off-by: NJavier Martinez Canillas <javier@osg.samsung.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>

Current clocks tree definition for CPSW/CPTS doesn't
correspond TRM for dra7/am57 SoCs.

CPTS: has to be sourced from gmac_rft_clk_mux clock
CPSW: DPLL_GMAC -> CLKOUT_M2 -> GMAC_250M_CLK -> 1/2 ->
      -> GMAC_MAIN_CLK (125 MHZ)

Hence, correct clock tree for GMAC_MAIN_CLK and use proper
clock for CPTS. This also require updating of CPTS clock
multiplier.
Signed-off-by: NGrygorii Strashko <grygorii.strashko@ti.com>
Reviewed-by: NMugunthan V N <mugunthanvnm@ti.com>
Acked-by: NTero Kristo <t-kristo@ti.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>

Since DRA7 has multiple PCIe Rootcomplex, add "linux,pci-domain"
property to assign a PCI domain number to each of the host
bridges.
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>

Silicon limitation i845 documents how to cope with false
disconnection condition on USB2 PHY. Reference: AM572x
silicon errata document SPRZ429H, revised January 2016.

Using compatible "ti,dra7x-usb2" enables the recommended
software workaround for this issue. Use it for USB1 PHY.

The workaround is already in place for USB2 PHY.
Signed-off-by: NSekhar Nori <nsekhar@ti.com>
Signed-off-by: NRoger Quadros <rogerq@ti.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>