1. 05 4月, 2014 1 次提交
  2. 18 2月, 2014 1 次提交
  3. 20 1月, 2014 1 次提交
  4. 08 1月, 2014 1 次提交
  5. 08 10月, 2013 1 次提交
    • H
      dmaengine: add driver for Samsung s3c24xx SoCs · ddeccb8d
      Heiko Stuebner 提交于
      This adds a new driver to support the s3c24xx dma using the dmaengine
      and makes the old one in mach-s3c24xx obsolete in the long run.
      
      Conceptually the s3c24xx-dma feels like a distant relative of the pl08x
      with numerous virtual channels being mapped to a lot less physical ones.
      The driver therefore borrows a lot from the amba-pl08x driver in this
      regard. Functionality-wise the driver gains a memcpy ability in addition
      to the slave_sg one.
      
      The driver supports both the method for requesting the peripheral used
      by SoCs before the S3C2443 and the different method for S3C2443 and later.
      
      On earlier SoCs the hardware channels usable for specific peripherals is
      constrainted while on later SoCs all channels can be used for any peripheral.
      
      Tested on a s3c2416-based board, memcpy using the dmatest module and
      slave_sg partially using the spi-s3c64xx driver.
      Signed-off-by: NHeiko Stuebner <heiko@sntech.de>
      Acked-by: NLinus Walleij <linus.walleij@linaro.org>
      Acked-by: NVinod Koul <vinod.koul@intel.com>
      Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>
      ddeccb8d
  6. 28 8月, 2013 1 次提交
  7. 09 8月, 2013 1 次提交
    • S
      usb: musb dma: add cppi41 dma driver · 9b3452d1
      Sebastian Andrzej Siewior 提交于
      This driver is currently used by musb' cppi41 couter part. I may merge
      both dma engine user of musb at some point but not just yet.
      
      The driver seems to work in RX/TX mode in host mode, tested on mass
      storage. I increaed the size of the TX / RX transfers and waited for the
      core code to cancel a transfers and it seems to recover.
      
      v2..3:
      - use mall transfers on RX side and check data toggle.
      - use rndis mode on tx side so we haveon interrupt for 4096 transfers.
      - remove custom "transferred" hack and use dmaengine_tx_status() to
        compute the total amount of data that has been transferred.
      - cancel transfers and reclaim descriptors
      
      v1..v2:
      - RX path added
      - dma mode 0 & 1 is working
      - device tree nodes re-created.
      
      Cc: Vinod Koul <vinod.koul@intel.com>
      Cc: Dan Williams <djbw@fb.com>
      Signed-off-by: NSebastian Andrzej Siewior <bigeasy@linutronix.de>
      Signed-off-by: NFelipe Balbi <balbi@ti.com>
      9b3452d1
  8. 05 7月, 2013 3 次提交
  9. 30 4月, 2013 1 次提交
  10. 16 4月, 2013 1 次提交
    • A
      dma: acpi-dma: introduce ACPI DMA helpers · 1b2e98bc
      Andy Shevchenko 提交于
      There is a new generic API to get a DMA channel for a slave device (commit
      9a6cecc8 "dmaengine: add helper function to request a slave DMA channel"). In
      similar fashion to the DT case (commit aa3da644 "of: Add generic device tree
      DMA helpers") we introduce helpers to the DMAC drivers which are enumerated by
      ACPI.
      
      The proposed extension provides the following API calls:
      	acpi_dma_controller_register(), devm_acpi_dma_controller_register()
      	acpi_dma_controller_free(), devm_acpi_dma_controller_free()
      	acpi_dma_simple_xlate()
      	acpi_dma_request_slave_chan_by_index()
      	acpi_dma_request_slave_chan_by_name()
      
      The first two should be used, for example, at probe() and remove() of the
      corresponding DMAC driver. At the register stage the DMAC driver supplies a
      custom xlate() function to translate a struct dma_spec into struct dma_chan.
      
      Accordingly to the ACPI Fixed DMA resource specification the only two pieces of
      information the slave device has are the channel id and the request line (slave
      id). Those two are represented by struct dma_spec. The
      acpi_dma_request_slave_chan_by_index() provides access to the specifix FixedDMA
      resource by its index. Whereas dma_request_slave_channel() takes a string
      parameter to identify the DMA resources required by the slave device. To make a
      slave device driver work with both DeviceTree and ACPI enumeration a simple
      convention is established: "tx" corresponds to the index 0 and "rx" to the
      index 1. In case of robust configuration the slave device driver unfortunately
      needs to call acpi_dma_request_slave_chan_by_index() directly.
      
      Additionally the patch provides "managed" version of the register/free pair
      i.e. devm_acpi_dma_controller_register() and devm_acpi_dma_controller_free().
      Usually, the driver uses only devm_acpi_dma_controller_register().
      Signed-off-by: NAndy Shevchenko <andriy.shevchenko@linux.intel.com>
      Reviewed-by: NMika Westerberg <mika.westerberg@linux.intel.com>
      Acked-by: NRafael J. Wysocki <rafael.j.wysocki@intel.com>
      Signed-off-by: NVinod Koul <vinod.koul@intel.com>
      1b2e98bc
  11. 14 2月, 2013 1 次提交
  12. 03 1月, 2013 1 次提交
  13. 14 9月, 2012 1 次提交
    • Z
      dmaengine: mmp-pdma support · c8acd6aa
      Zhangfei Gao 提交于
      1. virtual channel vs. physical channel
      Virtual channel is managed by dmaengine
      Physical channel handling resource, such as irq
      Physical channel is alloced dynamically as descending priority,
      freed immediately when irq done.
      The availble highest priority physically channel will alwayes be alloced
      
      Issue pending list -> alloc highest dma physically channel available -> dma done -> free physically channel
      
      2. list: running list & pending list
      submit: desc list -> pending list
      issue_pending_list: if (IDLE) pending list -> running list; free pending list (RUN)
      irq: free running list (IDLE)
           check pendlist -> pending list -> running list; free pending list (RUN)
      
      3. irq:
      Each list generate one irq, calling callback
      One list may contain several desc chain, in such case, make sure only the last desc list generate irq.
      
      4. async
      Submit will add desc chain to pending list, which can be multi-called
      If multi desc chain is submitted, only the last desc would generate irq -> call back
      If IDLE, issue_pending_list start pending_list, transforming pendlist to running list
      If RUN, irq will start pending list
      
      5. test
      5.1 pxa3xx_nand on pxa910
      5.2 insmod dmatest.ko (threads_per_chan=y)
      By default drivers/dma/dmatest.c test every channel and test memcpy with 1 threads per channel
      Signed-off-by: NZhangfei Gao <zhangfei.gao@marvell.com>
      Acked-by: NArnd Bergmann <arnd@arndb.de>
      Signed-off-by: NVinod Koul <vinod.koul@linux.intel.com>
      c8acd6aa
  14. 01 9月, 2012 1 次提交
  15. 31 7月, 2012 1 次提交
  16. 13 7月, 2012 1 次提交
  17. 01 7月, 2012 1 次提交
  18. 20 6月, 2012 1 次提交
  19. 08 6月, 2012 1 次提交
  20. 07 3月, 2012 1 次提交
    • R
      DMA: sa11x0: add SA-11x0 DMA driver · 6365bead
      Russell King 提交于
      Add support for the SA-11x0 DMA driver, which replaces the private
      API version in arch/arm/mach-sa1100/dma.c.
      
      We model this as a set of virtual DMA channels, one for each request
      signal, and assign the virtual DMA channel to a physical DMA channel
      when there is work to be done.  This allows DMA users to claim their
      channels, and hold them while not in use, without affecting the
      availability of the physical channels.
      
      Another advantage over this approach, compared to the private version,
      is that a channel can be reconfigured on the fly without having to
      release and re-request it - which for the IrDA driver, allows us to
      use DMA for SIR mode transmit without eating up three physical
      channels.  As IrDA is half-duplex, we actually only need one physical
      channel, and this architecture allows us to achieve that.
      Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
      6365bead
  21. 18 11月, 2011 1 次提交
  22. 09 6月, 2011 1 次提交
  23. 06 6月, 2011 1 次提交
  24. 17 3月, 2011 1 次提交
  25. 02 3月, 2011 1 次提交
    • S
      dmaengine: mxs-dma: add dma support for i.MX23/28 · a580b8c5
      Shawn Guo 提交于
      This patch adds dma support for Freescale MXS-based SoC i.MX23/28,
      including apbh-dma and apbx-dma.
      
      * apbh-dma and apbx-dma are supported in the driver as two mxs-dma
        instances.
      
      * apbh-dma is different between mx23 and mx28, hardware version
        register is used to differentiate.
      
      * mxs-dma supports pio function besides data transfer.  The driver
        uses dma_data_direction DMA_NONE to identify the pio mode, and
        steals sgl and sg_len to get pio words and numbers from clients.
      
      * mxs dmaengine has some very specific features, like sense function
        and the special NAND support (nand_lock, nand_wait4ready).  These
        are too specific to implemented in generic dmaengine driver.
      
      * The driver refers to imx-sdma and only a single descriptor is
        statically assigned to each channel.
      Signed-off-by: NShawn Guo <shawn.guo@freescale.com>
      Signed-off-by: NVinod Koul <vinod.koul@intel.com>
      a580b8c5
  26. 03 12月, 2010 1 次提交
  27. 08 10月, 2010 1 次提交
  28. 06 10月, 2010 1 次提交
    • S
      dmaengine: Add Freescale i.MX SDMA support · 1ec1e82f
      Sascha Hauer 提交于
      This patch adds support for the Freescale i.MX SDMA engine.
      
      The SDMA engine is a scatter/gather DMA engine which is implemented
      as a seperate coprocessor. SDMA needs its own firmware which is
      requested using the standard request_firmware mechanism. The firmware
      has different entry points for each peripheral type, so drivers
      have to pass the peripheral type to the DMA engine which in turn
      picks the correct firmware entry point from a table contained in
      the firmware image itself.
      The original Freescale code also supports support for transfering
      data to the internal SRAM which needs different entry points to
      the firmware. Support for this is currently not implemented. Also,
      support for the ASRC (asymmetric sample rate converter) is skipped.
      
      I took a very simple approach to implement dmaengine support. Only
      a single descriptor is statically assigned to a each channel. This
      means that transfers can't be queued up but only a single transfer
      is in progress. This simplifies implementation a lot and is sufficient
      for the usual device/memory transfers.
      Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>
      Reviewed-by: NLinus Walleij <linus.ml.walleij@gmail.com>
      Signed-off-by: NDan Williams <dan.j.williams@intel.com>
      1ec1e82f
  29. 30 9月, 2010 1 次提交
    • L
      dmaengine: driver for the ARM PL080/PL081 PrimeCells v5 · e8689e63
      Linus Walleij 提交于
      This creates a DMAengine driver for the ARM PL080/PL081 PrimeCells
      based on the implementation earlier submitted by Peter Pearse.
      This is working like a charm for memcpy and slave DMA to the PL011
      PrimeCell on the PB11MPCore.
      
      This DMA controller is used in mostly unmodified form in the ARM
      RealView and Versatile platforms, in the ST-Ericsson Nomadik, and
      in the ST SPEAr platform.
      
      It has been converted to use the header from the Samsung PL080
      derivate instead of its own defintions. The Samsungs have a custom
      driver in their mach-* folders though, atleast we can share the
      register definitions.
      
      Cc: Peter Pearse <peter.pearse@arm.com>
      Cc: Ben Dooks <ben-linux@fluff.org>
      Cc: Kukjin Kim <kgene.kim@samsung.com>
      Cc: Alessandro Rubini <rubini@unipv.it>
      Acked-by: NViresh Kumar <viresh.kumar@st.com>
      Signed-off-by: NLinus Walleij <linus.walleij@stericsson.com>
      [GFP_KERNEL to GFP_NOWAIT in pl08x_prep_dma_memcpy]
      Signed-off-by: NDan Williams <dan.j.williams@intel.com>
      e8689e63
  30. 05 8月, 2010 1 次提交
  31. 28 7月, 2010 1 次提交
    • V
      intel_mid: Add Mrst & Mfld DMA Drivers · b3c567e4
      Vinod Koul 提交于
      This patch add DMA drivers for DMA controllers in Langwell chipset
      of Intel(R) Moorestown platform and DMA controllers in Penwell of
      Intel(R) Medfield platfrom
      
      This patch adds support for Moorestown DMAC1 and DMAC2 controllers.
      It also add support for Medfiled GP DMA and DMAC1 controllers.
      These controllers supports memory to peripheral and peripheral to
      memory transfers. It support only single block transfers.
      
      This driver is based on Kernel DMA engine
      Anyone who wishes to use this controller should use DMA engine APIs
      
      This controller exposes DMA_SLAVE capabilities and notifies the client drivers
      of DMA transaction completion
      
      Config option required to be enabled CONFIG_INTEL_MID_DMAC=y
      Signed-off-by: NVinod Koul <vinod.koul@intel.com>
      Signed-off-by: NAlan Cox <alan@linux.intel.com>
      Signed-off-by: NDan Williams <dan.j.williams@intel.com>
      b3c567e4
  32. 24 5月, 2010 1 次提交
  33. 15 4月, 2010 1 次提交
  34. 26 3月, 2010 1 次提交
  35. 02 3月, 2010 2 次提交
  36. 12 12月, 2009 1 次提交
  37. 20 11月, 2009 1 次提交