1. 30 4月, 2015 7 次提交
  2. 10 4月, 2015 1 次提交
  3. 08 4月, 2015 1 次提交
  4. 04 4月, 2015 1 次提交
  5. 20 3月, 2015 2 次提交
  6. 13 3月, 2015 2 次提交
  7. 12 3月, 2015 1 次提交
    • J
      usb: dwc2: pci: Add device mode to the dwc2-pci driver · 9024c495
      John Youn 提交于
      The pci driver now registers a platform driver, like in dwc3, and lets
      its probe function do all the initialization. This allows it to
      account for changes to the platform driver that were not added to the
      pci driver. Also future changes to the probe function don't have to be
      duplicated. This also has the effect of adding device and DRD mode to
      the pci driver. Tested on the Synopsys HAPS PCIe platform.
      Signed-off-by: NJohn Youn <johnyoun@synopsys.com>
      Signed-off-by: NFelipe Balbi <balbi@ti.com>
      9024c495
  8. 11 3月, 2015 2 次提交
  9. 05 2月, 2015 1 次提交
    • R
      usb: dwc2: Fix a bug in reading the endpoint directions from reg. · 251a17f5
      Roshan Pius 提交于
      According to  the DWC2 datasheet, the HWCFG1 register stores
      the configured endpoint directions for endpoints 0-15 in bit positions
      0-31.
      ==========================
      Endpoint Direction (EpDir)
      This 32-bit field uses two bits per endpoint to determine the endpoint
      direction.
      Endpoint
      Bits [31:30]: Endpoint 15 direction
      Bits [29:28]: Endpoint 14 direction
      ....
      Bits [3:2]: Endpoint 1 direction
      Bits[1:0]: Endpoint 0 direction (always BIDIR)
      ==========================
      
      The DWC2 driver is currently interpreting the contents of the register
      as directions for endpoints 1-15 which leads to an error in determining
      the configured endpoint directions in the core because the first 2 bits
      determine the direction of endpoint 0 and not 1.
      
      This is based on testing/next branch in Felipe's git.
      Signed-off-by: NRoshan Pius <rpius@chromium.org>
      Acked-by: NJohn Youn <johnyoun@synopsys.com>
      Signed-off-by: NFelipe Balbi <balbi@ti.com>
      251a17f5
  10. 31 1月, 2015 13 次提交
  11. 25 1月, 2015 1 次提交
  12. 20 1月, 2015 2 次提交
  13. 19 1月, 2015 1 次提交
  14. 13 1月, 2015 5 次提交