NVIDIA's Tegra has multiple UART controller which supports:
- APB DMA based controller fifo read/write.
- End Of Data interrupt in incoming data to know whether end
  of frame achieve or not.
- HW controlled RTS and CTS flow control to reduce SW overhead.

Add serial driver to use all above feature.
Signed-off-by: NLaxman Dewangan <ldewangan@nvidia.com>
Acked-by: NAlan Cox <alan@linux.intel.com>
Reviewed-by: NStephen Warren <swarren@nvidia.com>
Signed-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>