Cc: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

Merge tag 'clk-hisilicon' of git://git.kernel.org/pub/scm/linux/kernel/git/hzhuang1/linux into clk-next-hisilicon

MSTP clocks are gate clocks controlled through a register that handles
up to 32 clocks. The register is often sparsely populated.

Those clocks are found on Renesas ARM SoCs.
Signed-off-by: NLaurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

DIV6 clocks are divider gate clocks controlled through a single
register. The divider is expressed on 6 bits, hence the name, and can
take values from 1/1 to 1/64.

Those clocks are found on Renesas ARM SoCs.
Signed-off-by: NLaurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

The R-Car Gen2 SoCs (R8A7790 and R8A7791) have several clocks that are
too custom to be supported in a generic driver. Those clocks can be
divided in two categories:

- Fixed rate clocks with multiplier and divisor set according to boot
  mode configuration

- Custom divider clocks with SoC-specific divider values

This driver supports both.
Signed-off-by: NLaurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: NKumar Gala <galak@codeaurora.org>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

Add missing CLK_SET_RATE_PARENT flag for gate clock.
Signed-off-by: NHaojian Zhuang <haojian.zhuang@gmail.com>

The flags on dividers should be CLK_DIVIDER_HIWORD_MASK, not
CLK_MUX_HIWORD_MASK.
Signed-off-by: NHaojian Zhuang <haojian.zhuang@gmail.com>

Fixes cpll control and lock register offset values for Exynos5420 SoC.
Signed-off-by: NChander Kashyap <chander.kashyap@linaro.org>
Acked-by: NKukjin Kim <kgene.kim@samsung.com>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

Enable common clock driver of Hi3620 SoC. clkgate-seperated driver is
used to support the clock gate that enable/disable/status registers
are seperated.
Signed-off-by: NHaojian Zhuang <haojian.zhuang@gmail.com>

Merge branch 'clk-tegra-next' of git://nv-tegra.nvidia.com/user/pdeschrijver/linux into clk-next-tegra

Allwinner sunXi SoCs clock changes

Those are mostly random fixes, except for one patch to the composite
clock that adds support for automatic reparenting.

Conflicts:
	drivers/clk/sunxi/clk-sunxi.c

In case of error, the function __clk_lookup() returns NULL pointer
not ERR_PTR(). The IS_ERR() test in the return value check should
be replaced with NULL test.
Signed-off-by: NWei Yongjun <yongjun_wei@trendmicro.com.cn>
Signed-off-by: NPeter De Schrijver <pdeschrijver@nvidia.com>

clk_round_rate() can be used by drivers to determine whether or not a
frequency is supported by the clock. The current Tegra clock driver
outputs an error message and a stacktrace when the requested rate isn't
supported. That's fine for clk_set_rate(), but it's confusing when all
the driver does is query whether or not a frequency is supported.
Signed-off-by: NThierry Reding <treding@nvidia.com>

The function socfpga_clk_init() can support clocks that do not have a divider
register, but a fixed-divider that can be read from DTS. Therefore, the "reg"
property is not a failing condition for socfpga_clk_init().
Signed-off-by: NDinh Nguyen <dinguyen@altera.com>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

The required properties are not named "div" and "mult",
but rather "clock-div" and "clock-mult".
Signed-off-by: NEzequiel Garcia <ezequiel.garcia@free-electrons.com>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

[Maybe the third time will be the charm. -Alex]

If CONFIG_COMMON_CLK_DEBUG is defined, clk_debug_create_one() is
called to populate a debugfs directory with a few entries that are
common for all clock types.

If an error happens after creating the first one debugfs_remove() is
called on the clock's directory.  The problem with this is that no
cleanup is done on the debugfs files already created in that
directory, so the directory never actually gets removed.   This
problem is silently ignored.

Fix this by calling debugfs_remove_recursive() instead.  Reset the
clk->dentry field to null afterward, to ensure it can't be mistaken
as a valid pointer.
Signed-off-by: NAlex Elder <elder@linaro.org>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

The low-power DSI clocks are used during host-driven transactions on the
DSI bus. Documentation recommends that they be children of PLLP and run
at a frequency of at least 52 MHz.
Signed-off-by: NThierry Reding <treding@nvidia.com>

This clock is needed to ensure the FUSE registers can be accessed
without freezing the system.
Signed-off-by: NAlexandre Courbot <acourbot@nvidia.com>

The clock for the PWM controller is slightly different from other
peripheral clocks on Tegra30. The clock source mux field start at
bit position 28 rather than 30.
Signed-off-by: NThierry Reding <treding@nvidia.com>

There are two GPUs on Tegra30 and each of them uses a separate clock, so
the secondary clock needs to be initialized in order for the gr3d module
to work properly.
Signed-off-by: NThierry Reding <treding@nvidia.com>

Add disp1 and disp2 clocks to the clock initialization table. These
clocks are required for display and HDMI support.
Signed-off-by: NMikko Perttunen <mperttunen@nvidia.com>
Signed-off-by: NThierry Reding <treding@nvidia.com>

Adding suspend/resume function for tegra_cpu_car_ops. We only save and
restore the setting of the clock of CoreSight. Other clocks still need
to be taken care by clock driver.

Cc: Mike Turquette <mturquette@linaro.org>
Signed-off-by: NJoseph Lo <josephl@nvidia.com>
Acked-by: NStephen Warren <swarren@nvidia.com>

Hook the functions for CPU hotplug support. After the CPU is hot
unplugged, the flow controller will handle to clock gate the CPU clock.
But still need to implement an empty function to avoid warning message.

Cc: Mike Turquette <mturquette@linaro.org>
Signed-off-by: NJoseph Lo <josephl@nvidia.com>

Implement clock support for Tegra124.
Signed-off-by: NPeter De Schrijver <pdeschrijver@nvidia.com>

Tegra124 introduces a number of new peripheral clocks. This patch adds those
to the common peripheral clock code.
Signed-off-by: NPeter De Schrijver <pdeschrijver@nvidia.com>

Tegra124 introduces a number of a new clocks. Introduce the corresponding
the IDs for them.
Signed-off-by: NPeter De Schrijver <pdeschrijver@nvidia.com>

Tegra124 has a clock which consists of a mux and a fractional divider.
Add support for this.
Signed-off-by: NPeter De Schrijver <pdeschrijver@nvidia.com>
Signed-off-by: NThierry Reding <treding@nvidia.com>

Tegra124 has periph clocks which share the hw register. Hence locking is
required.
Signed-off-by: NPeter De Schrijver <pdeschrijver@nvidia.com>
Signed-off-by: NThierry Reding <treding@nvidia.com>

Tegra124 has an extra bank of peripheral clock registers. Add it to the
generic peripheral clock code.
Signed-off-by: NPeter De Schrijver <pdeschrijver@nvidia.com>

Tegra124 introduces a new PLL type, PLLSS. Add support for it.
Signed-off-by: NPeter De Schrijver <pdeschrijver@nvidia.com>

Move tegra20 to common tegra clock infrastructure.
Signed-off-by: NPeter De Schrijver <pdeschrijver@nvidia.com>

Move tegra30 to common tegra clock infrastructure.
Signed-off-by: NPeter De Schrijver <pdeschrijver@nvidia.com>

Introduce a common function which performs super clock initialization for
Tegra114 and beyond.
Signed-off-by: NPeter De Schrijver <pdeschrijver@nvidia.com>

Introduce new files for fixed and PMC clocks common between several Tegra
SoCs and move Tegra114 to this new infrastructure.
Signed-off-by: NPeter De Schrijver <pdeschrijver@nvidia.com>

Introduce a new file for peripheral clocks common between several Tegra
SoCs and move Tegra114 to this new infrastructure. Also PLLP and the PLLP_OUT
clocks will be initialized here.
Signed-off-by: NPeter De Schrijver <pdeschrijver@nvidia.com>

Move audio clocks and PLLA initialization to a common file so it can be used by
multiple Tegra SoCs. Also a new array tegra114_clks is introduced for Tegra114
which specifies which common clocks are available on Tegra114 and what their
DT IDs are.
Signed-off-by: NPeter De Schrijver <pdeschrijver@nvidia.com>

Add a common infra for registering clkdev. This allows decoupling clk
registration from clkdev registration.
Signed-off-by: NPeter De Schrijver <pdeschrijver@nvidia.com>

Introduce a common infrastructure for sharing clock initialization between
SoCs.
Signed-off-by: NPeter De Schrijver <pdeschrijver@nvidia.com>

Many clocks are common between several Tegra SoCs. Define an enum to list
them so we can move them to separate files which can be shared between
SoCs. Each SoC specific file will provide an array with the common clocks
which are present on the SoC and their DT binding ID.
Signed-off-by: NPeter De Schrijver <pdeschrijver@nvidia.com>