Add pins, groups, and functions for all SCIF serial ports on R-Car H3
ES2.0.

Extracted from a big patch in the BSP by Takeshi Kihara.
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>
Cc: Takeshi Kihara <takeshi.kihara.df@renesas.com>

The Pin Function Controller module in the R-Car H3 ES2.0 differs from
ES1.x in many ways.

The goal is twofold:
  1. Support both the ES1.x and ES2.0 SoC revisions in a single binary
     for now,
  2. Make it clear which code supports ES1.x, so it can easily be
     identified and removed later, when production SoCs are deemed
     ubiquitous.

Hence this patch:
  1. Extracts the support for R-Car H3 ES1.x into a separate file, as
     the differences are quite large,
  2. Adds code for detecting the SoC revision at runtime using the new
     soc_device_match() API, and selecting pinctrl tables for the actual
     SoC revision,
  3. Replaces the core register and bitfield definitions by their
     counterparts for R-Car H3 ES2.0.

The addition of pins, groups, and functions for the various on-chip
devices is left to subsequent patches.

The R-Car H3 ES2.0 register and bitfield definitions were extracted from
a patch in the BSP by Takeshi Kihara.
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>
Cc: Takeshi Kihara <takeshi.kihara.df@renesas.com>

Update the sh_pfc_soc_info pointer after calling the SoC-specific
initialization function, as it may have been updated to e.g. handle
different SoC revisions.  This makes sure the correct subdriver name is
printed later.

Fixes: 0c151062 ("sh-pfc: Add support for SoC-specific initialization")
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>

Somehow the QSPI and SCIF_CLK fragments were inserted at the wrong
positions.  Restore sort order (alphabetically, per group).
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>

Fix typos in hscif2_clk_b_mux[] and hscif4_ctrl_mux[].

Fixes: a56069c4 ("pinctrl: sh-pfc: r8a7795: Add HSCIF pins, groups, and functions")
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>

Add pin configuration support for Gyro-ADC, named ADI on r8a7791 SoC.
Signed-off-by: NJacopo Mondi <jacopo@jmondi.org>
Tested-by: NMarek Vasut <marek.vasut@gmail.com>
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>

Commit df61b366af26 ("pinctrl: core: Use delayed work for hogs") caused a
regression at least with sh-pfc that is also a GPIO controller as
noted by Geert Uytterhoeven <geert@linux-m68k.org>.

As the original pinctrl_register() has issues calling pin controller
driver functions early before the controller has finished registering,
we can't just revert commit df61b366af26. That would break the drivers
using GENERIC_PINCTRL_GROUPS or GENERIC_PINMUX_FUNCTIONS.

So let's fix the issue with the following steps as a single patch:

1. Revert the late_init parts of commit df61b366af26.

   The late_init clearly won't work and we have to just give up
   on fixing pinctrl_register() for GENERIC_PINCTRL_GROUPS and
   GENERIC_PINMUX_FUNCTIONS.

2. Split pinctrl_register() into two parts

   By splitting pinctrl_register() into pinctrl_init_controller()
   and pinctrl_create_and_start() we have better control over when
   it's safe to call pinctrl_create().

3. Introduce a new pinctrl_register_and_init() function

   As suggested by Linus Walleij <linus.walleij@linaro.org>, we
   can just introduce a new function for the controllers that need
   pinctrl_create() called later.

4. Convert the four known problem cases to use new function

   Let's convert pinctrl-imx, pinctrl-single, sh-pfc and ti-iodelay
   to use the new function to fix the issues. The rest of the drivers
   can be converted later. Let's also update Documentation/pinctrl.txt
   accordingly because of the known issues with pinctrl_register().

Fixes: df61b366af26 ("pinctrl: core: Use delayed work for hogs")
Reported-by: NGeert Uytterhoeven <geert@linux-m68k.org>
Cc: Gary Bisson <gary.bisson@boundarydevices.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>
Tested-by: NGeert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Signed-off-by: NUlrich Hecht <ulrich.hecht+renesas@gmail.com>
[geert: Fix hscif2_clk_[bc]_mux[] and hscif4_ctrl_mux[]]
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>

Voltage switching is the same as on the r8a7791.
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>
Reviewed-by: NWolfram Sang <wsa+renesas@sang-engineering.com>
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>

This patch adds MSIOF{0,1,2,3} pins, groups and functions to R8A7796
SoC.
Signed-off-by: NTakeshi Kihara <takeshi.kihara.df@renesas.com>
[geert: Correct MSIOF3 SS1_E/SS2_E pins]
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>

This patch adds CAN FD[0-1] pinmux support to r8a7796 SoC.

Based on a patch for r8a7795 by Ramesh Shanmugasundaram.
Signed-off-by: NChris Paterson <chris.paterson2@renesas.com>
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>

This patch adds CAN[0-1] pinmux support to r8a7796 SoC.

Based on a patch for r8a7795 by Ramesh Shanmugasundaram.
Signed-off-by: NChris Paterson <chris.paterson2@renesas.com>
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>

There are pins on the r8a7795 which are not part of a GPIO bank nor
can be muxed between different functions. They do however allow for the
bias to be configured. Add those pins to the list of pins and
to the bias configuration array.

The pins can now be referred to in DT by function names and their bias
setting set.
Signed-off-by: NNiklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>

Implements pull-up and pull-down. On this SoC there is no simple mapping
of GP pins to bias register bits, so we need a table.
Signed-off-by: NNiklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>

Define the drive strength registers for the R8A7796. Add pins which are
not part of a GPIO bank nor can be muxed between different functions but
which still allow for their drive-strength to be configured.
Signed-off-by: NNiklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>

Group the QSPI0 and QSPI1 pins into similar groups found in other sh-pfc
drivers. The pins can not be muxed between functions other than QSPI,
but their drive strength can be controlled.
Signed-off-by: NNiklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>

Group the AVB pins into similar groups found in other sh-pfc drivers.
The pins can not be muxed between functions other then AVB but their
drive strength can be controlled.

The group avb_mdc containing ADV_MDC and ADV_MDIO are on other SoCs
called avb_mdio. In pfc-r8a7795 the avb_mdc group already existed and
is in use in DT. Therefore add the ADV_MDIO pin to the existing group
instead of renaming it.
Signed-off-by: NNiklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>

There are pins on the r8a7795 which are not part of a GPIO bank nor
can be muxed between different functions. They do however allow for the
drive-strength to be configured. Add those pins to the list of pins and
to the drive-strength configuration registers.

The pins can now be referred to in DT by function names and their
drive-strength modified.
Signed-off-by: NNiklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>

Pins not associated with a GPIO port can still have other configuration
parameters. Add a new macro SH_PFC_PIN_NAMED_CFG which allows for named
pins to be declared with a set of configurations. The new macro is an
modification of SH_PFC_PIN_NAMED to allow for optional configuration to
be assigned.

The flag SH_PFC_PIN_CFG_NO_GPIO is still enforced as this should only be
used to define pins not associated with a GPIO port.
Signed-off-by: NNiklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Acked-by: NLaurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>

Change the data structure and use the generic sh_pfc_pin_to_bias_info()
function to get the register offset and bit information.
Suggested-by: NLaurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: NNiklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Reviewed-by: NLaurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>

There is a bug in the r8a7795 bias code where a WARN() is trigged
anytime a pin from PUEN0/PUD0 is accessed.

 # cat /sys/kernel/debug/pinctrl/e6060000.pfc/pinconf-pins

 WARNING: CPU: 2 PID: 2391 at drivers/pinctrl/sh-pfc/pfc-r8a7795.c:5364 r8a7795_pinmux_get_bias+0xbc/0xc8
 [..]
 Call trace:
 [<ffff0000083c442c>] r8a7795_pinmux_get_bias+0xbc/0xc8
 [<ffff0000083c37f4>] sh_pfc_pinconf_get+0x194/0x270
 [<ffff0000083b0768>] pin_config_get_for_pin+0x20/0x30
 [<ffff0000083b11e8>] pinconf_generic_dump_one+0x168/0x188
 [<ffff0000083b144c>] pinconf_generic_dump_pins+0x5c/0x98
 [<ffff0000083b0628>] pinconf_pins_show+0xc8/0x128
 [<ffff0000081fe3bc>] seq_read+0x16c/0x420
 [<ffff00000831a110>] full_proxy_read+0x58/0x88
 [<ffff0000081d7ad4>] __vfs_read+0x1c/0xf8
 [<ffff0000081d8874>] vfs_read+0x84/0x148
 [<ffff0000081d9d64>] SyS_read+0x44/0xa0
 [<ffff000008082f4c>] __sys_trace_return+0x0/0x4

This is due to the WARN() check if the reg field of the pullups struct
is zero, and this should be 0 for pins controlled by the PUEN0/PUD0
registers since PU0 is defined as 0. Change the data structure and use
the generic sh_pfc_pin_to_bias_info() function to get the register
offset and bit information.

Fixes: 56065524 ("pinctrl: sh-pfc: r8a7795: Add bias pinconf support")
Signed-off-by: NNiklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Reviewed-by: NLaurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>

The last else statement is missing braces, and the indentation level can
be reduced.
Suggested-by: NLaurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: NNiklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Reviewed-by: NLaurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>

On some SoC there are no simple mapping of pins to bias register bits
and a lookup table is needed. This logic is already implemented in some
SoC specific drivers that could benefit from a generic implementation.

Add helpers to deal with the lookup which later can be used by the SoC
specific drivers. The logic used to lookup are different from the one it
aims to replace, this is intentional. This new method reduces the memory
consumption at the cost of increased CPU usage and fix a bug where a
WARN() would incorrectly be triggered if the register offset is 0.
Signed-off-by: NNiklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Reviewed-by: NLaurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>

Always stating PIN_CONFIG_BIAS_DISABLE is supported gives untrue output
when examining /sys/kernel/debug/pinctrl/e6060000.pfc/pinconf-pins if
the operation get_bias() is implemented but the pin is not handled by
the get_bias() implementation. In that case the output will state that
"input bias disabled" indicating that this pin has bias control
support.

Make support for PIN_CONFIG_BIAS_DISABLE depend on that the pin either
supports SH_PFC_PIN_CFG_PULL_UP or SH_PFC_PIN_CFG_PULL_DOWN. This also
solves the issue where SoC specific implementations print error messages
if their particular implementation of {set,get}_bias() is called with a
pin it does not know about.
Signed-off-by: NNiklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Acked-by: NLaurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>

Only the DU parallel RGB output signals are included, HDMI and TCON pins
will be added in separate groups. Based on a similar patch from Laurent
Pinchart for the r8a7795 PFC driver.
Signed-off-by: NNiklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Reviewed-by: NLaurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>

This patch adds AVB_LINK, AVB_MAGIC, AVB_PHY_INT, AVB_MDC, AVB_AVTP_PPS,
AVB_AVTP_MATCH, AVB_AVTP_CAPTURE pins, groups and functions to R8A7796
SoC.
Signed-off-by: NTakeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>

Fix off-by-one (row and/or register) errors in links to Peripheral
Function Select Register bitfields from GPIO/Peripheral Function Select
Register 4 macros for SDHI2 and SDHI3 pins.

Based on rev. 0.52E of the R-Car Gen3 User's Manual.
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>
Tested-by: NSimon Horman <horms+renesas@verge.net.au>

This patch adds DRIF[0-3] pinmux support for r8a7796 SoC.
Signed-off-by: NRamesh Shanmugasundaram <ramesh.shanmugasundaram@bp.renesas.com>
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>

Signed-off-by: NUlrich Hecht <ulrich.hecht+renesas@gmail.com>
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>

All the SHDIs can operate with either 3.3V or 1.8V signals, depending
on negotiation with the card.

Based on work by Wolfram Sang for the r8a7790.
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>
Acked-by: NWolfram Sang <wsa+renesas@sang-engineering.com>
Acked-by: NLinus Walleij <linus.walleij@linaro.org>
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>

All the SHDIs can operate with either 3.3V or 1.8V signals, depending
on negotiation with the card.

Based on work by Wolfram Sang for the r8a7790.
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>
Acked-by: NWolfram Sang <wsa+renesas@sang-engineering.com>
Acked-by: NLinus Walleij <linus.walleij@linaro.org>
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>

This follows the style of existing PORT_GP_X macros and
will be used by a follow-up patch for the r8a7791 SoC.
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>
Acked-by: NLinus Walleij <linus.walleij@linaro.org>
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>

This patch supports the {get,set}_io_voltage operations of SDHI.

This operates the POCCTRL0 register on R8A7796 SoC and makes 1.8v/3.3v
voltage switch.

Based on work by Takeshi Kihara and Wolfram Sang.

Cc: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>
Reviewed-by: NWolfram Sang <wsa+renesas@sang-engineering.com>
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>

The pinconf-generic code expects configurations with arguments to be
returned in a packed format in order to be displayed properly by
pinconf_generic_dump_one().

Reading /sys/kernel/debug/pinctrl/e6060000.pfc/pinconf-pins on
r8a7795/salvator-x now shows:

    pin 101 (GP_3_5): output drive strength (9 mA), pin power source (3300 selector)

Instead of:

    pin 101 (GP_3_5): output drive strength (0 mA), pin power source (0 selector)
Signed-off-by: NNiklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Tested-by: NGeert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>

Add MSIOF0/1 pin groups to the R8A7792 PFC driver.

Based  on the original (and large) patch by Vladimir Barinov
<vladimir.barinov@cogentembedded.com>.
Signed-off-by: NSergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>

Add QSPI pin groups to the R8A7792 PFC driver.

Based  on the original (and large) patch by Vladimir Barinov
<vladimir.barinov@cogentembedded.com>.
Signed-off-by: NSergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Acked-by: NLinus Walleij <linus.walleij@linaro.org>
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>

This patch adds SDHI pins, groups and functions to R8A7796 SoC.
Signed-off-by: NTakeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>

This patch adds SCIF{0,1,2,3,4,5} pins, groups and functions to R8A7796
SoC.
Signed-off-by: NTakeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>

This patch adds initial pinctrl driver to support for the R8A7796 SoC.
Signed-off-by: NTakeshi Kihara <takeshi.kihara.df@renesas.com>
[uli: rebased on top of renesas-drivers]
Signed-off-by: NUlrich Hecht <ulrich.hecht+renesas@gmail.com>
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>

Only the DU parallel RGB output signals are included, HDMI and TCON pins
will be added in separate groups.
Signed-off-by: NLaurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>