1. 30 8月, 2005 1 次提交
  2. 27 8月, 2005 2 次提交
  3. 25 8月, 2005 6 次提交
  4. 24 8月, 2005 1 次提交
  5. 19 8月, 2005 1 次提交
  6. 18 8月, 2005 3 次提交
  7. 13 8月, 2005 1 次提交
    • D
      [IA64] Fix race in mm-context wrap-around logic. · badea125
      David Mosberger-Tang 提交于
      The patch below should fix a race which could cause stale TLB entries.
      Specifically, when 2 CPUs ended up racing for entrance to
      wrap_mmu_context().  The losing CPU would find that by the time it
      acquired ctx.lock, mm->context already had a valid value, but then it
      failed to (re-)check the delayed TLB flushing logic and hence could
      end up using a context number when there were still stale entries in
      its TLB.  The fix is to check for delayed TLB flushes only after
      mm->context is valid (non-zero).  The patch also makes GCC v4.x
      happier by defining a non-volatile variant of mm_context_t called
      nv_mm_context_t.
      Signed-off-by: NDavid Mosberger-Tang <David.Mosberger@acm.org>
      Signed-off-by: NTony Luck <tony.luck@intel.com>
      badea125
  8. 12 8月, 2005 5 次提交
  9. 11 8月, 2005 2 次提交
    • C
      [IA64] Spinlock optimizations · f5210891
      Christoph Lameter 提交于
      1. Nontemporal store for spin unlock.
      
      A nontemporal store will not update the LRU setting for the cacheline. The
      cacheline with the lock may therefore be evicted faster from the cpu
      caches. Doing so may be useful since it increases the chance that the
      exclusive cache line has been evicted when another cpu is trying to
      acquire the lock.
      
      The time between dropping and reacquiring a lock on the same cpu is
      typically very small so the danger of the cacheline being
      evicted is negligible.
      
      2. Avoid semaphore operation in write_unlock and use nontemporal store
      
      write_lock uses a cmpxchg like the regular spin_lock but write_unlock uses
      clear_bit which requires a load and then a loop over a cmpxchg. The
      following patch makes write_unlock simply use a nontemporal store to clear
      the highest 8 bits. We will then still have the lower 3 bytes (24 bits)
      left to count the readers.
      
      Doing the byte store will reduce the number of possible readers from 2^31
      to 2^24 = 16 million.
      
      These patches were discussed already:
      
      http://marc.theaimsgroup.com/?t=111472054400001&r=1&w=2
      http://marc.theaimsgroup.com/?l=linux-ia64&m=111401837707849&w=2
      
      The nontemporal stores will only work using GCC. If a compiler is used
      that does not support inline asm then fallback C code is used. This
      will preserve the byte store but not be able to do the nontemporal stores.
      Signed-off-by: NChristoph Lameter <clameter@sgi.com>
      Signed-off-by: NTony Luck <tony.luck@intel.com>
      f5210891
    • K
      [IA64] fix iosapic_remove build error for !HOTPLUG · 1c53e435
      Kenji Kaneshige 提交于
      This patch removes the following stupid compile error that happens
      when CONFIG_HOTPLUG is not defined on ia64.
      
           arch/ia64/kernel/built-in.o(.text+0x712): In function `acpi_unregister_ioapic':
           : undefined reference to `iosapic_remove'
      Signed-off-by: NKenji Kaneshige <kaneshige.kenji@jp.fujitsu.com>
      Signed-off-by: NTony Luck <tony.luck@intel.com>
      1c53e435
  10. 28 7月, 2005 1 次提交
  11. 27 7月, 2005 1 次提交
    • E
      [PATCH] Add emergency_restart() · 7c903473
      Eric W. Biederman 提交于
      When the kernel is working well and we want to restart cleanly
      kernel_restart is the function to use.   But in many instances
      the kernel wants to reboot when thing are expected to be working
      very badly such as from panic or a software watchdog handler.
      
      This patch adds the function emergency_restart() so that
      callers can be clear what semantics they expect when calling
      restart.  emergency_restart() is expected to be callable
      from interrupt context and possibly reliable in even more
      trying circumstances.
      
      This is an initial generic implementation for all architectures.
      Signed-off-by: NEric W. Biederman <ebiederm@xmission.com>
      Signed-off-by: NLinus Torvalds <torvalds@osdl.org>
      7c903473
  12. 13 7月, 2005 3 次提交
    • C
      [IA64] Altix pcibus_to_node implementation · 7c2a6c62
      Christoph Lameter 提交于
      The Altix subarch does not provide node information via ACPI. Instead hooks
      are used to fixup pci structures. This patch determines the nodes for Altix
      PCI busses.
      
      Remote Bridges:
      ---------------
      Altix supports remote I/O nodes without memory or processors but with bridges.
      The TIOCA type of bridge is an AGP bridge and the PROM provides information
      about the closest node. That information will be returned by pcibus_to_node.
      
      The TIOCP remote bridge type is a PCI bridge but the PROM does not provide a
      closest node id. pcibus_to_node will return -1 for devices on those bridges
      meaning that device control structures may be allocated on any node.
      
      Safeguard:
      ----------
      Should the fixups result in invalid node information for a pci controller then
      a warning will be printed and pcibus_to_node will return -1.
      
      
      This patch also fixes the "FIXME" in sn_dma_alloc_coherent. This means that
      dma_alloc_coherent will now use alloc_pages_node to allocate memory local to
      the node that the PCI device is connected to.
      Signed-off-by: NChristoph Lameter <clameter@sgi.com>
      Signed-off-by: NTony Luck <tony.luck@intel.com>
      7c2a6c62
    • G
      [IA64] remove CONFIG_IA64_SGI_SN_SIM · 60a762b6
      Greg Edwards 提交于
      This patch removes the CONFIG_IA64_SGI_SN_SIM option entirely, allowing
      any kernel bootable on sn2 to also be booted in the simulator.
      
      Boot tested on Altix and HP rx2600.
      Signed-off-by: NGreg Edwards <edwardsg@sgi.com>
      Signed-off-by: NTony Luck <tony.luck@intel.com>
      60a762b6
    • C
      [IA64] pcibus_to_node implementation for IA64 · 514604c6
      Christoph Lameter 提交于
      pcibus_to_node provides a way for the Linux kernel to identify to which
      node a certain pcibus connects to. Allocations of control structures
      for devices can then be made on the node where the pci bus is located
      to allow local access during interrupt and other device manipulation.
      
      This patch provides a new "node" field in the the pci_controller
      structure. The node field will be set based on ACPI information (thanks
      to Alex Williamson  <alex.williamson@hp.com for that piece).
      Signed-off-by: NChristoph Lameter <clameter@sgi.com>
      Signed-off-by: NTony Luck <tony.luck@intel.com>
      514604c6
  13. 12 7月, 2005 4 次提交
  14. 07 7月, 2005 6 次提交
  15. 29 6月, 2005 3 次提交