The EDGE Port module of some ColdFire parts using the intc-simr interrupt
controller provides support for 7 external interrupts. These interrupts
go off-chip (that is they are not for internal peripherals). They need
some special handling and have some extra setup registers. Add code to
support them.
Signed-off-by: NGreg Ungerer <gerg@uclinux.org>

The EDGE Port module of some ColdFire parts using the intc-2 interrupt
controller provides support for 7 external interrupts. These interrupts
go off-chip (that is they are not for internal peripherals). They need
some special handling and have some extra setup registers. Add code to
support them.
Signed-off-by: NGreg Ungerer <gerg@uclinux.org>

The intc-simr interrupt controller on some ColdFire CPUs has a set range of
interrupts its supports (64 through 128 or 192 depending on model). We
shouldn't be setting this handler for every possible interrupt from 0 to
255. Set more appropriate limits, and this means we can drop the interrupt
number check in the mask and unmask routines.
Signed-off-by: NGreg Ungerer <gerg@uclinux.org>

Use a proper irq_startup() routine to intialize the interrupt priority
and level register in the ColdFire intc-2 controller code. We shouldn't
be checking if the priority/level has been set on every unmask operation.
Signed-off-by: NGreg Ungerer <gerg@uclinux.org>

The intc-2 interrupt controller on some ColdFire CPUs has a set range of
interrupts its supports (64 through 128 or 192 depending on model). We
shouldn't be setting this handler for every possible interrupt from 0 to
255. Set more appropriate limits, and this means we can drop the interrupt
number check in the mask and unmask routines.
Signed-off-by: NGreg Ungerer <gerg@uclinux.org>

In some of the RAM size autodetection code on ColdFire CPU startup
we reference DRAM registers relative to the MBAR register. Not all of
the supported ColdFire CPUs have an MBAR, and currently this works
because we fake an MBAR address on those registers. In an effort to
clean this up, and eventually remove the fake MBAR setting make the
DRAM register address definitions actually contain the MBAR (or IPSBAR
as appropriate) value as required.
Signed-off-by: NGreg Ungerer <gerg@uclinux.org>

Not all ColdFire CPUs that use the old style timer hardware module use
an MBAR set peripheral region. Move the TIMER base address defines to the
per-CPU header files where we can set it correctly based on how the
peripherals are mapped - instead of using a fake MBAR for some platforms.
Signed-off-by: NGreg Ungerer <gerg@uclinux.org>

The base addresses of the ColdFire DMA unit registers belong with
all the other address definitions in the per-cpu headers. The current
definitions assume they are relative to an MBAR register. Not all
ColdFire CPUs have an MBAR register. A clean address define can only
be acheived in the per-cpu headers along with all the other chips
peripheral base addresses.
Signed-off-by: NGreg Ungerer <gerg@uclinux.org>

The ColdFire 5207 and 5208 CPUs have fixed peripheral addresses.
They do not use the setable peripheral address registers like the MBAR
and IPSBAR used on many other ColdFire parts. Don't use fake values
of MBAR and IPSBAR when using peripheral addresses for them, there
is no need to.
Signed-off-by: NGreg Ungerer <gerg@uclinux.org>

The PIT hardware timer module used in some ColdFire CPU's is not always
addressed relative to an IPSBAR register. Parts like the ColdFire 5207 and
5208 have fixed peripheral addresses. So lets not define the register
addresses of the PIT relative to an IPSBAR definition. Move the base
address definitions into the per-part headers. This is a lot more consistent
since all the other peripheral base addresses are defined in the per-part
header files already.
Signed-off-by: NGreg Ungerer <gerg@uclinux.org>

The ColdFire 54xx family shares the same interrupt controller used
on the 523x, 527x and 528x ColdFire parts, but it isn't offset
relative to the IPSBAR register. The 54xx doesn't have an IPSBAR
register.

By including the base address of the peripheral registers in the register
definitions (MCFICM_INTC0 and MCFICM_INTC1 in this case) we can avoid
having to define a fake IPSBAR for the 54xx. And this makes the register
address definitions of these more consistent, the majority of the other
register address defines include the peripheral base address already.
Signed-off-by: NGreg Ungerer <gerg@uclinux.org>

Signed-off-by: NThomas Gleixner <tglx@linutronix.de>
Signed-off-by: NGreg Ungerer <gerg@uclinux.org>

Signed-off-by: NThomas Gleixner <tglx@linutronix.de>
Signed-off-by: NGreg Ungerer <gerg@uclinux.org>

Signed-off-by: NThomas Gleixner <tglx@linutronix.de>
Signed-off-by: NGreg Ungerer <gerg@uclinux.org>

The _TIF_WORK_MASK definition was removed in the clean up of MMU and
non-MMU arch/m68k/include/asm/thread_info*.h files (this was commit
cddafa35, "merge MMU and non-MMU
thread_info.h").

It didn't get cleaned out of the entry.S code for the 68328 and 68360
based platforms. And it was replaced by a hard coded constant mask for
coldfire platforms. There is currently no need to mask any of these bits,
so fix all uses (and former uses) to check for any non-zero value.
Signed-off-by: NGreg Ungerer <gerg@uclinux.org>

we shouldn't bugger off to userland when there still are
pending signals; among other things it makes e.g. SIGSEGV
triggered by failure to build a sigframe to be delivered
_now_ and not when we hit the next syscall or interrupt.
Signed-off-by: NAl Viro <viro@zeniv.linux.org.uk>
Acked-by: NGreg Ungerer <gerg@uclinux.org>
Signed-off-by: NGeert Uytterhoeven <geert@linux-m68k.org>

Signed-off-by: NAl Viro <viro@zeniv.linux.org.uk>
Acked-by: NGreg Ungerer <gerg@uclinux.org>
Signed-off-by: NGeert Uytterhoeven <geert@linux-m68k.org>

Currently the code to push cache lines is only available to version 4
cores. Version 3 cores may also need to use this if we support copy-
back caches on them. Move this code to make it more generic, and
useful for all version ColdFire cores.

With this in place we can now have a single cache_flush_all() code
path that does all the right things on all version cores.
Signed-off-by: NGreg Ungerer <gerg@uclinux.org>

The cache control code for the ColdFire CPU's is a big ugly mess
of "#ifdef"ery liberally coated with bit constants. Clean it up.

The cache controllers in the various ColdFire parts are actually quite
similar. Just differing in some bit flags and options supported. Using
the header defines now in place it is pretty easy to factor out the
small differences and use common setup and flush/invalidate code.

I have preserved the cache setups as they where in the old code
(except where obviously wrong - like in the case of the 5249). Following
from this it should be easy now to extend the possible setups used on
the CACHE controllers that support split cacheing or copy-back or
write through options.
Signed-off-by: NGreg Ungerer <gerg@uclinux.org>

The more modern ColdFire parts (even if based on older version cores)
have separate user and supervisor stack pointers (a7 register).
Modify the ColdFire CPU setup and exception code to enable and use
this on parts that have it.
Signed-off-by: NGreg Ungerer <gerg@uclinux.org>

There are no users of the old "fasthandler" interrupt entry code.
So remove it.
Signed-off-by: NGreg Ungerer <gerg@uclinux.org>

The ColdFire 547x family of processors is very similar to the ColdFire
548x series. Almost all of the support for them is the same. Make the
code supporting the 548x more gneric, so it will be capable of
supporting both families.

For the most part this is a renaming excerise to make the support
code more obviously apply to both families.
Signed-off-by: NGreg Ungerer <gerg@uclinux.org>

The MMU and non-MMU versions of thread_info.h are quite similar.
Merge the two files.
Signed-off-by: NGreg Ungerer <gerg@uclinux.org>
Signed-off-by: NGeert Uytterhoeven <geert@linux-m68k.org>

Break up syscall_trace() into separate entry and exit routines that use
tracehook_report_syscall_entry() and tracehook_report_syscall_exit().
Signed-off-by: NGreg Ungerer <gerg@uclinux.org>

Replace EXTRA_CFLAGS with ccflags-y and EXTRA_AFLAGS with asflags-y.
Signed-off-by: Nmatt mooney <mfm@muteddisk.com>
Signed-off-by: NGreg Ungerer <gerg@uclinux.org>

Add a very basic mmu-less support for coldfire m548x family.  This is perhaps
also valid for m547x family.  The port comprises the serial, tick timer and
reboot support.  The gpio part compiles but is empty.  This gives a functional
albeit limited linux for the m548x coldfire family.  This has been tested
on a Freescale M548xEVB Lite board with a M5484 processor and the default
dbug monitor.
Signed-off-by: NPhilippe De Muyter <phdm@macqel.be>
Signed-off-by: NGreg Ungerer <gerg@uclinux.org>

The use of __do_IRQ is deprecated, so lets stop using it.
Generally the interrupts on the supported processors here are
level triggered, so this is strait forward to switch over to
using the standard handle_level_irq flow handler. (Although
some ColdFire parts support edge triggered GPIO line  interrupts
we have no support for them yet).
Signed-off-by: NGreg Ungerer <gerg@uclinux.org>

The Coldfire MCF547x/MCF548x have the same interrupt controller as
the MCF528x e.g., but only one, not two as in the MCF528x.  Modify
intc-2.c to support only one interrupt controller if MCFICM_INTC1 is
not defined.
Signed-off-by: NPhilippe De Muyter <phdm@macqel.be>
Signed-off-by: NGreg Ungerer <gerg@uclinux.org>

The chips lists were in commit logs, but should also be in source files.
This way it is easier to choose the right source file for a not yet
supported Coldfire.
Signed-off-by: NPhilippe De Muyter <phdm@macqel.be>
Signed-off-by: NGreg Ungerer <gerg@uclinux.org>

Fix the IRQ flag handling naming.  In linux/irqflags.h under one configuration,
it maps:

	local_irq_enable() -> raw_local_irq_enable()
	local_irq_disable() -> raw_local_irq_disable()
	local_irq_save() -> raw_local_irq_save()
	...

and under the other configuration, it maps:

	raw_local_irq_enable() -> local_irq_enable()
	raw_local_irq_disable() -> local_irq_disable()
	raw_local_irq_save() -> local_irq_save()
	...

This is quite confusing.  There should be one set of names expected of the
arch, and this should be wrapped to give another set of names that are expected
by users of this facility.

Change this to have the arch provide:

	flags = arch_local_save_flags()
	flags = arch_local_irq_save()
	arch_local_irq_restore(flags)
	arch_local_irq_disable()
	arch_local_irq_enable()
	arch_irqs_disabled_flags(flags)
	arch_irqs_disabled()
	arch_safe_halt()

Then linux/irqflags.h wraps these to provide:

	raw_local_save_flags(flags)
	raw_local_irq_save(flags)
	raw_local_irq_restore(flags)
	raw_local_irq_disable()
	raw_local_irq_enable()
	raw_irqs_disabled_flags(flags)
	raw_irqs_disabled()
	raw_safe_halt()

with type checking on the flags 'arguments', and then wraps those to provide:

	local_save_flags(flags)
	local_irq_save(flags)
	local_irq_restore(flags)
	local_irq_disable()
	local_irq_enable()
	irqs_disabled_flags(flags)
	irqs_disabled()
	safe_halt()

with tracing included if enabled.

The arch functions can now all be inline functions rather than some of them
having to be macros.

Signed-off-by: David Howells <dhowells@redhat.com> [X86, FRV, MN10300]
Signed-off-by: Chris Metcalf <cmetcalf@tilera.com> [Tile]
Signed-off-by: Michal Simek <monstr@monstr.eu> [Microblaze]
Tested-by: Catalin Marinas <catalin.marinas@arm.com> [ARM]
Acked-by: NThomas Gleixner <tglx@linutronix.de>
Acked-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com> [AVR]
Acked-by: Tony Luck <tony.luck@intel.com> [IA-64]
Acked-by: Hirokazu Takata <takata@linux-m32r.org> [M32R]
Acked-by: Greg Ungerer <gerg@uclinux.org> [M68K/M68KNOMMU]
Acked-by: Ralf Baechle <ralf@linux-mips.org> [MIPS]
Acked-by: Kyle McMartin <kyle@mcmartin.ca> [PA-RISC]
Acked-by: Paul Mackerras <paulus@samba.org> [PowerPC]
Acked-by: Martin Schwidefsky <schwidefsky@de.ibm.com> [S390]
Acked-by: Chen Liqin <liqin.chen@sunplusct.com> [Score]
Acked-by: Matt Fleming <matt@console-pimps.org> [SH]
Acked-by: David S. Miller <davem@davemloft.net> [Sparc]
Acked-by: Chris Zankel <chris@zankel.net> [Xtensa]
Reviewed-by: Richard Henderson <rth@twiddle.net> [Alpha]
Reviewed-by: Yoshinori Sato <ysato@users.sourceforge.jp> [H8300]
Cc: starvik@axis.com [CRIS]
Cc: jesper.nilsson@axis.com [CRIS]
Cc: linux-cris-kernel@axis.com

The m68knommu coldfire pit clocksource looks like it was incorrectly
marked as a continuous clocksource.  Running with it marked as a
continuous clocksource could cause hangs when the system switches to
highres mode or enables nohz.

This patch removes the CLOCK_SOURCE_IS_CONTINUOUS flag on the coldfire pit
clocksource.  This will disallow systems using this clocksource from
entering oneshot mode (disabling highres timers and nohz).
Signed-off-by: NJohn Stultz <johnstul@us.ibm.com>
Acked-by: NGreg Ungerer <gerg@snapgear.com>
Cc: Steven King <sfking@fdwdc.com>
Signed-off-by: NAndrew Morton <akpm@linux-foundation.org>
Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>

export the clk_*  stubs defined in arch/m68knommu/platform/coldfire/clk.c so
they can be used by modules.
Signed-off-by: NSteven King <sfking@fdwdc.com>
Signed-off-by: NGreg Ungerer <gerg@goober.(none)>

This patch adds m68knommu support for getting the kernel command line
arguments from uboot, including the passing of an initrd image from uboot.

We use this on a 5270/5271 based board, and have used it on the 5271evb
development board.  It is based on a patch found in the linux-2.6-denx
git tree, although that tree seems to have had lots of other changes
since which are not in the main Linus kernel.  I believe this will work
on all coldfires, although other m68knommu might be missing the _init_sp
stuff in head.S as far as I can tell.  I only have the coldfire to
test on.
Signed-off-by: NLennart Sorensen <lsorense@csclub.uwaterloo.ca>
Signed-off-by: NGreg Ungerer <gerg@uclinux.org>

Commit f159ee78 ("locking,
m68k/asm-offsets: Rename pt_regs offset defines") breaks the
m68knommu entry code that relies on these define names.
Fix the files to match the new define names.
Signed-off-by: NGreg Ungerer <gerg@uclinux.org>

The ColdFire 5272 CPU has a very different interrupt controller than
any of the other ColdFire parts. It needs its own controller code to
correctly setup and ack interrupts.
Signed-off-by: NGreg Ungerer <gerg@uclinux.org>

The recent changes to the old ColdFire interrupt controller code means
we no longer need to manually unmask the timer interrupt. That is now
done in the interrupt controller code proper.
Signed-off-by: NGreg Ungerer <gerg@uclinux.org>

The older simple ColdFire interrupt controller has no one-to-one mapping
of interrupt numbers to bits in the interrupt mask register. Create a
mapping array that each ColdFire CPU type can populate with its available
interrupts and the bits that each use in the interrupt mask register.
Signed-off-by: NGreg Ungerer <gerg@uclinux.org>

The ColdFire "timers" clock setup can be simplified. There is really no
need for the flexible per-platform setup code. The clock interrupt can be
hard defined per CPU platform (in CPU include files). This makes the
actual timer code simpler.
Signed-off-by: NGreg Ungerer <gerg@uclinux.org>

The external interrupts used on the old Coldfire parts with the old style
interrupt controller can be properly mask/unmasked in the interrupt
handling code.
Signed-off-by: NGreg Ungerer <gerg@uclinux.org>

Currently the code that supports setting the old style ColdFire interrupt
controller mask registers is macros in the include files of each of the
CPU types. Merge all these into a set of real masking functions in the
old Coldfire interrupt controller code proper. All the macros are basically
the same (excepting a register size difference on really early parts).
Signed-off-by: NGreg Ungerer <gerg@uclinux.org>