- 16 3月, 2011 3 次提交
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由 Stephen Rothwell 提交于
[AV: on architectures where default conflicts with existing flags, that is] Signed-off-by: NStephen Rothwell <sfr@canb.auug.org.au> Signed-off-by: NAl Viro <viro@zeniv.linux.org.uk>
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由 Boris Ostrovsky 提交于
Support for Always Running APIC timer (ARAT) was introduced in commit db954b58. This feature allows us to avoid switching timers from LAPIC to something else (e.g. HPET) and go into timer broadcasts when entering deep C-states. AMD processors don't provide a CPUID bit for that feature but they also keep APIC timers running in deep C-states (except for cases when the processor is affected by erratum 400). Therefore we should set ARAT feature bit on AMD CPUs. Tested-by: NBorislav Petkov <borislav.petkov@amd.com> Acked-by: NAndreas Herrmann <andreas.herrmann3@amd.com> Acked-by: NMark Langsdorf <mark.langsdorf@amd.com> Acked-by: NThomas Gleixner <tglx@linutronix.de> Signed-off-by: NBoris Ostrovsky <boris.ostrovsky@amd.com> LKML-Reference: <1300205624-4813-1-git-send-email-ostr@amd64.org> Signed-off-by: NIngo Molnar <mingo@elte.hu>
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由 Andreas Herrmann 提交于
Commit 7f74f8f2 (x86 quirk: Fix polarity for IRQ0 pin2 override on SB800 systems) introduced a regression. It removed some SB600 specific code to determine the revision ID without adapting a corresponding revision ID check for SB600. See this mail thread: http://marc.info/?l=linux-kernel&m=129980296006380&w=2 This patch adapts the corresponding check to cover all SB600 revisions. Tested-by: NWang Lei <f3d27b@gmail.com> Signed-off-by: NAndreas Herrmann <andreas.herrmann3@amd.com> Cc: Andrew Morton <akpm@linux-foundation.org> Cc: stable@kernel.org # 38.x, 37.x, 32.x LKML-Reference: <20110315143137.GD29499@alberich.amd.com> Signed-off-by: NIngo Molnar <mingo@elte.hu>
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- 15 3月, 2011 37 次提交
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由 Mathieu Desnoyers 提交于
Intel Archiecture Software Developer's Manual section 7.1.3 specifies that a core serializing instruction such as "cpuid" should be executed on _each_ core before the new instruction is made visible. Failure to do so can lead to unspecified behavior (Intel XMC erratas include General Protection Fault in the list), so we should avoid this at all cost. This problem can affect modified code executed by interrupt handlers after interrupt are re-enabled at the end of stop_machine, because no core serializing instruction is executed between the code modification and the moment interrupts are reenabled. Because stop_machine_text_poke performs the text modification from the first CPU decrementing stop_machine_first, modified code executed in thread context is also affected by this problem. To explain why, we have to split the CPUs in two categories: the CPU that initiates the text modification (calls text_poke_smp) and all the others. The scheduler, executed on all other CPUs after stop_machine, issues an "iret" core serializing instruction, and therefore handles core serialization for all these CPUs. However, the text modification initiator can continue its execution on the same thread and access the modified text without any scheduler call. Given that the CPU that initiates the code modification is not guaranteed to be the one actually performing the code modification, it falls into the XMC errata. Q: Isn't this executed from an IPI handler, which will return with IRET (a serializing instruction) anyway? A: No, now stop_machine uses per-cpu workqueue, so that handler will be executed from worker threads. There is no iret anymore. Signed-off-by: NMathieu Desnoyers <mathieu.desnoyers@efficios.com> LKML-Reference: <20110303160137.GB1590@Krystal> Reviewed-by: NMasami Hiramatsu <masami.hiramatsu.pt@hitachi.com> Cc: <stable@kernel.org> Cc: Arjan van de Ven <arjan@infradead.org> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Steven Rostedt <rostedt@goodmis.org> Cc: Andrew Morton <akpm@linux-foundation.org> Cc: Andi Kleen <andi@firstfloor.org> Cc: Frederic Weisbecker <fweisbec@gmail.com> Signed-off-by: NH. Peter Anvin <hpa@linux.intel.com>
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由 Greg Ungerer 提交于
The EDGE Port module of some ColdFire parts using the intc-simr interrupt controller provides support for 7 external interrupts. These interrupts go off-chip (that is they are not for internal peripherals). They need some special handling and have some extra setup registers. Add code to support them. Signed-off-by: NGreg Ungerer <gerg@uclinux.org>
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由 Greg Ungerer 提交于
The EDGE Port module of some ColdFire parts using the intc-2 interrupt controller provides support for 7 external interrupts. These interrupts go off-chip (that is they are not for internal peripherals). They need some special handling and have some extra setup registers. Add code to support them. Signed-off-by: NGreg Ungerer <gerg@uclinux.org>
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由 Greg Ungerer 提交于
The reality is that you do not need the abiltity to configure the clock divider for ColdFire CPUs. It is a fixed ratio on any given ColdFire family member. It is not the same for all ColdFire parts, but it is always the same in a model range. So hard define the divider for each supported ColdFire CPU type and remove the Kconfig option. Signed-off-by: NGreg Ungerer <gerg@uclinux.org>
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由 Greg Ungerer 提交于
Fix these compiler warnings: arch/m68knommu/platform/5407/gpio.c:35:3: warning: initialisation makes pointer from integer without a cast arch/m68knommu/platform/5407/gpio.c:36:3: warning: initialisation makes pointer from integer without a cast arch/m68knommu/platform/5407/gpio.c:37:3: warning: initialisation makes pointer from integer without a cast Signed-off-by: NGreg Ungerer <gerg@uclinux.org>
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由 Greg Ungerer 提交于
Fix these compiler warnings: arch/m68knommu/platform/532x/gpio.c:35:3: warning: initialisation makes pointer from integer without a cast arch/m68knommu/platform/532x/gpio.c:36:3: warning: initialisation makes pointer from integer without a cast arch/m68knommu/platform/532x/gpio.c:37:3: warning: initialisation makes pointer from integer without a cast arch/m68knommu/platform/532x/gpio.c:51:3: warning: initialisation makes pointer from integer without a cast arch/m68knommu/platform/532x/gpio.c:52:3: warning: initialisation makes pointer from integer without a cast arch/m68knommu/platform/532x/gpio.c:53:3: warning: initialisation makes pointer from integer without a cast arch/m68knommu/platform/532x/gpio.c:54:3: warning: initialisation makes pointer from integer without a cast ... Signed-off-by: NGreg Ungerer <gerg@uclinux.org>
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由 Greg Ungerer 提交于
Fix these compiler warnings: arch/m68knommu/platform/5307/gpio.c:35:3: warning: initialisation makes pointer from integer without a cast arch/m68knommu/platform/5307/gpio.c:36:3: warning: initialisation makes pointer from integer without a cast arch/m68knommu/platform/5307/gpio.c:37:3: warning: initialisation makes pointer from integer without a cast Signed-off-by: NGreg Ungerer <gerg@uclinux.org>
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由 Greg Ungerer 提交于
Fix these compiler warnings: arch/m68knommu/platform/527x/gpio.c:37:3: warning: initialisation makes pointer from integer without a cast arch/m68knommu/platform/527x/gpio.c:38:3: warning: initialisation makes pointer from integer without a cast arch/m68knommu/platform/527x/gpio.c:39:3: warning: initialisation makes pointer from integer without a cast arch/m68knommu/platform/527x/gpio.c:53:3: warning: initialisation makes pointer from integer without a cast arch/m68knommu/platform/527x/gpio.c:54:3: warning: initialisation makes pointer from integer without a cast arch/m68knommu/platform/527x/gpio.c:55:3: warning: initialisation makes pointer from integer without a cast ... Signed-off-by: NGreg Ungerer <gerg@uclinux.org>
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由 Greg Ungerer 提交于
Fix these compiler warnings: arch/m68knommu/platform/5272/gpio.c:35:3: warning: initialisation makes pointer from integer without a cast arch/m68knommu/platform/5272/gpio.c:36:3: warning: initialisation makes pointer from integer without a cast arch/m68knommu/platform/5272/gpio.c:37:3: warning: initialisation makes pointer from integer without a cast arch/m68knommu/platform/5272/gpio.c:51:3: warning: initialisation makes pointer from integer without a cast arch/m68knommu/platform/5272/gpio.c:52:3: warning: initialisation makes pointer from integer without a cast arch/m68knommu/platform/5272/gpio.c:53:3: warning: initialisation makes pointer from integer without a cast arch/m68knommu/platform/5272/gpio.c:67:3: warning: initialisation makes pointer from integer without a cast arch/m68knommu/platform/5272/gpio.c:68:3: warning: initialisation makes pointer from integer without a cast arch/m68knommu/platform/5272/gpio.c:69:3: warning: initialisation makes pointer from integer without a cast Signed-off-by: NGreg Ungerer <gerg@uclinux.org>
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由 Greg Ungerer 提交于
Fix these compiler warnings: arch/m68knommu/platform/5249/gpio.c:35:3: warning: initialisation makes pointer from integer without a cast arch/m68knommu/platform/5249/gpio.c:36:3: warning: initialisation makes pointer from integer without a cast arch/m68knommu/platform/5249/gpio.c:37:3: warning: initialisation makes pointer from integer without a cast arch/m68knommu/platform/5249/gpio.c:51:3: warning: initialisation makes pointer from integer without a cast arch/m68knommu/platform/5249/gpio.c:52:3: warning: initialisation makes pointer from integer without a cast arch/m68knommu/platform/5249/gpio.c:53:3: warning: initialisation makes pointer from integer without a cast Signed-off-by: NGreg Ungerer <gerg@uclinux.org>
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由 Greg Ungerer 提交于
Fix these compiler warnings: arch/m68knommu/platform/523x/gpio.c:36:3: warning: initialisation makes pointer from integer without a cast arch/m68knommu/platform/523x/gpio.c:37:3: warning: initialisation makes pointer from integer without a cast arch/m68knommu/platform/523x/gpio.c:38:3: warning: initialisation makes pointer from integer without a cast arch/m68knommu/platform/523x/gpio.c:52:3: warning: initialisation makes pointer from integer without a cast arch/m68knommu/platform/523x/gpio.c:53:3: warning: initialisation makes pointer from integer without a cast ... Signed-off-by: NGreg Ungerer <gerg@uclinux.org>
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由 Greg Ungerer 提交于
Fix these compiler warnings: rch/m68knommu/platform/520x/gpio.c:35:3: warning: initialisation makes pointer from integer without a cast arch/m68knommu/platform/520x/gpio.c:36:3: warning: initialisation makes pointer from integer without a cast arch/m68knommu/platform/520x/gpio.c:37:3: warning: initialisation makes pointer from integer without a cast arch/m68knommu/platform/520x/gpio.c:51:3: warning: initialisation makes pointer from integer without a cast arch/m68knommu/platform/520x/gpio.c:52:3: warning: initialisation makes pointer from integer without a cast ... Signed-off-by: NGreg Ungerer <gerg@uclinux.org>
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由 Greg Ungerer 提交于
Fix these compiler warnings: arch/m68knommu/platform/5206e/gpio.c:35:3: warning: initialisation makes pointer from integer without a cast CC kernel/panic.o arch/m68knommu/platform/5206e/gpio.c:36:3: warning: initialisation makes pointer from integer without a cast arch/m68knommu/platform/5206e/gpio.c:37:3: warning: initialisation makes pointer from integer without a cast Signed-off-by: NGreg Ungerer <gerg@uclinux.org>
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由 Greg Ungerer 提交于
Fix these compiler warnings: arch/m68knommu/platform/5206/gpio.c:35:3: warning: initialisation makes pointer from integer without a cast arch/m68knommu/platform/5206/gpio.c:36:3: warning: initialisation makes pointer from integer without a cast arch/m68knommu/platform/5206/gpio.c:37:3: warning: initialisation makes pointer from integer without a cast Signed-off-by: NGreg Ungerer <gerg@uclinux.org>
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由 Alexander Kurz 提交于
Signed-off-by: NAlexander Kurz <linux@kbdbabel.org> Signed-off-by: NGreg Ungerer <gerg@uclinux.org>
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由 Greg Ungerer 提交于
The intc-simr interrupt controller on some ColdFire CPUs has a set range of interrupts its supports (64 through 128 or 192 depending on model). We shouldn't be setting this handler for every possible interrupt from 0 to 255. Set more appropriate limits, and this means we can drop the interrupt number check in the mask and unmask routines. Signed-off-by: NGreg Ungerer <gerg@uclinux.org>
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由 Greg Ungerer 提交于
Use a proper irq_startup() routine to intialize the interrupt priority and level register in the ColdFire intc-2 controller code. We shouldn't be checking if the priority/level has been set on every unmask operation. Signed-off-by: NGreg Ungerer <gerg@uclinux.org>
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由 Greg Ungerer 提交于
The intc-2 interrupt controller on some ColdFire CPUs has a set range of interrupts its supports (64 through 128 or 192 depending on model). We shouldn't be setting this handler for every possible interrupt from 0 to 255. Set more appropriate limits, and this means we can drop the interrupt number check in the mask and unmask routines. Signed-off-by: NGreg Ungerer <gerg@uclinux.org>
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由 Greg Ungerer 提交于
The FireBee is a ColdFire 5475 based board. Add a configuration option to support it, and the basic platform flash layout code. Signed-off-by: NGreg Ungerer <gerg@uclinux.org>
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由 Greg Ungerer 提交于
Most ColdFire CPUs have an internal peripheral set that can be mapped at a user selectable address. Different ColdFire parts either use an MBAR register of an IPSBAR register to map the peripheral region. Most boards use the Freescale default mappings - but not all. Make the setting of the MBAR or IPSBAR register configurable. And only make the selection available on the appropriate ColdFire CPU types. Signed-off-by: NGreg Ungerer <gerg@uclinux.org>
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由 Greg Ungerer 提交于
Different ColdFire CPUs have different ways of defining where their internal peripheral registers sit in their address space. Some use an MBAR register, some use and IPSBAR register, some have a fixed mapping. Now that most of the peripheral address definitions have been cleaned up we can clean up the setting of the MBAR and IPSBAR defines to limit them to just where they are needed (and where they actually exist). Signed-off-by: NGreg Ungerer <gerg@uclinux.org>
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由 Greg Ungerer 提交于
In some of the RAM size autodetection code on ColdFire CPU startup we reference DRAM registers relative to the MBAR register. Not all of the supported ColdFire CPUs have an MBAR, and currently this works because we fake an MBAR address on those registers. In an effort to clean this up, and eventually remove the fake MBAR setting make the DRAM register address definitions actually contain the MBAR (or IPSBAR as appropriate) value as required. Signed-off-by: NGreg Ungerer <gerg@uclinux.org>
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由 Greg Ungerer 提交于
Not all ColdFire CPUs that use the old style timer hardware module use an MBAR set peripheral region. Move the TIMER base address defines to the per-CPU header files where we can set it correctly based on how the peripherals are mapped - instead of using a fake MBAR for some platforms. Signed-off-by: NGreg Ungerer <gerg@uclinux.org>
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由 Greg Ungerer 提交于
The base addresses of the ColdFire DMA unit registers belong with all the other address definitions in the per-cpu headers. The current definitions assume they are relative to an MBAR register. Not all ColdFire CPUs have an MBAR register. A clean address define can only be acheived in the per-cpu headers along with all the other chips peripheral base addresses. Signed-off-by: NGreg Ungerer <gerg@uclinux.org>
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由 Greg Ungerer 提交于
The ColdFire 528x family of CPUs does not have an MBAR register, so don't define its peripheral addresses relative to one. Its internal peripherals are relative to the IPSBAR register, so make sure to use that. Signed-off-by: NGreg Ungerer <gerg@uclinux.org>
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由 Greg Ungerer 提交于
The ColdFire 527x family of CPUs does not have an MBAR register, so don't define its peripheral addresses relative to one. Its internal peripherals are relative to the IPSBAR register, so make sure to use that. Signed-off-by: NGreg Ungerer <gerg@uclinux.org>
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由 Greg Ungerer 提交于
The ColdFire 523x family of CPUs does not have an MBAR register, so don't define its peripheral addresses relative to one. Its internal peripherals are relative to the IPSBAR register, so make sure to use that. Signed-off-by: NGreg Ungerer <gerg@uclinux.org>
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由 Greg Ungerer 提交于
The ColdFire 5207 and 5208 CPUs have fixed peripheral addresses. They do not use the setable peripheral address registers like the MBAR and IPSBAR used on many other ColdFire parts. Don't use fake values of MBAR and IPSBAR when using peripheral addresses for them, there is no need to. Signed-off-by: NGreg Ungerer <gerg@uclinux.org>
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由 Greg Ungerer 提交于
The PIT hardware timer module used in some ColdFire CPU's is not always addressed relative to an IPSBAR register. Parts like the ColdFire 5207 and 5208 have fixed peripheral addresses. So lets not define the register addresses of the PIT relative to an IPSBAR definition. Move the base address definitions into the per-part headers. This is a lot more consistent since all the other peripheral base addresses are defined in the per-part header files already. Signed-off-by: NGreg Ungerer <gerg@uclinux.org>
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由 Greg Ungerer 提交于
Remove the bogus definition of the MBAR register for the ColdFire 532x family. It doesn't have an MBAR register, its peripheral registers are at fixed addresses and are not relative to a settable base. All the code that relyed on this definition existing has been cleaned up. The register address definitions now include the base as required. Signed-off-by: NGreg Ungerer <gerg@uclinux.org>
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由 Greg Ungerer 提交于
The ColdFire 54xx family shares the same interrupt controller used on the 523x, 527x and 528x ColdFire parts, but it isn't offset relative to the IPSBAR register. The 54xx doesn't have an IPSBAR register. By including the base address of the peripheral registers in the register definitions (MCFICM_INTC0 and MCFICM_INTC1 in this case) we can avoid having to define a fake IPSBAR for the 54xx. And this makes the register address definitions of these more consistent, the majority of the other register address defines include the peripheral base address already. Signed-off-by: NGreg Ungerer <gerg@uclinux.org>
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由 Greg Ungerer 提交于
The MBAR2 register is only used on the ColdFire 5249 part, so move its definition out of the common coldfire.h and into the 5249 support header. Signed-off-by: NGreg Ungerer <gerg@uclinux.org>
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由 Thomas Gleixner 提交于
All chips converted and proper accessor functions used. Signed-off-by: NThomas Gleixner <tglx@linutronix.de> Signed-off-by: NGreg Ungerer <gerg@uclinux.org>
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由 Thomas Gleixner 提交于
Signed-off-by: NThomas Gleixner <tglx@linutronix.de> Signed-off-by: NGreg Ungerer <gerg@uclinux.org>
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由 Thomas Gleixner 提交于
/me idly wonders what sets the handlers for this chip. Signed-off-by: NThomas Gleixner <tglx@linutronix.de> Signed-off-by: NGreg Ungerer <gerg@uclinux.org>
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由 Thomas Gleixner 提交于
Signed-off-by: NThomas Gleixner <tglx@linutronix.de> Signed-off-by: NGreg Ungerer <gerg@uclinux.org>
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由 Thomas Gleixner 提交于
Signed-off-by: NThomas Gleixner <tglx@linutronix.de> Signed-off-by: NGreg Ungerer <gerg@uclinux.org>
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