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  1. 29 1月, 2008 13 次提交
  3. 22 1月, 2008 1 次提交
  5. 15 1月, 2008 1 次提交
  7. 15 12月, 2007 1 次提交
  9. 09 12月, 2007 1 次提交
  11. 07 12月, 2007 1 次提交
  13. 01 12月, 2007 1 次提交
    • P
      [MIPS] Fix use of smp_processor_id() in preemptible code. · 54fd6441
      由 Pavel Kiryukhin 提交于 
      Freeing prom memory: 956kb freed
Freeing firmware memory: 978944k freed
Freeing unused kernel memory: 180k freed
BUG: using smp_processor_id() in preemptible [00000000] code: swapper/1
caller is r4k_dma_cache_wback_inv+0x144/0x2a0
Call Trace:
 [<80117af8>] r4k_dma_cache_wback_inv+0x144/0x2a0
 [<802e4b84>] debug_smp_processor_id+0xd4/0xf0
 [<802e4b7c>] debug_smp_processor_id+0xcc/0xf0
...
CONFIG_DEBUG_PREEMPT is enabled.
--
Bug cause is blast_dcache_range() in preemptible code [in
r4k_dma_cache_wback_inv()].
blast_dcache_range() is constructed via __BUILD_BLAST_CACHE_RANGE that
uses cpu_dcache_line_size(). It uses current_cpu_data that use
smp_processor_id() in turn. In case of CONFIG_DEBUG_PREEMPT
smp_processor_id emits BUG if we are executing with preemption
enabled.

Cpu options of cpu0 are assumed to be the superset of all processors.

Can I make the same assumptions for cache line size  and fix this
issue the following way:
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
      54fd6441
  15. 30 11月, 2007 1 次提交
  17. 27 11月, 2007 7 次提交
    • R
      [MIPS] 64-bit Sibyte kernels need DMA32. · cce335ae
      由 Ralf Baechle 提交于 
      Sibyte SOCs only have 32-bit PCI.  Due to the sparse use of the address
space only the first 1GB of memory is mapped at physical addresses
below 1GB.  If a system has more than 1GB of memory 32-bit DMA will
not be able to reach all of it.

For now this patch is good enough to keep Sibyte users happy but it seems
eventually something like swiotlb will be needed for Sibyte.
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
      cce335ae
    • R
      [MIPS] Only build r4k clocksource for systems that work ok with it. · 940f6b48
      由 Ralf Baechle 提交于 
      In particular as-is it's not suited for multicore and mutiprocessors
systems where there is on guarantee that the counter are synchronized
or running from the same clock at all.  This broke Sibyte and probably
others since the "[MIPS] Handle R4000/R4400 mfc0 from count register."
commit.
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
      940f6b48
    • R
      [MIPS] Handle R4000/R4400 mfc0 from count register. · 5aa85c9f
      由 Ralf Baechle 提交于 
      The R4000 and R4400 have an errata where if the cp0 count register is read
in the exact moment when it matches the compare register no interrupt will
be generated.

This bug may be triggered if the cp0 count register is being used as
clocksource and the compare interrupt as clockevent.  So a simple
workaround is to avoid using the compare for both facilities on the
affected CPUs.

This is different from the workaround suggested in the old errata documents;
at some opportunity probably the official version should be implemented
and tested.  Another thing to find out is which processor versions
exactly are affected.  I only have errata documents upto R4400 V3.0
available so for the moment the code treats all R4000 and R4400 as broken.

This is potencially a problem for some machines that have no other decent
clocksource available; this workaround will cause them to fall back to
another clocksource, worst case the "jiffies" source.
      5aa85c9f
    • R
      [MIPS] Fix possible hang in LL/SC futex loops. · 0f67e90e
      由 Ralf Baechle 提交于 
      The LL / SC loops in __futex_atomic_op() have the usual fixups necessary
for memory acccesses to userspace from kernel space installed:

        __asm__ __volatile__(
        "       .set    push                            \n"
        "       .set    noat                            \n"
        "       .set    mips3                           \n"
        "1:     ll      %1, %4  # __futex_atomic_op     \n"
        "       .set    mips0                           \n"
        "       " insn  "                               \n"
        "       .set    mips3                           \n"
        "2:     sc      $1, %2                          \n"
        "       beqz    $1, 1b                          \n"
        __WEAK_LLSC_MB
        "3:                                             \n"
        "       .set    pop                             \n"
        "       .set    mips0                           \n"
        "       .section .fixup,\"ax\"                  \n"
        "4:     li      %0, %6                          \n"
        "       j       2b                              \n"	<-----
        "       .previous                               \n"
        "       .section __ex_table,\"a\"               \n"
        "       "__UA_ADDR "\t1b, 4b                    \n"
        "       "__UA_ADDR "\t2b, 4b                    \n"
        "       .previous                               \n"
        : "=r" (ret), "=&r" (oldval), "=R" (*uaddr)
        : "0" (0), "R" (*uaddr), "Jr" (oparg), "i" (-EFAULT)
        : "memory");

The branch at the end of the fixup code, it goes back to the SC
instruction, no matter if the fault was first taken by the LL or SC
instruction resulting in an endless loop which will only terminate if
the address become valid again due to another thread setting up an
accessible mapping and the CPU happens to execute the SC instruction
successfully which due to the preceeding ERET instruction of the fault
handler would only happen if UNPREDICTABLE instruction behaviour of the
SC instruction without a preceeding LL happens to favor that outcome.
But normally processes are nice, pass valid arguments and we were just
getting away with this.

Thanks to Kaz Kylheku <kaz@zeugmasystems.com> for providing the original
report and a test case.
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
      0f67e90e
    • R
      [MIPS] Fix context DSP context / TLS pointer switching bug for new threads. · 07500b0d
      由 Ralf Baechle 提交于 
      A new born thread starts execution not in schedule but rather in
ret_from_fork which results in it bypassing the part of the code to
load a new context written in C which are the DSP context and the
userlocal register which Linux uses for the TLS pointer.  Frequently
we were just getting away with this bug for a number of reasons:

 o Real world application scenarios are very unlikely to use clone or fork
   in blocks of DSP code.
 o Linux by default runs the child process right after the fork, so the
   child by luck will find all the right context in the DSP and userlocal
   registers.
 o So far the rdhwr instruction was emulated on all hardware so userlocal
   wasn't getting referenced at all and the emulation wasn't suffering
   from the issue since it gets it's value straight from the thread's
   thread_info.

Fixed by moving the code to load the context from switch_to() to
finish_arch_switch which will be called by newborn and old threads.
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
      07500b0d
    • R
      [MIPS] IP32: More interrupt renumbering fixes. · 98ce4721
      由 Ralf Baechle 提交于 
      Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
      98ce4721
    • R
      [MIPS] Fix pcspeaker build. · cfb6f260
      由 Ralf Baechle 提交于 
      Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
      cfb6f260
  19. 16 11月, 2007 3 次提交
    • Y
      [MIPS] Lasat: Fix overlap of interrupt number ranges. · 89becf5c
      由 Yoichi Yuasa 提交于 
      The range of MIPS_CPU IRQ and the range of LASAT IRQ overlap.
Signed-off-by: NYoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
      89becf5c
    • R
      [MIPS] Fix shadow register support. · f6771dbb
      由 Ralf Baechle 提交于 
      Shadow register support would not possibly have worked on multicore
systems.  The support code for it was also depending not on MIPS R2 but
VSMP or SMTC kernels even though it makes perfect sense with UP kernels.

SR sets are a scarce resource and the expected usage pattern is that
users actually hardcode the register set numbers in their code.  So fix
the allocator by ditching it.  Move the remaining CPU probe bits into
the generic CPU probe.
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
      f6771dbb
    • R
      [MIPS] Change get_cycles to always return 0. · efb9ca08
      由 Ralf Baechle 提交于 
      This avoids us executing an mfc0 c0_count instruction on processors which
don't have but also on certain R4000 and R4400 versions where reading from
the count register just in the very moment when its value equals
c0_compare will result in the timer interrupt getting lost.

There is still a number of users of get_cycles remaining outside the
arch code:

crypto/tcrypt.c:                start = get_cycles();
crypto/tcrypt.c:                end = get_cycles();
crypto/tcrypt.c:                start = get_cycles();
crypto/tcrypt.c:                end = get_cycles();
crypto/tcrypt.c:                start = get_cycles();
crypto/tcrypt.c:                end = get_cycles();
drivers/char/hangcheck-timer.c: return get_cycles();
drivers/char/hangcheck-timer.c: printk("Hangcheck: Using get_cycles().\n");
drivers/char/random.c:  sample.cycles = get_cycles();
drivers/input/joystick/analog.c:#define GET_TIME(x)     do { x = get_cycles(); }
include/linux/arcdevice.h:          _x = get_cycles(); \
include/linux/arcdevice.h:          _y = get_cycles(); \
mm/slub.c:      if (!s->defrag_ratio || get_cycles() % 1024 > s->defrag_ratio)
mm/slub.c:      p += 64 + (get_cycles() & 0xff) * sizeof(void *);
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
      efb9ca08
  21. 03 11月, 2007 6 次提交
  23. 30 10月, 2007 4 次提交