1. 26 5月, 2014 1 次提交
  2. 17 4月, 2014 1 次提交
    • J
      spi: fsl-espi: Configure FSL eSPI CSBEF and CSAFT · d0fb47a5
      Jane Wan 提交于
      Make FSL eSPI CSnBEF and CSnAFT fields in ESPI_SPMODEn registers
      (n=0,1,2,3) configurable through device tree.
      
      CSnBEF is the chip select setup time.  It's the delay in bits from the
      activation of chip select pin to the first clock for data frame.
      
      CSnAFT is the chip select hold time.  It's the delay in bits from the
      last clock for data frame to the deactivation of chip select pin.
      
      The FSL eSPI driver hardcodes CSnBEF and CSnAFT to 0.  Need to set
      them to a different value for some device.
      Signed-off-by: NJane Wan <Jane.Wan@gainspeed.com>
      Signed-off-by: NMark Brown <broonie@linaro.org>
      d0fb47a5
  3. 15 4月, 2014 1 次提交
  4. 03 4月, 2014 1 次提交
  5. 22 3月, 2014 1 次提交
  6. 12 12月, 2013 1 次提交
  7. 11 12月, 2013 1 次提交
  8. 15 11月, 2013 1 次提交
  9. 24 10月, 2013 1 次提交
  10. 17 10月, 2013 1 次提交
  11. 10 10月, 2013 1 次提交
  12. 29 8月, 2013 1 次提交
  13. 02 6月, 2013 1 次提交
  14. 30 5月, 2013 1 次提交
  15. 08 12月, 2012 1 次提交
  16. 14 4月, 2012 1 次提交
  17. 16 3月, 2012 2 次提交
  18. 25 10月, 2011 1 次提交
  19. 06 6月, 2011 1 次提交
  20. 31 3月, 2011 1 次提交
  21. 01 3月, 2011 1 次提交
  22. 30 12月, 2010 1 次提交
  23. 24 12月, 2010 2 次提交
  24. 13 10月, 2010 1 次提交
    • M
      spi/fsl_spi: add eSPI controller support · 8b60d6c2
      Mingkai Hu 提交于
      Add eSPI controller support based on the library code spi_fsl_lib.c.
      
      The eSPI controller is newer controller 85xx/Pxxx devices supported.
      There're some differences comparing to the SPI controller:
      
      1. Has different register map and different bit definition
         So leave the code operated the register to the driver code, not
         the common code.
      
      2. Support 4 dedicated chip selects
         The software can't controll the chip selects directly, The SPCOM[CS]
         field is used to select which chip selects is used, and the
         SPCOM[TRANLEN] field is set to tell the controller how long the CS
         signal need to be asserted. So the driver doesn't need the chipselect
         related function when transfering data, just set corresponding register
         fields to controll the chipseclect.
      
      3. Different Transmit/Receive FIFO access register behavior
         For SPI controller, the Tx/Rx FIFO access register can hold only
         one character regardless of the character length, but for eSPI
         controller, the register can hold 4 or 2 characters according to
         the character lengths. Access the Tx/Rx FIFO access register of the
         eSPI controller will shift out/in 4/2 characters one time. For SPI
         subsystem, the command and data are put into different transfers, so
         we need to combine all the transfers to one transfer in order to pass
         the transfer to eSPI controller.
      
      4. The max transaction length limitation
         The max transaction length one time is limitted by the SPCOM[TRANSLEN]
         field which is 0xFFFF. When used mkfs.ext2 command to create ext2
         filesystem on the flash, the read length will exceed the max value of
         the SPCOM[TRANSLEN] field.
      Signed-off-by: NMingkai Hu <Mingkai.hu@freescale.com>
      Signed-off-by: NGrant Likely <grant.likely@secretlab.ca>
      8b60d6c2