The Tegra20 fuse driver is the only user of tegra_apb_readl_using_dma().
Therefore we can simply the code by incorporating the APB DMA handling into
the driver directly. tegra_apb_writel_using_dma() is dropped because there
are no users.
Signed-off-by: NPeter De Schrijver <pdeschrijver@nvidia.com>
Signed-off-by: NStephen Warren <swarren@nvidia.com>
Signed-off-by: NThierry Reding <treding@nvidia.com>

Implement fuse driver for Tegra20, Tegra30, Tegra114 and Tegra124. This
replaces functionality previously provided in arch/arm/mach-tegra, which
is removed in this patch.

While at it, move the only user of the global tegra_revision variable
over to tegra_sku_info.revision and export tegra_fuse_readl() to allow
drivers to read calibration fuses.
Signed-off-by: NPeter De Schrijver <pdeschrijver@nvidia.com>
Signed-off-by: NStephen Warren <swarren@nvidia.com>
Signed-off-by: NThierry Reding <treding@nvidia.com>

All fuse related functionality will move to a driver in the following
patches. To prepare for this, export all the required functionality in a
global header file and move all users of fuse.h to soc/tegra/fuse.h.

While we're at it, remove tegra_bct_strapping, as its only user was
removed in Commit a7cbe92c ("ARM: tegra: remove tegra EMC scaling
driver").
Signed-off-by: NPeter De Schrijver <pdeschrijver@nvidia.com>
Signed-off-by: NStephen Warren <swarren@nvidia.com>
Signed-off-by: NThierry Reding <treding@nvidia.com>

Export APB DMA readl and writel. These are needed because we can't
access the fuses directly on Tegra20 without potentially causing a
system hang. Also have the APB DMA readl and writel return an error in
case of a read failure instead of just returning zero or ignore write
failures.
Signed-off-by: NPeter De Schrijver <pdeschrijver@nvidia.com>
Signed-off-by: NStephen Warren <swarren@nvidia.com>
Signed-off-by: NThierry Reding <treding@nvidia.com>

Instead of using a simple variable access to get at the Tegra chip ID,
use a function so that we can run additional code. This can be used to
determine where the chip ID is being accessed without being available.
That in turn will be handy for resolving boot sequence dependencies in
order to convert more code to regular initcalls rather than a sequence
fixed by Tegra SoC setup code.
Signed-off-by: NThierry Reding <treding@nvidia.com>

If these aren't sorted alphabetically, then the logical choice is to
append new ones, however that creates a lot of potential for conflicts
because every change will then add new includes in the same location.
Signed-off-by: NThierry Reding <treding@nvidia.com>

In order to not clutter the include/linux directory with SoC specific
headers, move the Tegra-specific headers out into a separate directory.
Signed-off-by: NThierry Reding <treding@nvidia.com>

Remove the explicit call to l2x0_of_init(), converting to the generic
infrastructure instead.
Acked-by: NStephen Warren <swarren@nvidia.com>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

Acked-by: NStephen Warren <swarren@nvidia.com>
Tested-by: NStephen Warren <swarren@nvidia.com>
Reviewed-by: NJoseph Lo <josephl@nvidia.com>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

The cache size should already be present in the L2 cache auxiliary
control register: it is part of the integration process to configure
the hardware IP.  Most platforms get this right, yet still many
cargo-cult program, and assume that they always need specifying to
the L2 cache code.  Remove them so we can find out which really need
this.
Acked-by: NStephen Warren <swarren@nvidia.com>
Tested-by: NStephen Warren <swarren@nvidia.com>
Acked-by: NPeter De Schrijver <pdeschrijver@nvidia.com>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

Since we now automatically enable early BRESP in core L2C-310 code when
we detect a Cortex-A9, we don't need platforms/SoCs to set this bit
explicitly.  Instead, they should seek to preserve the value of bit 30
in the auxiliary control register.
Acked-by: NTony Lindgren <tony@atomide.com>
Acked-by: NStephen Warren <swarren@nvidia.com>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

We have a mixture of different devices with different register layouts,
but we group all the bits together in an opaque mess.  Split them out
into those which are L2C-310 specific and ones which refer to earlier
devices.  Provide full auxiliary control register definitions.
Acked-by: NTony Lindgren <tony@atomide.com>
Acked-by: NLinus Walleij <linus.walleij@linaro.org>
Acked-by: NShawn Guo <shawn.guo@linaro.org>
Acked-by: NStephen Warren <swarren@nvidia.com>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

When targetting ARCH_MULTIPLATFORM, we may include support for SoCs with
PCI-capable devices (e.g. mach-virt with virtio-pci).

This patch allows PCI support to be selected for these SoCs by selecting
CONFIG_MIGHT_HAVE_PCI when CONFIG_ARCH_MULTIPLATFORM=y and removes the
individual selections from multi-platform enabled SoCs.
Acked-by: NRob Herring <robh@kernel.org>
Signed-off-by: NWill Deacon <will.deacon@arm.com>
Signed-off-by: NOlof Johansson <olof@lixom.net>

The boot ROM on Tegra SoCs supports booting into forced recovery mode
(RCM) by setting a bit in the PMC scratch register 0. Similarily, the
Android bootloader examines some of the bits in this register to disable
autoboot or enter recovery mode.

Support these modes by setting the corresponding bits depending on the
specified reboot command (forced-recovery, bootloader, recovery). Recent
systemd-based distributions allow this to be specified using an optional
argument to the reboot command.
Signed-off-by: NThierry Reding <treding@nvidia.com>
Tested-by: NAlexandre Courbot <acourbot@nvidia.com>
Signed-off-by: NStephen Warren <swarren@nvidia.com>

Commit a7cbe92c ("ARM: tegra: remove tegra EMC scaling driver")
removed the only user of TEGRA_EMC_SCALING_ENABLE. Remove its Kconfig
entry too.
Signed-off-by: NPaul Bolle <pebolle@tiscali.nl>
Signed-off-by: NStephen Warren <swarren@nvidia.com>
Signed-off-by: NArnd Bergmann <arnd@arndb.de>

After moving to description based gpio interface in
rfkill-gpio, the gpio numbers are not used any more.
Signed-off-by: NHeikki Krogerus <heikki.krogerus@linux.intel.com>
Reviewed-by: NMarc Dietrich <marvin24@gmx.de>
Acked-by: NStephen Warren <swarren@nvidia.com>
Acked-by: NAlexandre Courbot <acourbot@nvidia.com>
Signed-off-by: NJohannes Berg <johannes.berg@intel.com>

The I/O rail functions can be used by drivers that are buildable as
modules. Exporting the functions makes sure that they're available.
Signed-off-by: NThierry Reding <treding@nvidia.com>
Signed-off-by: NStephen Warren <swarren@nvidia.com>

Nothing calls into the Tegra EMC (External Memory Controller) scaling
driver any more, so it's dead code. Remove it.

Cc: Joseph Lo <josephl@nvidia.com>
Signed-off-by: NStephen Warren <swarren@nvidia.com>

Many V6 and V7 platforms have an L2x0 cache, so make
CONFIG_MIGHT_HAVE_CACHE_L2X0 visible for V6 and V7 multi-platform
builds.
Signed-off-by: NRob Herring <robh@kernel.org>
Acked-by: NStephen Warren <swarren@nvidia.com>
Acked-by: NArnd Bergmann <arnd@arndb.de>

All V7 platforms can run SMP kernels, so make CONFIG_SMP visible for V7
multi-platform builds.
Signed-off-by: NRob Herring <robh@kernel.org>
Acked-by: NStephen Warren <swarren@nvidia.com>
Acked-by: NArnd Bergmann <arnd@arndb.de>

Multi-platform requires various kconfig options to be selected, so
platforms don't need to select them individually.
Signed-off-by: NRob Herring <robh@kernel.org>
Acked-by: NLinus Walleij <linus.walleij@linaro.org>
Cc: Russell King <linux@arm.linux.org.uk>
Acked-by: NStephen Warren <swarren@nvidia.com>
Tested-by: NStephen Warren <swarren@wwwdotorg.org>
Acked-by: NArnd Bergmann <arnd@arndb.de>

Fix tegra_init_cache() to check whether the system has a PL310 cache
before touching the PL310 registers. This prevents access to non-existent
registers on Tegra114 and later.

Note for stable kernels:
In <= v3.12, the file to patch is arch/arm/mach-tegra/common.c.

Cc: <stable@vger.kernel.org> # v3.9+
Signed-off-by: NStephen Warren <swarren@nvidia.com>
Signed-off-by: NOlof Johansson <olof@lixom.net>

Attempt to invoke the prepare_idle() and do_idle() firmware calls
to power down a CPU so an underlying firmware gets informed of
the idle operation and performs it by itself if designed in such a way.
Signed-off-by: NAlexandre Courbot <acourbot@nvidia.com>
Acked-by: NOlof Johansson <olof@lixom.net>
Signed-off-by: NStephen Warren <swarren@nvidia.com>

USB_ARCH_HAS_EHCI, USB_ARCH_HAS_OHCI, and USB_ARCH_HAS_XHCI were just
removed. Selecting them is a nop. The select statements for these
symbols can be removed too.
Signed-off-by: NPaul Bolle <pebolle@tiscali.nl>
Acked-by: NAlan Stern <stern@rowland.harvard.edu>
Signed-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>

When booting secondary CPU(s) which are not yet powergated, a wrong
check lead to a timeout after 100 jiffies. With this patch, we only
delay powergating if CPUs are still not powered yet.
Signed-off-by: NStefan Agner <stefan@agner.ch>
Reviewed-by: NThierry Reding <treding@nvidia.com>
Signed-off-by: NStephen Warren <swarren@nvidia.com>

arch/arm/mach-tegra/pm.c, kernel/power/console.c and mm/vmpressure.c
were somehow getting slab.h indirectly through cgroup.h which in turn
was getting it indirectly through xattr.h.  A scheduled cgroup change
drops xattr.h inclusion from cgroup.h and breaks compilation of these
three files.  Add explicit slab.h includes to the three files.

A pending cgroup patch depends on this change and it'd be great if
this can be routed through cgroup/for-3.14-fixes branch.
Signed-off-by: NTejun Heo <tj@kernel.org>
Acked-by: NStephen Warren <swarren@wwwdotorg.org>
Cc: Thierry Reding <thierry.reding@gmail.com>
Cc: linux-tegra@vger.kernel.org
Cc: "Rafael J. Wysocki" <rjw@rjwysocki.net>
Cc: linux-pm@vger.kernel.org
Cc: Johannes Weiner <hannes@cmpxchg.org>
Cc: Michal Hocko <mhocko@suse.cz>
Cc: Balbir Singh <bsingharora@gmail.com>
Cc: KAMEZAWA Hiroyuki <kamezawa.hiroyu@jp.fujitsu.com>
Cc: cgroups@vger.kernel.org

Add tegra_io_rail_power_off() and tegra_io_rail_power_on() functions to
put IO rails into or out of deep powerdown mode, respectively.
Signed-off-by: NThierry Reding <treding@nvidia.com>
Signed-off-by: NStephen Warren <swarren@nvidia.com>

A separate register is used to remove the clamps for the GPU on
Tegra124. In order to be able to use the same API, special-case
this particular partition.
Signed-off-by: NThierry Reding <treding@nvidia.com>
Signed-off-by: NStephen Warren <swarren@nvidia.com>

Three new gates have been added for Tegra124: SOR, VIC and IRAM. In
addition, PCIe and SATA gates are again supported, like on Tegra20 and
Tegra30.
Signed-off-by: NThierry Reding <treding@nvidia.com>
Signed-off-by: NStephen Warren <swarren@nvidia.com>

Drivers can use the tegra_powergate_remove_clamping() API during
initialization. In order to allow such drivers to be built as modules,
export the symbol.
Signed-off-by: NThierry Reding <treding@nvidia.com>
Signed-off-by: NStephen Warren <swarren@nvidia.com>

This function can be used by drivers, which in turn may be built as
modules. Export the symbol so it is available to modules.
Signed-off-by: NThierry Reding <treding@nvidia.com>
Signed-off-by: NStephen Warren <swarren@nvidia.com>

This matches the name of the powergate as listed in the TRM.
Signed-off-by: NThierry Reding <treding@nvidia.com>
Signed-off-by: NStephen Warren <swarren@nvidia.com>

Some of the powergate code uses unusual spacing around == and has a tab
instead of a space before an opening parenthesis.
Signed-off-by: NThierry Reding <treding@nvidia.com>
Signed-off-by: NStephen Warren <swarren@nvidia.com>

Use a firmware operation to set the CPU reset handler and only resort to
doing it ourselves if there is none defined.

This supports the booting of secondary CPUs on devices using a TrustZone
secure monitor.
Signed-off-by: NAlexandre Courbot <acourbot@nvidia.com>
Reviewed-by: NTomasz Figa <t.figa@samsung.com>
Reviewed-by: NStephen Warren <swarren@nvidia.com>
Signed-off-by: NStephen Warren <swarren@nvidia.com>

Not all Tegra devices can set the CPU reset handler in the same way.
In particular, devices using a TrustZone secure monitor cannot set it
up directly and need to ask the firmware to do it.

This patch separates the act of setting the reset handler from its
preparation, so the former can be implemented in a different way.
Signed-off-by: NAlexandre Courbot <acourbot@nvidia.com>
Reviewed-by: NTomasz Figa <t.figa@samsung.com>
Reviewed-by: NStephen Warren <swarren@nvidia.com>
Signed-off-by: NStephen Warren <swarren@nvidia.com>

Register the firmware operations for Trusted Foundations if the device
tree indicates it is active on the device.
Signed-off-by: NAlexandre Courbot <acourbot@nvidia.com>
Reviewed-by: NTomasz Figa <t.figa@samsung.com>
Reviewed-by: NStephen Warren <swarren@nvidia.com>
Signed-off-by: NStephen Warren <swarren@nvidia.com>

The pincontrol driver for Tegra124 is build through config
PINCTRL_TEGRA124. Select this config option whenever Tegra124
SoC is enabled.
Signed-off-by: NLaxman Dewangan <ldewangan@nvidia.com>
Signed-off-by: NStephen Warren <swarren@nvidia.com>

Add a missing break to the switch in tegra_init_fuse() which determines
which SoC the code is running on. This prevents the Tegra30+ fuse
handling code from running on Tegra20.

Fixes: 3bd1ae57 ("ARM: tegra: add fuses as device randomness")
Signed-off-by: NStephen Warren <swarren@nvidia.com>
Signed-off-by: NOlof Johansson <olof@lixom.net>

Tegra's clock driver now provides an implementation of the common
reset API (include/linux/reset.h). Use this instead of the old Tegra-
specific API; that will soon be removed.
Signed-off-by: NStephen Warren <swarren@nvidia.com>
Acked-by: NBjorn Helgaas <bhelgaas@google.com>
Acked-By: NTerje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: NThierry Reding <treding@nvidia.com>
Acked-by: NThierry Reding <treding@nvidia.com>

The Tegra clock driver is built unconditionally when Tegra support is
enabled. In order to avoid having to ifdef the forthcoming reset driver
implementation, have ARCH_TEGRA select RESET_CONTROLLER.
Signed-off-by: NStephen Warren <swarren@nvidia.com>
Reviewed-by: NThierry Reding <treding@nvidia.com>