- 17 7月, 2014 1 次提交
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由 Peter De Schrijver 提交于
Add efuse and apbmisc bindings for Tegra20, Tegra30, Tegra114 and Tegra124. Signed-off-by: NPeter De Schrijver <pdeschrijver@nvidia.com> Signed-off-by: NStephen Warren <swarren@nvidia.com> Signed-off-by: NThierry Reding <treding@nvidia.com>
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- 26 2月, 2014 1 次提交
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由 Thierry Reding 提交于
To disable a device tree node, the status property should be set to "disabled", not "disable". Signed-off-by: NThierry Reding <treding@nvidia.com> Signed-off-by: NStephen Warren <swarren@nvidia.com>
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- 19 2月, 2014 1 次提交
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由 Thierry Reding 提交于
The number of the head specifies the index of the display controller unit and is required to properly configure outputs so that they receive video data from the correct source. Signed-off-by: NThierry Reding <treding@nvidia.com> Acked-by: NStephen Warren <swarren@nvidia.com> Signed-off-by: NOlof Johansson <olof@lixom.net>
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- 20 12月, 2013 5 次提交
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由 Thierry Reding 提交于
Add the gr3d device tree node. The gr3d block on Tegra114 is backwards- compatible with the one on Tegra20. Signed-off-by: NThierry Reding <treding@nvidia.com> Signed-off-by: NStephen Warren <swarren@nvidia.com>
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由 Thierry Reding 提交于
Add the device tree for the gr2d hardware found on Tegra114 SoCs. Signed-off-by: NThierry Reding <treding@nvidia.com> Signed-off-by: NStephen Warren <swarren@nvidia.com>
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由 Thierry Reding 提交于
Add device tree nodes for the DSI controllers found on Tegra114 SoCs. Signed-off-by: NThierry Reding <treding@nvidia.com> Signed-off-by: NStephen Warren <swarren@nvidia.com>
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由 Mikko Perttunen 提交于
Add host1x, DC (display controller) and HDMI devices to Tegra114 device tree. Signed-off-by: NMikko Perttunen <mperttunen@nvidia.com> Signed-off-by: NThierry Reding <treding@nvidia.com> Signed-off-by: NStephen Warren <swarren@nvidia.com>
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由 Thierry Reding 提交于
Add a device node for the MIPI calibration block on Tegra114. There is no need to disable it by default because it only enables the clock while performing calibration and therefore shouldn't be consuming any power when unused. Signed-off-by: NThierry Reding <treding@nvidia.com> [swarren, add unit address to new DT node name] Signed-off-by: NStephen Warren <swarren@nvidia.com>
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- 17 12月, 2013 2 次提交
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由 Laxman Dewangan 提交于
Use Tegra pinconrol dt-binding macro to set the values of different pinmux properties of Tegra114 platforms. Signed-off-by: NLaxman Dewangan <ldewangan@nvidia.com> Signed-off-by: NStephen Warren <swarren@nvidia.com>
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由 Stephen Warren 提交于
DT node names should include a unit address iff the node has a reg property. For Tegra DTs at least, we were previously applying a different rule, namely that node names only needed to include a unit address if it was required to make the node name unique. Consequently, many unit addresses are missing. Add them. Signed-off-by: NStephen Warren <swarren@nvidia.com>
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- 12 12月, 2013 4 次提交
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由 Stephen Warren 提交于
Now that all Tegra drivers have been converted to use DMA APIs which retrieve DMA channel information from standard DMA DT properties, we can remove all the legacy DT DMA-related properties. Signed-off-by: NStephen Warren <swarren@nvidia.com> Reviewed-by: NThierry Reding <treding@nvidia.com>
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由 Stephen Warren 提交于
Now that all Tegra drivers have been converted to use the common reset framework, we can remove all the legacy DT clocks/clock-names entries for "clocks" that were only used with the old custom Tegra module reset API. Signed-off-by: NStephen Warren <swarren@nvidia.com> Reviewed-by: NThierry Reding <treding@nvidia.com>
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由 Stephen Warren 提交于
This patch switches the Tegra DT files to use the standard DMA DT bindings rather than custom properties. Note that the legacy properties are not yet removed; the drivers must be updated to use the new properties first. Signed-off-by: NStephen Warren <swarren@nvidia.com> Reviewed-by: NThierry Reding <treding@nvidia.com>
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由 Stephen Warren 提交于
An earlier patch updated the Tegra DT bindings to require resets and reset-names properties to be filled in. This patch updates the DT files to include those properties. Note that any legacy clocks and clock-names entries that are replaced by reset properties are not yet removed; the drivers must be updated to use the new resets and reset-names properties first. Signed-off-by: NStephen Warren <swarren@nvidia.com>
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- 31 10月, 2013 1 次提交
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由 Hiroshi Doyu 提交于
The IOMMU node's reg property contains completely bogus values! Somehow, this had no practical effect, despite the fact the IOMMU driver appears to be writing to those registers. I suppose that since no HW modules is actually at that address, the writes simply had no effect. Note that I'm not CCing stable here, even though the problem exists as far back as v3.9, simply because this patch doesn't fix any observed issue, and I don't want to run the risk of suddenly writing to some registers and causing a regression. Signed-off-by: NHiroshi Doyu <hdoyu@nvidia.com> [swarren, wrote commit description] Signed-off-by: NStephen Warren <swarren@nvidia.com> Signed-off-by: NOlof Johansson <olof@lixom.net>
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- 14 8月, 2013 1 次提交
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由 Mikko Perttunen 提交于
Device tree entries for the three EHCI controllers on Tegra114. Enables the the third controller (USB host) on Dalmore. Signed-off-by: NMikko Perttunen <mperttunen@nvidia.com> Signed-off-by: NStephen Warren <swarren@nvidia.com>
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- 29 5月, 2013 5 次提交
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由 Stephen Warren 提交于
Add nodes for the Tegra114 AHUB and I2S controllers. Signed-off-by: NStephen Warren <swarren@nvidia.com>
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由 Hiroshi Doyu 提交于
Use the Tegra114 CAR binding header (tegra114-car.h) to replace magic numbers in the device tree. For example, - clocks = <&tegra_car 28>; + clocks = <&tegra_car CLK_HOST1X>; Signed-off-by: NHiroshi Doyu <hdoyu@nvidia.com> [swarren, updated since tegra20-car.h moved for consistency] Signed-off-by: NStephen Warren <swarren@nvidia.com>
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由 Stephen Warren 提交于
Use the GIC and standard IRQ binding defines in all IRQ specifiers. Signed-off-by: NStephen Warren <swarren@nvidia.com>
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由 Stephen Warren 提交于
Use TEGRA_GPIO() macro to name all GPIOs referenced by GPIO properties, and some interrupts properties. Use standard GPIO flag defines too. Signed-off-by: NStephen Warren <swarren@nvidia.com>
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由 Stephen Warren 提交于
Replace /include/ (dtc) with #include (C pre-processor) for all Tegra DT files, so that gcc -E handles the entire include tree, and hence any of those files can #include some other file e.g. for constant definitions. This allows future use of #defines and header files in order to define names for various constants, such as the IDs and flags in GPIO specifiers. Use of those features will increase the readability of the device tree files. Signed-off-by: NStephen Warren <swarren@nvidia.com>
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- 05 4月, 2013 8 次提交
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由 Laxman Dewangan 提交于
NVIDIA's Tegra114 has 6 SPI controllers. These controllers are redesign on T114 with different register interface. Add DT entry for spi controllers and make it compatible with "nvidia,tegra114-spi", since they are a new incompatible design. Signed-off-by: NLaxman Dewangan <ldewangan@nvidia.com> [swarren: fixed reg property for 3rd SPI controller] Signed-off-by: NStephen Warren <swarren@nvidia.com>
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由 Laxman Dewangan 提交于
NVIDIA's Tegra114 SoCs have the matrix keyboard controller which supports 11x8 type of matrix. The number of rows and columns are configurable. Add DT entry for KBC controller with compatibility as "nvidia,tegra114-kbc". Signed-off-by: NLaxman Dewangan <ldewangan@nvidia.com> Signed-off-by: NStephen Warren <swarren@nvidia.com>
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由 Laxman Dewangan 提交于
Add APB DMA requestor and serial aliases for serial controller. There are two serial drivers i.e. 8250 based simple serial driver and APB DMA based serial driver for higher baudrate and performace. The simple serial driver is selected by compatible value "nvidia,tegra114-uart", "nvidia,tegra20-uart", and the APB DMA based driver is selected by compatible value "nvidia,tegra114-hsuart", "nvidia,tegra30-hsuart". Signed-off-by: NLaxman Dewangan <ldewangan@nvidia.com> Signed-off-by: NStephen Warren <swarren@nvidia.com>
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由 Laxman Dewangan 提交于
NVIDIA's Tegra114 has 5 I2C controllers. These controllers have the following changes which makes incompatible with previous hardware: - Single clock source to I2C controller. - Interrupt support for per packet transfer. Add DT entry for I2C controllers and make it compatible with "nvidia,tegra114-i2c". Signed-off-by: NLaxman Dewangan <ldewangan@nvidia.com> [swarren: fixed location of status property for consistency] Signed-off-by: NStephen Warren <swarren@nvidia.com>
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由 Laxman Dewangan 提交于
NVIDIA's Tegra114 has 32 channels APB DMA controller. Add DT entry for APB DMA controllers and make it compatible with "nvidia,tegra114-apbdma". Tegra114 DMA controller is not compatible with Tegra30/Tegra20 DMA controller driver as in Tegra114, the global pause also clock gate the DMA register and hence it iw not possible to write the DMA register with global pause. Signed-off-by: NLaxman Dewangan <ldewangan@nvidia.com> [swarren: fixed DT node order] Signed-off-by: NStephen Warren <swarren@nvidia.com>
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由 Andrew Chew 提交于
This patch adds a device tree node for the four PWM controllers present on Tegra114. Signed-off-by: NAndrew Chew <achew@nvidia.com> Signed-off-by: NStephen Warren <swarren@nvidia.com>
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由 Pritesh Raithatha 提交于
This patch adds in the SDHCI nodes for the busses supported on Tegra114 boards. Signed-off-by: NPritesh Raithatha <praithatha@nvidia.com> [Rhyland added clk refs to & reordered sdhci nodes and removed spaces] Signed-off-by: NRhyland Klein <rklein@nvidia.com> [swarren: fixed DT node sort order] Signed-off-by: NStephen Warren <swarren@nvidia.com>
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由 Peter De Schrijver 提交于
Add references to tegra_car clocks for the basic device nodes. Also remove the clock-frequency property of the serial node as the UART driver can now use the clock framework to obtain the frequency. Signed-off-by: NPeter De Schrijver <pdeschrijver@nvidia.com> Acked-by: NMike Turquette <mturquette@linaro.org> Signed-off-by: NStephen Warren <swarren@nvidia.com>
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- 04 4月, 2013 1 次提交
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由 Joseph Lo 提交于
Adding the bindings of the clock source of PMC in DT. Signed-off-by: NJoseph Lo <josephl@nvidia.com> Signed-off-by: NStephen Warren <swarren@nvidia.com>
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- 12 3月, 2013 1 次提交
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由 Joseph Lo 提交于
The PMC HW is not 100% compatible across all Tegra series. We need to specify them in DT. Signed-off-by: NJoseph Lo <josephl@nvidia.com> Signed-off-by: NStephen Warren <swarren@nvidia.com>
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- 30 1月, 2013 3 次提交
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由 Laxman Dewangan 提交于
Add DT entry for pinmux and drive configuration addresses. Signed-off-by: NLaxman Dewangan <ldewangan@nvidia.com> Signed-off-by: NStephen Warren <swarren@nvidia.com>
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由 Laxman Dewangan 提交于
Tegra114 has the GPIO controllers with 8 GPIO bank and each bank supports 32 pins. Add DT entry for GPIO controller. Tegra114 GPIO controller is compatible with Tegra30 GPIO controller driver. Signed-off-by: NLaxman Dewangan <ldewangan@nvidia.com> Signed-off-by: NStephen Warren <swarren@nvidia.com>
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由 Hiroshi Doyu 提交于
Add SMMU entry. Signed-off-by: NHiroshi Doyu <hdoyu@nvidia.com> Signed-off-by: NStephen Warren <swarren@nvidia.com>
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- 29 1月, 2013 2 次提交
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由 Hiroshi Doyu 提交于
Add AHB entry. Signed-off-by: NHiroshi Doyu <hdoyu@nvidia.com> Signed-off-by: NStephen Warren <swarren@nvidia.com>
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由 Hiroshi Doyu 提交于
Initial support for Tegra 114 SoC. This is expected to be included in the board DTS files, Tegra 114 SoC based evaluation board family. Signed-off-by: NHiroshi Doyu <hdoyu@nvidia.com> Signed-off-by: NStephen Warren <swarren@nvidia.com>
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