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  1. 10 6月, 2015 7 次提交
    • K
      i2c: brcmstb: Add Broadcom settop SoC i2c controller driver · dd1aa252
      由 Kamal Dasu 提交于 
      Adding support for i2c controller driver for Broadcom settop
SoCs.
Signed-off-by: NKamal Dasu <kdasu.kdev@gmail.com>
[wsa: removed superfluous owner in platform_driver]
Signed-off-by: NWolfram Sang <wsa@the-dreams.de>
      dd1aa252
    • C
      i2c: at91: add support to FIFOs · 5e3cfc6c
      由 Cyrille Pitchen 提交于 
      When FIFOs are available and enabled, the driver now configures the Atmel
eXtended DMA Controller to perform word accesses instead of byte accesses
when possible.
The actual access width depends on the size of the buffer to transmit.

To enable FIFO support the "atmel,fifo-size" property must be set properly
in the I2C controller node of the device tree.
Signed-off-by: NCyrille Pitchen <cyrille.pitchen@atmel.com>
Acked-by: NLudovic Desroches <ludovic.desroches@atmel.com>
Signed-off-by: NWolfram Sang <wsa@the-dreams.de>
      5e3cfc6c
    • C
      i2c: at91: print hardware version · 6ce461ea
      由 Cyrille Pitchen 提交于 
      The probe() function now prints the hardware version of the I2C
controller.
Signed-off-by: NCyrille Pitchen <cyrille.pitchen@atmel.com>
[wsa: s/version/hw version/] for clarity]
Acked-by: NLudovic Desroches <ludovic.desroches@atmel.com>
Signed-off-by: NWolfram Sang <wsa@the-dreams.de>
      6ce461ea
    • C
      i2c: at91: add support for new alternative command mode · 0ef6f321
      由 Cyrille Pitchen 提交于 
      The alternative command mode was introduced to simplify the transmission
of STOP conditions and to solve timing and latency issues around them.

This mode relies on a new register, the Alternative Command Register,
which must be set at the same time as the Master Mode Register. This new
register was designed to allow simple setup of basic combined transactions
built from up to two unitary transactions.

Indeed, the ACR is split into two areas, which describe one unitary
transaction each. Each area is filled with Data Length 8bit counter, a
Direction and a PEC Request bit. The PEC bit is only used in SMBus mode
and is not supported by this driver yet. Also when using alternative
command mode, the MREAD bit from the Master Mode Register is ignored.
Instead the Direction bits from ACR are used to setup the direction, read
or write, of each unitary transaction. Finally the 8bit counters must
filled with the data length of their respective transaction. Then if only
one transaction is to be used, the data length of the second one must be
set to zero. At the moment, this driver uses only the first transaction.

In addition to MMR and ACR, the Control Register also need to be written
to enable the alternative command mode. That's the purpose of its ACMEN
bit, which stands for Alternative Command Mode Enable.

Note that the alternative command mode is compatible with the use of the
Internal Address Register. So combined transactions for eeprom read are
actually implemented with the Internal Address Register. This register is
written with up to 3 bytes, which are the internal address sent to the
slave through the first write transaction. Then the first area of the ACR
describe the write transaction to follow, which carries the data to be
read from the eeprom. The second area of the ACR is not used so its Data
Length 8bit counter is cleared.

For each byte sent or received by the device, the Data Length 8bit counter
is decremented. When it reaches 0, a STOP condition is automatically sent.
Signed-off-by: NCyrille Pitchen <cyrille.pitchen@atmel.com>
Acked-by: NLudovic Desroches <ludovic.desroches@atmel.com>
Signed-off-by: NWolfram Sang <wsa@the-dreams.de>
      0ef6f321
    • C
      i2c: at91: update documentation for DT bindings · 0ba82c95
      由 Cyrille Pitchen 提交于 
      add a new value "atmel,sama5d2-i2c" for the "compatible" property.
add a new optional property "atmel,fifo-size" to enable FIFO support when
available.
add missing optional properties "dmas" and "dma-names".
Signed-off-by: NCyrille Pitchen <cyrille.pitchen@atmel.com>
Acked-by: NLudovic Desroches <ludovic.desroches@atmel.com>
Signed-off-by: NWolfram Sang <wsa@the-dreams.de>
      0ba82c95
    • C
      i2c: at91: use BIT() macro to define register bits · e84cf8f0
      由 Cyrille Pitchen 提交于 
      This patch just fixes typo before applying later patches which will use
register bits with index above 16.
Signed-off-by: NCyrille Pitchen <cyrille.pitchen@atmel.com>
Acked-by: NLudovic Desroches <ludovic.desroches@atmel.com>
Signed-off-by: NWolfram Sang <wsa@the-dreams.de>
      e84cf8f0
    • C
      i2c: at91: fix a race condition when using the DMA controller · 93563a6a
      由 Cyrille Pitchen 提交于 
      For TX transactions, the TXCOMP bit in the Status Register is cleared
when the first data is written into the Transmit Holding Register.

In the lines from at91_do_twi_transfer():
at91_twi_write_data_dma(dev);
at91_twi_write(dev, AT91_TWI_IER, AT91_TWI_TXCOMP);

the TXCOMP interrupt may be enabled before the DMA controller has
actually started to write into the THR. In such a case, the TXCOMP bit
is still set into the Status Register so the interrupt is triggered
immediately. The driver understands that a transaction completion has
occurred but this transaction hasn't started yet. Hence the TXCOMP
interrupt is no longer enabled by at91_do_twi_transfer() but instead
by at91_twi_write_data_dma_callback().

Also, the TXCOMP bit in the Status Register in not a clear on read flag
but a snapshot of the transmission state at the time the Status
Register is read.
When a NACK error is dectected by the I2C controller, the TXCOMP, NACK
and TXRDY bits are set together to 1 in the SR. If enabled, the TXCOMP
interrupt is triggered at the same time. Also setting the TXRDY to 1
triggers the DMA controller to write the next data into the THR. Such
a write resets the TXCOMP bit to 0 in the SR. So depending on when the
interrupt handler reads the SR, it may fail to detect the NACK error
if it relies on the TXCOMP bit. The NACK bit and its interrupt should
be used instead.

For RX transactions, the TXCOMP bit in the Status Register is cleared
when the START bit is set into the Control Register. However to unify
the management of the TXCOMP bit when the DMA controller is used, the
TXCOMP interrupt is now enabled by the DMA callbacks for both TX and
RX transfers.
Signed-off-by: NCyrille Pitchen <cyrille.pitchen@atmel.com>
Cc: stable@vger.kernel.org #3.10 and later
Acked-by: NLudovic Desroches <ludovic.desroches@atmel.com>
Signed-off-by: NWolfram Sang <wsa@the-dreams.de>
      93563a6a
  3. 03 6月, 2015 2 次提交
  5. 02 6月, 2015 2 次提交
  7. 01 6月, 2015 10 次提交
  9. 13 5月, 2015 3 次提交
  11. 12 5月, 2015 4 次提交
    • P
      i2c: omap: Add calls for pinctrl state select · 096ea30c
      由 Pascal Huerst 提交于 
      This adds calls to pinctrl subsystem in order to switch pin states
on suspend/resume if you provide a "sleep" state in DT.

If no "sleep" state is provided in the DT, these calls turn
to NOPs, so we don't need error checking here.
Signed-off-by: NPascal Huerst <pascal.huerst@gmail.com>
Reviewed-by: NSekhar Nori <nsekhar@ti.com>
Signed-off-by: NWolfram Sang <wsa@the-dreams.de>
      096ea30c
    • G
      i2c: Allow compile test of GPIO consumers if !GPIOLIB · 7e5cd69a
      由 Geert Uytterhoeven 提交于 
      The GPIO subsystem provides dummy GPIO consumer functions if GPIOLIB is
not enabled. Hence drivers that depend on GPIOLIB, but use GPIO consumer
functionality only, can still be compiled if GPIOLIB is not enabled.

Relax the dependency on GPIOLIB if COMPILE_TEST is enabled, where
appropriate.
Signed-off-by: NGeert Uytterhoeven <geert@linux-m68k.org>
Signed-off-by: NWolfram Sang <wsa@the-dreams.de>
      7e5cd69a
    • S
      i2c: xiic: Fix kerneldoc warnings · bea6ff02
      由 Shubhrajyoti Datta 提交于 
      info(drivers/i2c/busses/i2c-xiic.c:55): Scanning doc for struct xiic_i2c
Warning(drivers/i2c/busses/i2c-xiic.c:79): No description found for parameter 'endianness'
Signed-off-by: NShubhrajyoti Datta <shubhraj@xilinx.com>
Signed-off-by: NWolfram Sang <wsa@the-dreams.de>
      bea6ff02
    • D
      i2c: rk3x: Increase wait timeout to 1 second · 4489750f
      由 Doug Anderson 提交于 
      Although unlikely, it is remotely possible for an i2c command to need
more than 200ms complete. Unlike smbus, i2c devices can clock stretch
for an unspecified amount of time. The longest time I've seen
specified for a device is 144ms (bq27541 battery gas), but one could
imagine a device taking a bit slower. 1 second "ought to be enough for
anyone."

The above is not the only justifcation for going above 200ms for a
timeout, though.  It turns out that if you've got a large number of
printks going out to a serial console, interrupts on a CPU can be
disabled for hundreds of milliseconds. That's not a great situation to
be in to start with (maybe we should put a cap in vprintk_emit()) but
it's pretty annoying to start seeing unexplained i2c timeouts.

Note that to understand why we can timeout when printk has interrupts
disabled, you need to understand that on current Linux ARM kernels
interrupts are routed to a single CPU in a multicore system. Thus,
you can get:

1. CPU1 is running rk3x_i2c_xfer()
2. CPU0 calls vprintk_emit(), which disables all IRQs on CPU0.
3. I2C interrupt is ready but is set to only run on CPU0, where IRQs
   are disabled.
4. CPU1 timeout expires. I2C interrupt is still ready, but CPU0 is
   still sitting in the same vprintk_emit()
5. CPU1 sees that no interrupt happened in 200ms, so timeout.

A normal system shouldn't see i2c timeouts anyway, so increasing the
timeout should help people debugging without hurting other people
excessively.
Signed-off-by: NDoug Anderson <dianders@chromium.org>
Tested-by: NCaesar Wang <wxt@rock-chips.com>
Acked-by: NUwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: NWolfram Sang <wsa@the-dreams.de>
      4489750f
  13. 04 5月, 2015 8 次提交
  15. 03 5月, 2015 3 次提交
    • J
      ext4: fix growing of tiny filesystems · 2c869b26
      由 Jan Kara 提交于 
      The estimate of necessary transaction credits in ext4_flex_group_add()
is too pessimistic. It reserves credit for sb, resize inode, and resize
inode dindirect block for each group added in a flex group although they
are always the same block and thus it is enough to account them only
once. Also the number of modified GDT block is overestimated since we
fit EXT4_DESC_PER_BLOCK(sb) descriptors in one block.

Make the estimation more precise. That reduces number of requested
credits enough that we can grow 20 MB filesystem (which has 1 MB
journal, 79 reserved GDT blocks, and flex group size 16 by default).
Signed-off-by: NJan Kara <jack@suse.cz>
Signed-off-by: NTheodore Ts'o <tytso@mit.edu>
Reviewed-by: NEric Sandeen <sandeen@redhat.com>
      2c869b26
    • D
      ext4: move check under lock scope to close a race. · 280227a7
      由 Davide Italiano 提交于 
      fallocate() checks that the file is extent-based and returns
EOPNOTSUPP in case is not. Other tasks can convert from and to
indirect and extent so it's safe to check only after grabbing
the inode mutex.
Signed-off-by: NDavide Italiano <dccitaliano@gmail.com>
Signed-off-by: NTheodore Ts'o <tytso@mit.edu>
Cc: stable@vger.kernel.org
      280227a7
    • L
      ext4: fix data corruption caused by unwritten and delayed extents · d2dc317d
      由 Lukas Czerner 提交于 
      Currently it is possible to lose whole file system block worth of data
when we hit the specific interaction with unwritten and delayed extents
in status extent tree.

The problem is that when we insert delayed extent into extent status
tree the only way to get rid of it is when we write out delayed buffer.
However there is a limitation in the extent status tree implementation
so that when inserting unwritten extent should there be even a single
delayed block the whole unwritten extent would be marked as delayed.

At this point, there is no way to get rid of the delayed extents,
because there are no delayed buffers to write out. So when a we write
into said unwritten extent we will convert it to written, but it still
remains delayed.

When we try to write into that block later ext4_da_map_blocks() will set
the buffer new and delayed and map it to invalid block which causes
the rest of the block to be zeroed loosing already written data.

For now we can fix this by simply not allowing to set delayed status on
written extent in the extent status tree. Also add WARN_ON() to make
sure that we notice if this happens in the future.

This problem can be easily reproduced by running the following xfs_io.

xfs_io -f -c "pwrite -S 0xaa 4096 2048" \
          -c "falloc 0 131072" \
          -c "pwrite -S 0xbb 65536 2048" \
          -c "fsync" /mnt/test/fff

echo 3 > /proc/sys/vm/drop_caches
xfs_io -c "pwrite -S 0xdd 67584 2048" /mnt/test/fff

This can be theoretically also reproduced by at random by running fsx,
but it's not very reliable, though on machines with bigger page size
(like ppc) this can be seen more often (especially xfstest generic/127)
Signed-off-by: NLukas Czerner <lczerner@redhat.com>
Signed-off-by: NTheodore Ts'o <tytso@mit.edu>
Cc: stable@vger.kernel.org
      d2dc317d
  17. 02 5月, 2015 1 次提交