1. 18 10月, 2015 2 次提交
  2. 05 10月, 2015 2 次提交
  3. 22 6月, 2015 1 次提交
    • P
      serial: 8250_ingenic: support for Ingenic SoC UARTs · 0cf985f4
      Paul Burton 提交于
      Introduce a driver suitable for use with the UARTs present in
      Ingenic SoCs such as the JZ4740 & JZ4780. These are described as being
      ns16550 compatible but aren't quite - they require the setting of an
      extra bit in the FCR register to enable the UART module. The serial_out
      implementation is the same as that in arch/mips/jz4740/serial.c - which
      will shortly be removed.
      Signed-off-by: NPaul Burton <paul.burton@imgtec.com>
      Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
      Cc: Jiri Slaby <jslaby@suse.cz>
      Cc: Lars-Peter Clausen <lars@metafoo.de>
      Cc: linux-serial@vger.kernel.org
      Cc: linux-mips@linux-mips.org
      Cc: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
      Cc: Peter Hurley <peter@hurleysoftware.com>
      Cc: Alan Cox <alan@linux.intel.com>
      Cc: linux-kernel@vger.kernel.org
      Cc: Matthias Brugger <matthias.bgg@gmail.com>
      Cc: Ricardo Ribalda Delgado <ricardo.ribalda@gmail.com>
      Cc: Tony Lindgren <tony@atomide.com>
      Cc: John Crispin <blogic@openwrt.org>
      Patchwork: https://patchwork.linux-mips.org/patch/10159/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
      0cf985f4
  4. 01 6月, 2015 2 次提交
  5. 27 3月, 2015 1 次提交
    • A
      serial: 8250_pci: replace switch-case by formula · 21947ba6
      Andy Shevchenko 提交于
      This patch replaces a switch-case by a formula using rational best
      approximation that does necessary calculations for byt_set_termios().
      
      Below is a list of the calculations done for all defined baud rates. Each line
      in a format: 1) numerator, 2) denominator, 3) prescaler, 4) Fuart, 5) port UART
      clock, 6) list of baud rates with DLAB values.
      
      4        5        16 80000000   80000000   2500000(2)
      14       25       16 56000000   56000000   3500000(1)
      16       25       16 64000000   64000000   500000(8),1000000(4),2000000(2),
      					4000000(1)
      24       25       16 96000000   96000000   1500000(4),3000000(2)
      2180     3103     16 70254592   70254592   134(32768)
      2304     3125     16 73728000   73728000   576000(8),1152000(4)
      8192     15625    16 52428800   52428800   50(65536),200(16384)
      9216     15625    16 58982400   58982400   1800(2048),57600(64),115200(32),
      					230400(16),460800(8),921600(4),1843200(2)
      12288    15625    16 78643200   78643200   75(65536),150(32768),300(16384),
      					600(8192),1200(4096),2400(2048),
      					4800(1024),9600(512),19200(256),38400(128)
      9893     17154    16 57671680   57671680   110(32768)
      Signed-off-by: NAndy Shevchenko <andriy.shevchenko@linux.intel.com>
      Reviewed-by: NPeter Hurley <peter@hurleysoftware.com>
      Reviewed-by: NHeikki Krogerus <heikki.krogerus@linux.intel.com>
      Signed-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>
      21947ba6
  6. 10 1月, 2015 1 次提交
  7. 07 11月, 2014 1 次提交
  8. 06 11月, 2014 1 次提交
    • S
      tty: serial: Add 8250-core based omap driver · 61929cf0
      Sebastian Andrzej Siewior 提交于
      This patch provides a 8250-core based UART driver for the internal OMAP
      UART. The long term goal is to provide the same functionality as the
      current OMAP uart driver and DMA support.
      I tried to merge omap-serial code together with the 8250-core code.
      There should should be hardly a noticable difference. The trigger levels
      are different compared to omap-serial:
      - omap serial
        TX: Interrupt comes after TX FIFO has room for 16 bytes.
            TX of 4096 bytes in one go results in 256 interrupts
      
        RX: Interrupt comes after there is on byte in the FIFO.
            RX of 4096 bytes results in 4096 interrupts.
      
      - this driver
        TX: Interrupt comes once the TX FIFO is empty.
            TX of 4096 bytes results in 65 interrupts. That means there will
            be gaps on the line while the driver reloads the FIFO.
      
        RX: Interrupt comes once there are 48 bytes in the FIFO or less over
            "longer" time frame. We have
                1 / 11520 * 10^3 * 16 => 1.38… ms
            1.38ms to react and purge the FIFO on 115200,8N1. Since the other
            driver fired after each byte it had ~5.47ms time to react. This
            _may_ cause problems if one relies on no missing bytes and has no
            flow control. On the other hand we get only 85 interrupts for the
            same amount of data.
      
      It has been only tested as console UART on am335x-evm, dra7-evm and
      beagle bone. I also did some longer raw-transfers to meassure the load.
      
      The device name is ttyS based instead of ttyO. If a ttyO based node name
      is required please ask udev for it. If both driver are activated (this
      and omap-serial) then this serial driver will take control over the
      device due to the link order
      
      v9…v10:
      	- Tony noticed that omap3 won't show anything after waking up
      	  from core off. In v9 I reworked the register restore and set
      	  IER to 0 by accident. This went unnoticed because start_tx
      	  usually sets ier (either due to DMA bug or due to TX-complete
      	  IRQ).
      	- dropped EFR and SLEEP from capabilities. We do have both but
      	  nobody should touch it. We already handle SLEEP ourself.
      	- make the private copy of the registers (like EFR) u8 instead
      	  u32
      	- drop MDR1 & DL[ML] reset in restore registers. Does not look
      	  required it is set to the required value later.
      	- update MDR1 & SCR only if changed.
      	- set MDR1 as the last thing. The errata says that we should
      	  setup everything before MDR1 set.
      	- avoid div by 0 in omap_8250_get_divisor() if baud rate gets
      	  very large (Frans Klaver fixed the same thing omap-serial)
      	- drop "is in early stage" from Kconfig.
      v8…v9:
      	- less on a file seems to hang the am335x after a while. I
      	  believe I introduce this bug a while ago since I can reproduce
      	  this prior to v8. Fixed by redoing the omap8250_restore_regs()
      v7…v8:
      	- redo the register write. There is now one function for that
      	  which is used from set_termios() and runtime-resume.
      	- drop PORT_OMAP_16750 and move the setup to the omap file. We
      	  have our own set termios function anyway (Heikki Krogerus)
      	- use MEM instead of MEM32. TRM of AM/DM37x says that 32bit
      	  access on THR might result in data abort. We only need 32bit
      	  access in the errata function which is before we use 8250's
      	  read function so it doesn't matter.
      v4…v7:
      	- change trigger levels after some tests with raw transfers.
      v3…v4:
      	- drop RS485 support
      	- wire up ->throttle / ->unthrottle
      v2…v3:
      	- wire up startup & shutdown for wakeup-irq handling.
      	- RS485 handling (well the core does).
      
      v1…v2:
      	- added runtime PM. Could somebody could please double check
      	  this?
      	- added omap_8250_set_termios()
      Reviewed-by: NTony Lindgren <tony@atomide.com>
      Tested-by: NTony Lindgren <tony@atomide.com>
      Tested-by: NFrans Klaver <frans.klaver@xsens.com>
      Signed-off-by: NSebastian Andrzej Siewior <bigeasy@linutronix.de>
      Reviewed-by: NPeter Hurley <peter@hurleysoftware.com>
      Signed-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>
      61929cf0
  9. 10 9月, 2014 1 次提交
  10. 09 9月, 2014 1 次提交
  11. 25 4月, 2014 2 次提交
  12. 26 11月, 2013 1 次提交
  13. 27 7月, 2013 1 次提交
  14. 04 6月, 2013 1 次提交
  15. 26 3月, 2013 1 次提交
  16. 30 1月, 2013 1 次提交
  17. 16 1月, 2013 3 次提交
  18. 26 10月, 2012 1 次提交
  19. 27 9月, 2012 1 次提交
  20. 18 5月, 2012 1 次提交
  21. 05 5月, 2012 1 次提交
    • M
      serial8250-em: Emma Mobile UART driver V2 · 22886ee9
      Magnus Damm 提交于
      This is V2 of the Emma Mobile 8250 platform driver.
      
      The hardware itself has according to the data sheet
      up to 64 byte FIFOs but at this point we only make
      use of the 16550 compatible mode.
      
      To support this piece of hardware the common UART
      registers need to be remapped, and the access size
      differences need to be handled.
      
      The DLL and DLM registers can due to offset collision
      not be remapped easily, and because of that this
      driver makes use of ->dl_read() and ->dl_write()
      callbacks. This in turn requires a registration
      function that takes 8250-specific paramenters.
      
      Future potential enhancements include DT support,
      early platform driver console and fine grained PM.
      Signed-off-by: NMagnus Damm <damm@opensource.se>
      Acked-by: NAlan Cox <alan@linux.intel.com>
      Acked-by: NArnd Bergmann <arnd@arndb.de>
      Signed-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>
      22886ee9
  22. 25 1月, 2012 1 次提交