1. 06 2月, 2015 8 次提交
  2. 02 2月, 2015 2 次提交
  3. 21 1月, 2015 5 次提交
  4. 16 1月, 2015 3 次提交
  5. 13 1月, 2015 5 次提交
    • G
      mtd: denali: fix incorrect bitmask error in denali_setup_dma · 7c272ac5
      Graham Moore 提交于
      commit 3157d1ed ("mtd: denali: remove unnecessary casts") introduced
      an error by using a wrong bitmask.
      
      A uint16_t cast was replaced with & 0xff, should be & 0xffff.
      Signed-off-by: NGraham Moore <grmoore@opensource.altera.com>
      Signed-off-by: NDinh Nguyen <dinguyen@opensource.altera.com>
      Signed-off-by: NBrian Norris <computersforpeace@gmail.com>
      7c272ac5
    • L
      mtd: st_spi_fsm: Fix [-Wsign-compare] build warning · a9b679bf
      Lee Jones 提交于
      drivers/mtd/devices/st_spi_fsm.c:1647:17:
        warning: comparison between signed and unsigned integer expressions
      Signed-off-by: NLee Jones <lee.jones@linaro.org>
      Signed-off-by: NBrian Norris <computersforpeace@gmail.com>
      a9b679bf
    • L
      mtd: st_spi_fsm: Obtain and use EMI clock · 69d5af8d
      Lee Jones 提交于
      ST's Common Clk Framework is now available. This patch ensures the FSM
      makes use of it by obtaining and enabling the EMI clock. If system fails
      to provide the EMI clock, we bomb out.
      Signed-off-by: NLee Jones <lee.jones@linaro.org>
      Signed-off-by: NBrian Norris <computersforpeace@gmail.com>
      69d5af8d
    • L
      mtd: st_spi_fsm: Extend fsm_clear_fifo to handle unwanted bytes · 5ecd3ea1
      Lee Jones 提交于
      Under certain conditions, the SPI-FSM Controller can be left in a state where
      the data FIFO is not entirely empty.  This can lead to problems where subsequent
      data transfers appear to have been shifted by a number of unidentified bytes.
      
      One simple example would be an errant FSM sequence which loaded more data to the
      FIFO than was read by the host.  Another more interesting case results from an
      obscure artefact in the FSM Controller.  When switching from data transfers in
      x4 or x2 mode to data transfers in x1 mode, extraneous bytes will appear in the
      FIFO, unless the previous data transfer was a multiple of 32 cycles (i.e. 8
      bytes for x2, and 16 bytes for x4).  This applies equally whether FSM is being
      operated directly by a S/W driver, or by the SPI boot-controller in FSM-Boot
      mode.  Furthermore, data in the FIFO not only survive a transition between
      FSM-Boot and FSM, but also a S/W reset of IP block [1].
      
      By taking certain precautions, it is possible to prevent the driver from causing
      this type of problem (e.g. ensuring that the host and programmed sequence
      agree on the transfer size, and restricting transfer sizes to multiples of
      32-cycles [2]).  However, at the point the driver is loaded, no assumptions can be
      made regarding the state of the FIFO.  Even if previous S/W drivers have behaved
      correctly, it is impossible to control the number of transactions serviced by
      the controller operating in FSM-Boot.
      
      To address this problem, we ensure the FIFO is cleared during initialisation,
      before performing any FSM operations.  Previously, the fsm_clear_fifo() code was
      capable of detecting and clearing any unwanted 32-bit words from the FIFO.  This
      patch extends the capability to handle an arbitrary number of bytes present in
      the FIFO [3].  Now that the issue is better understood, we also remove the calls
      to fsm_clear_fifo() following the fsm_read() and fsm_write() operations.
      
      The process of actually clearing the FIFO deserves a mention.  While the FIFO
      may contain any number of bytes, the SPI_FAST_SEQ_STA register only reports the
      number of complete 32-bit words present.  Furthermore, data can only be drained
      from the FIFO by reading complete 32-bit words.  With this in mind, a two stage
      process is used to the clear the FIFO:
      
          1. Read any complete 32-bit words from the FIFO, as reported by the
                 SPI_FAST_SEQ_STA register.
      
          2. Mop up any remaining bytes.  At this point, it is not known if there
                 are 0, 1, 2, or 3 bytes in the FIFO.  To handle all cases, a dummy
                 FSM sequence is used to load one byte at a time, until a complete
                 32-bit word is formed; at most, 4 bytes will need to be loaded.
      
      [1] Although this issue has existed since early versions of the SPI-FSM
          controller, its full extent only emerged recently as a consequence of the
          targetpacks starting to use FSM-Boot(x4) as the default configuration.
      
      [2] The requirement to restrict transfers to multiples of 32 cycles was found
          empirically back when DUAL and QUAD mode support was added.  The current
          analysis now gives a satisfactory explanation for this requirement.
      
      [3] Theoretically, it is possible for the FIFO to contain an arbitrary number of
          bits.  However, since there are no known use-cases that leave incomplete
          bytes in the FIFO, only words and bytes are considered here.
      Signed-off-by: NAngus Clark <angus.clark@st.com>
      Signed-off-by: NLee Jones <lee.jones@linaro.org>
      Signed-off-by: NBrian Norris <computersforpeace@gmail.com>
      5ecd3ea1
    • R
      jffs2: compr_rubin: Remove unused function · e4999bbe
      Rickard Strandqvist 提交于
      Remove the function pulledbits() that is not used anywhere.
      
      This was partially found by using a static code analysis program called cppcheck.
      Signed-off-by: NRickard Strandqvist <rickard_strandqvist@spectrumdigital.se>
      Reviewed-by: NRichard Weinberger <richard@nod.at>
      Signed-off-by: NBrian Norris <computersforpeace@gmail.com>
      e4999bbe
  6. 10 1月, 2015 6 次提交
  7. 08 1月, 2015 7 次提交
  8. 23 12月, 2014 3 次提交
  9. 21 12月, 2014 1 次提交