- 03 5月, 2018 1 次提交
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由 Fabio Estevam 提交于
Adopt the SPDX license identifier headers to ease license compliance management. Signed-off-by: NFabio Estevam <fabio.estevam@nxp.com> Signed-off-by: NMark Brown <broonie@kernel.org>
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- 30 12月, 2014 1 次提交
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由 Aurelien BOUIN 提交于
The xDC field should have 5 bit width according to Reference Manual. Thus this patch fixes it. Signed-off-by: NAurelien BOUIN <a_bouin@yahoo.fr> Signed-off-by: NNicolin Chen <nicoleotsuka@gmail.com> Signed-off-by: NMark Brown <broonie@kernel.org> Cc: stable@vger.kernel.org
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- 17 8月, 2014 1 次提交
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由 Shengjiu Wang 提交于
Original driver didn't store the number of slots, just fix the slot number to 2, use this default number to calculate bclk and pins for TX/RX. In this patch, add one parameter for slots, and update the calculation of bclk and pins of TX/RX. Then driver will be compatible with slots > 2 in TDM mode. Signed-off-by: NShengjiu Wang <shengjiu.wang@freescale.com> Acked-by: NNicolin Chen <nicoleotsuka@gmail.com> Signed-off-by: NMark Brown <broonie@linaro.org>
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- 14 8月, 2014 1 次提交
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由 Shengjiu Wang 提交于
Original driver didn't store the number of slots, just fix the slot number to 2, use this default number to calculate bclk and pins for TX/RX. In this patch, add one parameter for slots, and update the calculation of bclk and pins of TX/RX. Then driver will be compatible with slots > 2 in TDM mode. Signed-off-by: NShengjiu Wang <shengjiu.wang@freescale.com> Acked-by: NNicolin Chen <nicoleotsuka@gmail.com> Signed-off-by: NMark Brown <broonie@linaro.org>
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- 10 2月, 2014 1 次提交
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由 Xiubo Li 提交于
Signed-off-by: NXiubo Li <Li.Xiubo@freescale.com> Acked-by: NNicolin Chen <Guangyu.Chen@freescale.com> Signed-off-by: NMark Brown <broonie@linaro.org>
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- 10 1月, 2014 1 次提交
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由 Nicolin Chen 提交于
This patch implements a device-tree-only CPU DAI driver for Freescale ESAI controller that supports: - 12 channels playback and 8 channels record. [ Some of the inner transmitters and receivers are sharing same group of pins. So the maxmium 12 output or 8 input channels are only valid if there is no pin conflict occurring to it. ] - Independent (asynchronous mode) or shared (synchronous mode) transmit and receive sections with separate or shared internal/external clocks and frame syncs, operating in Master or Slave mode. [ Current ALSA seems not to allow CPU DAI drivers to configure DAI format separately for PLAYBACK and CAPTURE. So this first version only supports the case that uses the same DAI format for both directions. ] - Various DAI formats: I2S, Left-Justified, Right-Justified, DSP-A and DSP-B. - Programmable word length (8, 16, 20 or 24bits) - Flexible selection between system clock or external oscillator as input clock source, programmable internal clock divider and frame sync generation. Signed-off-by: NNicolin Chen <Guangyu.Chen@freescale.com> Signed-off-by: NMark Brown <broonie@linaro.org>
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