This adds support for extended ASIDs (up to 16-bits) on newer SH-X3 cores
that implement the PTAEX register and respective functionality. Presently
only the 65nm SH7786 (90nm only supports legacy 8-bit ASIDs).

The main change is in how the PTE is written out when loading the entry
in to the TLB, as well as in how the TLB entry is selectively flushed.

While SH-X2 extended mode splits out the memory-mapped U and I-TLB data
arrays for extra bits, extended ASID mode splits out the address arrays.
While we don't use the memory-mapped data array access, the address
array accesses are necessary for selective TLB flushes, so these are
implemented newly and replace the generic SH-4 implementation.

With this, TLB flushes in switch_mm() are almost non-existent on newer
parts.
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

This provides a method for supporting fixed PMB mappings inherited from
the bootloader, as an alternative to the dynamic PMB mapping currently
used by the kernel. In the future these methods will be combined.

P1/P2 area is handled like a regular 29-bit physical address, and local
bus device are assigned P3 area addresses.
Signed-off-by: NYoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

This converts the sh64 /proc/asids entry to debugfs and enables it for
all SH parts that have debugfs enabled.

On MMU systems this can be used to determine which processes are using
which ASIDs which in turn can be used for finer grained cache tag
analysis.
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

With the PMB enabled, only P1SEG and up are covered by the PMB mappings,
meaning that situations where out-of-bounds physical addresses are read
from will lead to TLB reset after the PMB miss, allowing for use cases
like dd if=/dev/mem to reset the TLB.

Fix this up to make sure the reference is between __MEMORY_START (phys)
and __pa(high_memory). This is coherent across all variants of sh/sh64
with and without MMU, though the PMB bug itself is only applicable to
SH-4A parts.
Reported-by: NHideo Saito <saito@densan.co.jp>
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

Includes:
- SH2 (7619) Writeback support.
- SH2A cache handling fix.
Signed-off-by: NYoshinori Sato <ysato@users.sourceforge.jp>
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

Follow the MIPS and sparc64 changes for -Werror instrumentation.
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

We stopped referencing these functions unconditionally when the
old entry.S code was refactored, so this is just dead code at
present. Kill it off.
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

The cache disabling stuff screwed up some of the sh4 nommu
builds, fix it up again.
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

This reworks the cache mode configuration in Kconfig, and allows for
explicit selection of write-back/write-through/off configurations.
All of the cache flushing routines are optimized away for the off
case.
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

fault-nommu defines the page fault handler stubs for SH-3/4 parts,
but is not needed on SH-2/SH-2A now that the entry code has been
logically separated.

Add it in for SH-3 and SH-4 explicitly.
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

There's no point in keeping these around, they've been broken
for some time, and the dmaenging/async_tx framework provides a
far more reasonable interface.
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

This adds basic support for multiple nodes on SH machines.
This is primarily useful for boards with many different
memory blocks that are otherwise unused (SH7722/SH7785 URAM
and so forth).
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

A simple debugging aid for easier visibility of the respective
cachelines.
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

A few more outstanding nommu fixups..
Signed-off-by: NYoshinori Sato <ysato@users.sourceforge.jp>
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

ioremap() overhaul. Add support for transparent PMB mapping, get rid of
p3_ioremap(), etc. Also drop ioremap() and iounmap() routines from the
machvec, as everyone can use the generic ioremap() API instead. For PCI
memory apertures and other special cases, use the pci_iomap() API, as
boards are already required to get the mapping right there.
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

Cleanup of page table allocators, using generic folded PMD and PUD
helpers. TLB flushing operations are moved to a more sensible spot.

The page fault handler is also optimized slightly, we no longer waste
cycles on IRQ disabling for flushing of the page from the ITLB, since
we're already under CLI protection by the initial exception handler.
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

Add support for 32-bit physical addressing through the SH-4A
Privileged Space Mapping Buffer (PMB).
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

Initial git repository build. I'm not bothering with the full history,
even though we have it. We can create a separate "historical" git
archive of that later if we want to, and in the meantime it's about
3.2GB when imported into git - space that would just make the early
git days unnecessarily complicated, when we don't have a lot of good
infrastructure for it.

Let it rip!