- 02 4月, 2012 1 次提交
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由 Eugeni Dodonov 提交于
This adds PCI ID for IVB GT2 server variant which we were missing. Signed-off-by: NEugeni Dodonov <eugeni.dodonov@intel.com> [danvet: fix up conflict because the patch has been diffed against next. tsk.] Signed-Off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
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- 10 2月, 2012 2 次提交
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由 Daniel Vetter 提交于
We need this because ppgtt page directory entries need to be in the global gtt pagetable. Reviewed-by: NBen Widawsky <ben@bwidawsk.net> Tested-by: NChris Wilson <chris@chris-wilson.co.uk> Tested-by: NEugeni Dodonov <eugeni.dodonov@intel.com> Reviewed-by: NEugeni Dodonov <eugeni.dodonov@intel.com> Signed-Off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
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由 Daniel Vetter 提交于
To implement a PPGTT for drm/i915 that fully aliases the GTT, we also need to properly alias the scratch page. Reviewed-by: NBen Widawsky <ben@bwidawsk.net> Tested-by: NChris Wilson <chris@chris-wilson.co.uk> Tested-by: NEugeni Dodonov <eugeni.dodonov@intel.com> Reviewed-by: NEugeni Dodonov <eugeni.dodonov@intel.com> Signed-Off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
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- 08 11月, 2011 2 次提交
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由 Keith Packard 提交于
Kernels with no iommu support cannot ever need the Ironlake work-around, so never enable it in that case. Might be better to completely remove the work-around from the kernel in this case? Signed-off-by: NKeith Packard <keithp@keithp.com> Reviewed-by: NBen Widawsky <ben@bwidawsk.net>
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由 Dan Carpenter 提交于
The semi-colon is a typo here and it makes the if statement unconditional. Signed-off-by: NDan Carpenter <dan.carpenter@oracle.com> Signed-off-by: NKeith Packard <keithp@keithp.com>
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- 29 10月, 2011 2 次提交
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由 Keith Packard 提交于
Kernels with no iommu support cannot ever need the Ironlake work-around, so never enable it in that case. Might be better to completely remove the work-around from the kernel in this case? Signed-off-by: NKeith Packard <keithp@keithp.com> Reviewed-by: NBen Widawsky <ben@bwidawsk.net>
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由 Dan Carpenter 提交于
The semi-colon is a typo here and it makes the if statement unconditional. Signed-off-by: NDan Carpenter <dan.carpenter@oracle.com> Signed-off-by: NKeith Packard <keithp@keithp.com>
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- 21 10月, 2011 1 次提交
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由 Ben Widawsky 提交于
Idle the GPU before doing any unmaps. We know if VT-d is in use through an exported variable from iommu code. This should avoid a known HW issue. Signed-off-by: NBen Widawsky <ben@bwidawsk.net> Reviewed-by: NDaniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: NKeith Packard <keithp@keithp.com>
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- 21 9月, 2011 1 次提交
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由 Suresh Siddha 提交于
Change the CONFIG_DMAR to CONFIG_INTEL_IOMMU to be consistent with the other IOMMU options. Rename the CONFIG_INTR_REMAP to CONFIG_IRQ_REMAP to match the irq subsystem name. And define the CONFIG_DMAR_TABLE for the common ACPI DMAR routines shared by both CONFIG_INTEL_IOMMU and CONFIG_IRQ_REMAP. Signed-off-by: NSuresh Siddha <suresh.b.siddha@intel.com> Cc: yinghai@kernel.org Cc: youquan.song@intel.com Cc: joerg.roedel@amd.com Cc: tony.luck@intel.com Cc: dwmw2@infradead.org Link: http://lkml.kernel.org/r/20110824001456.558630224@sbsiddha-desk.sc.intel.comSigned-off-by: NIngo Molnar <mingo@elte.hu>
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- 14 5月, 2011 1 次提交
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由 Jesse Barnes 提交于
Just use the Sandy Bridge routines. Signed-off-by: NJesse Barnes <jbarnes@virtuousgeek.org> Reviewed-by: NKeith Packard <keithp@keithp.com> Signed-off-by: NKeith Packard <keithp@keithp.com>
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- 22 2月, 2011 1 次提交
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由 Chris Wilson 提交于
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=27187 Tested-by: Thorsten Vollmer <thorsten@thvo.de> (DFI-ACP G5M150-N w/852GME) Tested-by: Moritz Brunner <2points@gmx.org> (Asus M2400N/i855GM) Tested-by: Indan Zupancic <indan@nul.nu> (Thinkpad X40/855GM rev 02) Tested-by: Eric Anholt <eric@anholt.net> (865G) Signed-off-by: NChris Wilson <chris@chris-wilson.co.uk>
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- 16 2月, 2011 1 次提交
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由 Chris Wilson 提交于
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=27187 Tested-by: Thorsten Vollmer <thorsten@thvo.de> (DFI-ACP G5M150-N w/852GME) Tested-by: Moritz Brunner <2points@gmx.org> (Asus M2400N/i855GM) Tested-by: Indan Zupancic <indan@nul.nu> (Thinkpad X40/855GM rev 02) Tested-by: Eric Anholt <eric@anholt.net> (865G) Signed-off-by: NChris Wilson <chris@chris-wilson.co.uk>
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- 25 1月, 2011 1 次提交
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由 Chris Wilson 提交于
We can only utilize the stolen portion of the GTT if we are in sole charge of the hardware. This is only true if using GEM and KMS, otherwise VESA continues to access stolen memory. Reported-by: NArnd Bergmann <arnd@arndb.de> Reported-by: NFrederic Weisbecker <fweisbec@gmail.com> Tested-by: NJiri Olsa <jolsa@redhat.com> Tested-by: NFrederic Weisbecker <fweisbec@gmail.com> Cc: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: NChris Wilson <chris@chris-wilson.co.uk>
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- 15 1月, 2011 1 次提交
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由 Oswald Buddenhagen 提交于
They got mixed up when the switch was converted to a table in 2007. Signed-off-by: NOswald Buddenhagen <ossi@kde.org> [ickle: minor changes for 2.6.37+] Signed-off-by: NChris Wilson <chris@chris-wilson.co.uk>
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- 12 1月, 2011 3 次提交
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由 Dave Airlie 提交于
Previous to the last GTT rework we always rewrote the GTT then unmapped the object, somehow this got reversed in the rework in 2.6.37-rc5 timeframe. This fix needs to go to stable in an alternate form since the code changed. This fixes DMAR reports on my Ironlake HP2540p. Signed-off-by: NDave Airlie <airlied@redhat.com>
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由 Dave Airlie 提交于
This code was setting up the status page before setting the DMAR-is-on-bit, so we were getting DMAR errors on the status page. Reverse the two bits of init code to the correct result. Signed-off-by: NDave Airlie <airlied@redhat.com>
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由 Chris Wilson 提交于
Flush the chipset write buffers before and after adjusting the GTT base register, just in case. We only modify this value upon initialisation (boot and resume) so there should be no outstanding writes, however there are always those persistent PGTBL_ER that keep getting reported upon resume. Signed-off-by: NChris Wilson <chris@chris-wilson.co.uk>
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- 14 12月, 2010 1 次提交
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由 Chris Wilson 提交于
This fixes regression from a6963596, that missed to set cached memory type in GTT entry. Signed-off-by: NZhenyu Wang <zhenyuw@linux.intel.com> Signed-off-by: NChris Wilson <chris@chris-wilson.co.uk>
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- 05 12月, 2010 1 次提交
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由 Takashi Iwai 提交于
Add a missing NULL check and fix the wrong address passed to kunmap() in i830_cleanup(). Cc: stable@kernel.org Signed-off-by: NTakashi Iwai <tiwai@suse.de> [danvet: added cc stable] Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: NChris Wilson <chris@chris-wilson.co.uk>
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- 24 11月, 2010 10 次提交
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由 Chris Wilson 提交于
drivers/char/agp/intel-gtt.c:340:48: warning: duplicate const Signed-off-by: NChris Wilson <chris@chris-wilson.co.uk>
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由 Daniel Vetter 提交于
Just some minor shuffling to get rid of any agp traces in the exported functions. Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: NChris Wilson <chris@chris-wilson.co.uk>
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由 Daniel Vetter 提交于
The intel drm calls the chipset functions now directly. Userspace never called the corresponding ioctl, hence it can be killed, too. Cc: Dave Airlie <airlied@gmail.com> Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: NChris Wilson <chris@chris-wilson.co.uk>
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由 Daniel Vetter 提交于
Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: NChris Wilson <chris@chris-wilson.co.uk>
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由 Daniel Vetter 提交于
... and a few other defines. Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: NChris Wilson <chris@chris-wilson.co.uk>
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由 Daniel Vetter 提交于
Now the intel-gtt.c rewrite is complete! Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: NChris Wilson <chris@chris-wilson.co.uk>
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由 Daniel Vetter 提交于
Still a separate agp_bridge_driver because of the i81x-only dedicated vram support. Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: NChris Wilson <chris@chris-wilson.co.uk>
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由 Daniel Vetter 提交于
Initialization is still done with the old code with a few added things sprinkled in to make the intel_fake_agp helper functions work. Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: NChris Wilson <chris@chris-wilson.co.uk>
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由 Daniel Vetter 提交于
Used for the now dead agp type_to_mask stuff. Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: NChris Wilson <chris@chris-wilson.co.uk>
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由 Daniel Vetter 提交于
i830_check_flags already disallows it, so no need to implement it in the write_entry function. Seems to be a remnant from i810 support. Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: NChris Wilson <chris@chris-wilson.co.uk>
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- 23 11月, 2010 2 次提交
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由 Chris Wilson 提交于
Signed-off-by: NChris Wilson <chris@chris-wilson.co.uk>
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由 Chris Wilson 提交于
Now that the stolen memory does not also steal entries from the GTT, we can use all the memory the BIOS set aside for the GPU. Signed-off-by: NChris Wilson <chris@chris-wilson.co.uk>
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- 04 11月, 2010 2 次提交
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由 Zhenyu Wang 提交于
This is broken from 97ef1bdd. Let's set the correct bit for LLC+MLC and LLC only. Signed-off-by: NZhenyu Wang <zhenyuw@linux.intel.com> Cc: stable@kernel.org Signed-off-by: NChris Wilson <chris@chris-wilson.co.uk>
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由 Zhenyu Wang 提交于
This restores cache behavior for default AGP_USER_MEMORY as uncached, and leave default AGP_USER_CACHED_MEMORY as LLC only. I've seen different cache behavior on one sandybridge desktop CPU vs. another mobile CPU. Until we figure out how to detect the real cache config, restore back to the original behavior now. Signed-off-by: NZhenyu Wang <zhenyuw@linux.intel.com> Cc: stable@kernel.org Signed-off-by: NChris Wilson <chris@chris-wilson.co.uk>
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- 02 11月, 2010 2 次提交
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由 Zhenyu Wang 提交于
This restores cache behavior for default AGP_USER_MEMORY as uncached, and leave default AGP_USER_CACHED_MEMORY as LLC only. I've seen different cache behavior on one sandybridge desktop CPU vs. another mobile CPU. Until we figure out how to detect the real cache config, restore back to the original behavior now. Signed-off-by: NZhenyu Wang <zhenyuw@linux.intel.com> Signed-off-by: NChris Wilson <chris@chris-wilson.co.uk>
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由 Zhenyu Wang 提交于
This is broken from 97ef1bdd. Let's set the correct bit for LLC+MLC and LLC only. Signed-off-by: NZhenyu Wang <zhenyuw@linux.intel.com> Signed-off-by: NChris Wilson <chris@chris-wilson.co.uk>
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- 31 10月, 2010 1 次提交
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由 Chris Wilson 提交于
... and trying to set the bit is ineffectual. Fixes the regression from e380f60b which detected that we were trying to do undefined operations on the I830_GMCH_CTRL. Reported-by: NAlexey Fisher <bug-track@fisher-privat.net> Signed-off-by: NChris Wilson <chris@chris-wilson.co.uk>
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- 30 10月, 2010 1 次提交
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由 Chris Wilson 提交于
Signed-off-by: NChris Wilson <chris@chris-wilson.co.uk>
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- 28 10月, 2010 2 次提交
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由 Daniel Vetter 提交于
On VT-d supporting platforms the GGTT is allocated in a stolen mem section separate from graphcis stolen mem. The GMCH register contains a bitfield specifying the size of that region. Docs suggest that this region can only be used for GGTT and PPGTT. Hence ensure that the PPGTT is disabled and use the complete area for the GGTT. Unfortunately the graphics core on G33/Pineview can't cope with really large GTTs and the BIOS usually enables the maximum of 512MB. So don't bother with maximizing the GTT on these platforms. Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: NChris Wilson <chris@chris-wilson.co.uk>
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由 Daniel Vetter 提交于
... and switch to a more classical store-reg-on-suspend, restore-on-resume way of doing things. Obviously this is just preparation for the future, the code is not there at all, yet. This is needed because the next patch adjusts this register and everything in it (not just the pagetable address) needs to be restored on resume. Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: NChris Wilson <chris@chris-wilson.co.uk>
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- 22 10月, 2010 1 次提交
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由 Chris Wilson 提交于
In cleaning up the mask functions in bdd30729, the setting of the PTE valid bit was dropped for Sandybridge. Signed-off-by: NChris Wilson <chris@chris-wilson.co.uk>
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