1. 18 12月, 2013 14 次提交
    • B
      drm/i915: Piggy back hangstats off of contexts · c482972a
      Ben Widawsky 提交于
      To simplify the codepaths somewhat, we can simply always create a
      context. Contexts already keep hangstat information. This prevents us
      from having to differentiate at other parts in the code.
      
      There is allocation overhead, but it should not be measurable.
      Signed-off-by: NBen Widawsky <ben@bwidawsk.net>
      Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
      c482972a
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      drm/i915: Create a per file_priv default context · 0eea67eb
      Ben Widawsky 提交于
      Every file will get it's own context, and we use this context instead of
      the default context. The default context still exists for future
      shrinker usage as well as reset handling.
      
      v2: Updated to address Mika's recent context guilty changes
      Some more changes around this come up in later patches as well.
      
      v3: Use a fake context to avoid allocation for the !HAS_HW_CONTEXT case.
      I've tried the alternatives. This looks the best to me.
      Removed hangstat stuff from v2 - for a separate patch
      Demote failed PPGTT set to DRM_DEBUG_DRIVER since it can now be invoked
      easily from userspace.
      Signed-off-by: NBen Widawsky <ben@bwidawsk.net>
      Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
      0eea67eb
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      drm/i915: Do aliasing PPGTT init with contexts · bdf4fd7e
      Ben Widawsky 提交于
      We have a default context which suits the aliasing PPGTT well. Tie them
      together so it looks like any other context/PPGTT pair. This makes the
      code cleaner as it won't have to special case aliasing as often.
      
      The patch has one slightly tricky part in the default context creation
      function. In the future (and on aliased setup) we create a new VM for a
      context (potentially). However, if we have aliasing PPGTT, which occurs
      at this point in time for all platforms GEN6+, we can simply manage the
      refcounting to allow things to behave as normal. Now is a good time to
      recall that the aliasing_ppgtt doesn't have a real VM, it uses the GGTT
      drm_mm.
      Signed-off-by: NBen Widawsky <ben@bwidawsk.net>
      Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
      bdf4fd7e
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      drm/i915: Add VM to context · c7c48dfd
      Ben Widawsky 提交于
      Pretty straightforward so far except for the bit about the refcounting.
      The PPGTT will potentially be shared amongst multiple contexts. Because
      contexts themselves have a refcounted lifecycle, the easiest way to
      manage this will be to refcount the PPGTT. To acheive this, we piggy
      back off of the existing context refcount, and will increment and
      decrement the PPGTT refcount with context creation, and destruction.
      
      To put it more clearly, if context A, and context B both use PPGTT 0, we
      can't free the PPGTT until both A, and B are destroyed.
      
      Note that because the PPGTT is permanently pinned (for now), it really
      just matters for the PPGTT destruction, as opposed to making space under
      memory pressure.
      Signed-off-by: NBen Widawsky <ben@bwidawsk.net>
      Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
      c7c48dfd
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      drm/i915: Reorganize intel_enable_ppgtt · 246cbfb5
      Ben Widawsky 提交于
      This patch consolidates the way in which we handle the various supported
      PPGTT by module parameter in addition to what the hardware supports. It
      strives to make doing the right thing in the code as simple as possible,
      with the USES_ macros.
      
      I've opted to add the full PPGTT argument simply so one can see how I
      intend to use this function. It will not/cannot be used until later.
      Signed-off-by: NBen Widawsky <ben@bwidawsk.net>
      Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
      246cbfb5
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      drm/i915: Extract mm switching to function · eeb9488e
      Ben Widawsky 提交于
      In order to do the full context switch with address space, it's
      convenient to have a way to switch the address space. We already have
      this in our code - just pull it out to be called by the context switch
      code later.
      
      v2: Rebased on BDW support. Required adding BDW.
      Signed-off-by: NBen Widawsky <ben@bwidawsk.net>
      Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
      eeb9488e
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      drm/i915: Use drm_mm for PPGTT PDEs · c8d4c0d6
      Ben Widawsky 提交于
      When PPGTT support was originally enabled, it was only designed to
      support 1 PPGTT. It therefore made sense to simply hide the GGTT space
      required to enable this from the drm_mm allocator.
      
      Since we intend to support full PPGTT, which means more than 1, and they
      can be created and destroyed ad hoc it will be required to use the
      proper allocation techniques we already have.
      
      The first step here is to make the existing single PPGTT use the
      allocator.
      
      The astute observer will notice that we are reserving space in the GGTT
      for the PDEs for the lifetime of the address space, and would be right
      to question whether or not this is a good idea. It does not make a
      difference with this current patch only the aliasing PPGTT (indeed the
      PDEs should still be hidden from the shrinker). For the future, we are
      allocating from top to bottom to avoid using the precious "gtt
      space" The GGTT space at that point should only be used for scanout, HW
      contexts, ringbuffers, HWSP, PDEs, and a couple of other small buffers
      (potentially) used by the kernel. Everything else should be mapped into
      a PPGTT. To put the consumption in more tangible terms, it takes
      approximately 4 sets of PDEs to equal one 19x10 framebuffer (with no
      fancy stride or alignment constraints). 3/4 of the total [average] GGTT
      can be used for PDEs, and hopefully never touch the 1/4 that the
      framebuffer needs.
      
      The astute, and persistent observer might ask about the page tables
      which are also pinned for the address space. This waste is unfortunate.
      We use 2MB of memory per address space. We leave wrapping the PDEs as a
      real GEM object as a TODO.
      
      v2: Align PDEs to 64b in GTT
      Allocate the node dynamically so we can use drm_mm_put_block
      Now tested on IGT
      Allocate node at the top to avoid fragmentation (Chris)
      
      v3: Use Chris' top down allocator
      
      v4: Embed drm_mm_node into ppgtt struct (Jesse)
      Remove hunks which didn't belong (Jesse)
      
      v5: Don't subtract guard page since we now killed the guard page prior
      to this patch. (Ben)
      
      v6: Rebased and removed guard page stuff.
      Added a chunk to the commit message
      Allow adding a context to mappable region
      
      v7: Undo v3, so we can make the drm patch last in the series
      
      Cc: Chris Wilson <chris@chris-wilson.co.uk>
      Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org> (v4)
      Signed-off-by: NBen Widawsky <ben@bwidawsk.net>
      
      squash: drm/i915: allow PPGTT to use mappable
      Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
      c8d4c0d6
    • B
    • B
      drm/i915: Split context enabling from init · 2fa48d8d
      Ben Widawsky 提交于
      We **need** to do this for exactly 1 reason, because we want to embed a
      PPGTT into the context, but we don't want to special case the default
      context.
      
      To achieve that, we must be able to initialize contexts after the GTT is
      setup (so we can allocate and pin the default context's BO), but before
      the PPGTT and rings are initialized. This is because, currently, context
      initialization requires ring usage. We don't have rings until after the
      GTT is setup. If we split the enabling part of context initialization,
      the part requiring the ringbuffer, we can untangle this, and then later
      embed the PPGTT
      
      Incidentally this allows us to also adhere to the original design of
      context init/fini in future patches: they were only ever meant to be
      called at driver load and unload.
      
      v2: Move hw_contexts_disabled test in i915_gem_context_enable() (Chris)
      
      v3: BUG_ON after checking for disabled contexts. Or else it blows up pre
      gen6 (Ben)
      
      v4: Forward port
      Modified enable for each ring, since that patch is earlier in the series
      Dropped ring arg from create_default_context so it can be used by others
      Signed-off-by: NBen Widawsky <ben@bwidawsk.net>
      Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
      2fa48d8d
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      drm/i915: Better reset handling for contexts · acce9ffa
      Ben Widawsky 提交于
      This patch adds to changes for contexts on reset:
      Sets last context to default - this will prevent the context switch
      happening after a reset. That switch is not possible because the
      rings are hung during reset and context switch requires reset. This
      behavior will need to be reworked in the future, but this is what we
      want for now.
      
      In the future, we'll also want to reset the guilty context to
      uninitialized. We should wait for ARB_Robustness related code to land
      for that.
      
      This is somewhat for paranoia.  Because we really don't know what the
      GPU was doing when it hung, or the state it was in (mid context write,
      for example), later restoring the context is a bad idea. By setting the
      flag to not initialized, the next load of that context will not restore
      the state, and thus on the subsequent switch away from the context will
      overwrite the old data.
      
      NOTE: This code needs a fixup when we actually have multiple VMs. The
      issue that can occur is inactive objects in a VM will need to be
      destroyed before the last context unref. This can now happen via the
      fake switch introduced in this patch (and it other ways in the future)
      Signed-off-by: NBen Widawsky <ben@bwidawsk.net>
      Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
      acce9ffa
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      drm/i915: Track which ring a context ran on · 0009e46c
      Ben Widawsky 提交于
      Previously we dropped the association of a context to a ring. It is
      however very important to know which ring a context ran on (we could
      have reused the other member, but I was nitpicky).
      
      This is very important when we switch address spaces, which unlike
      context objects, do change per ring.
      
      As an example, if we have:
      
              RCS   BCS
      ctx            A
      ctx      A
      ctx      B
      ctx            B
      
      Without tracking the last ring B ran on, we wouldn't know to switch the
      address space on BCS in the last row.
      
      As a result, we no longer need to track which ring a context "belongs"
      to, as it never really made much sense anyway.
      Signed-off-by: NBen Widawsky <ben@bwidawsk.net>
      Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
      0009e46c
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      drm/i915: Add a context open function · e422b888
      Ben Widawsky 提交于
      We'll be doing a bit more stuff with each file, so having our own open
      function should make things clean.
      
      This also allows us to easily add conditionals for stuff we don't want
      to do when we don't have HW contexts.
      Signed-off-by: NBen Widawsky <ben@bwidawsk.net>
      Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
      e422b888
    • B
      drm/i915: Create bind/unbind abstraction for VMAs · 6f65e29a
      Ben Widawsky 提交于
      To sum up what goes on here, we abstract the vma binding, similarly to
      the previous object binding. This helps for distinguishing legacy
      binding, versus modern binding. To keep the code churn as minimal as
      possible, I am leaving in insert_entries(). It serves as the per
      platform pte writing basically. bind_vma and insert_entries do share a
      lot of similarities, and I did have designs to combine the two, but as
      mentioned already... too much churn in an already massive patchset.
      
      What follows are the 3 commits which existed discretely in the original
      submissions. Upon rebasing on Broadwell support, it became clear that
      separation was not good, and only made for more error prone code. Below
      are the 3 commit messages with all their history.
      
      drm/i915: Add bind/unbind object functions to VMA
      drm/i915: Use the new vm [un]bind functions
      drm/i915: reduce vm->insert_entries() usage
      
      drm/i915: Add bind/unbind object functions to VMA
      
      As we plumb the code with more VM information, it has become more
      obvious that the easiest way to deal with bind and unbind is to simply
      put the function pointers in the vm, and let those choose the correct
      way to handle the page table updates. This change allows many places in
      the code to simply be vm->bind, and not have to worry about
      distinguishing PPGTT vs GGTT.
      
      Notice that this patch has no impact on functionality. I've decided to
      save the actual change until the next patch because I think it's easier
      to review that way. I'm happy to squash the two, or let Daniel do it on
      merge.
      
      v2:
      Make ggtt handle the quirky aliasing ppgtt
      Add flags to bind object to support above
      Don't ever call bind/unbind directly for PPGTT until we have real, full
      PPGTT (use NULLs to assert this)
      Make sure we rebind the ggtt if there already is a ggtt binding.  This
      happens on set cache levels.
      Use VMA for bind/unbind (Daniel, Ben)
      
      v3: Reorganize ggtt_vma_bind to be more concise and easier to read
      (Ville). Change logic in unbind to only unbind ggtt when there is a
      global mapping, and to remove a redundant check if the aliasing ppgtt
      exists.
      
      v4: Make the bind function a bit smarter about the cache levels to avoid
      unnecessary multiple remaps. "I accept it is a wart, I think unifying
      the pin_vma / bind_vma could be unified later" (Chris)
      Removed the git notes, and put version info here. (Daniel)
      
      v5: Update the comment to not suck (Chris)
      
      v6:
      Move bind/unbind to the VMA. It makes more sense in the VMA structure
      (always has, but I was previously lazy). With this change, it will allow
      us to keep a distinct insert_entries.
      Reviewed-by: NChris Wilson <chris@chris-wilson.co.uk>
      Signed-off-by: NBen Widawsky <ben@bwidawsk.net>
      
      drm/i915: Use the new vm [un]bind functions
      
      Building on the last patch which created the new function pointers in
      the VM for bind/unbind, here we actually put those new function pointers
      to use.
      
      Split out as a separate patch to aid in review. I'm fine with squashing
      into the previous patch if people request it.
      
      v2: Updated to address the smart ggtt which can do aliasing as needed
      Make sure we bind to global gtt when mappable and fenceable. I thought
      we could get away without this initialy, but we cannot.
      
      v3: Make the global GTT binding explicitly use the ggtt VM for
      bind_vma(). While at it, use the new ggtt_vma helper (Chris)
      
      At this point the original mailing list thread diverges. ie.
      
      v4^:
      use target_obj instead of obj for gen6 relocate_entry
      vma->bind_vma() can be called safely during pin. So simply do that
      instead of the complicated conditionals.
      Don't restore PPGTT bound objects on resume path
      Bug fix in resume path for globally bound Bos
      Properly handle secure dispatch
      Rebased on vma bind/unbind conversion
      Signed-off-by: NBen Widawsky <ben@bwidawsk.net>
      
      drm/i915: reduce vm->insert_entries() usage
      
      FKA: drm/i915: eliminate vm->insert_entries()
      
      With bind/unbind function pointers in place, we no longer need
      insert_entries. We could, and want, to remove clear_range, however it's
      not totally easy at this point. Since it's used in a couple of place
      still that don't only deal in objects: setup, ppgtt init, and restore
      gtt mappings.
      
      v2: Don't actually remove insert_entries, just limit its usage. It will
      be useful when we introduce gen8. It will always be called from the vma
      bind/unbind.
      
      Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> (v1)
      Signed-off-by: NBen Widawsky <ben@bwidawsk.net>
      Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
      6f65e29a
    • B
      drm/i915: Make pin count per VMA · d7f46fc4
      Ben Widawsky 提交于
      Signed-off-by: NBen Widawsky <ben@bwidawsk.net>
      Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
      d7f46fc4
  2. 28 11月, 2013 3 次提交
  3. 27 11月, 2013 5 次提交
  4. 19 11月, 2013 2 次提交
  5. 14 11月, 2013 4 次提交
  6. 13 11月, 2013 2 次提交
  7. 12 11月, 2013 2 次提交
    • M
      drm/i915: add i915_get_reset_stats_ioctl · b6359918
      Mika Kuoppala 提交于
      This ioctl returns reset stats for specified context.
      
      The struct returned contains context loss counters.
      
      reset_count:    all resets across all contexts
      batch_active:   active batches lost on resets
      batch_pending:  pending batches lost on resets
      
      v2: get rid of state tracking completely and deliver only counts. Idea
          from Chris Wilson.
      
      v3: fix commit message
      
      v4: default context handled inside i915_gem_context_get_hang_stats
      
      v5: reset_count only for priviledged process
      
      v6: ctx=0 needs CAP_SYS_ADMIN for batch_* counters (Chris Wilson)
      
      v7: context hang stats never returns NULL
      
      v8: rebased on top of reworked context hang stats
          DRM_RENDER_ALLOW for ioctl
      
      v9: use DEFAULT_CONTEXT_ID. Improve comments for ioctl struct members
      Signed-off-by: NMika Kuoppala <mika.kuoppala@intel.com>
      Cc: Ian Romanick <idr@freedesktop.org>
      Cc: Chris Wilson <chris@chris-wilson.co.uk>
      Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
      Reviewed-by: NDamien Lespiau <damien.lespiau@intel.com>
      Reviewed-by: NIan Romanick <ian.d.romanick@intel.com>
      Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
      b6359918
    • M
      drm/i915: add i915_reset_count · 2ac0f450
      Mika Kuoppala 提交于
      reset_counter will be incremented twice per successful
      reset. Odd values mean reset is in progress and even values
      mean that reset has completed.
      
      Reset status ioctl introduced in following commit
      needs to deliver global reset count to userspace so
      use reset_counter to derive the actual reset count
      for the gpu
      
      Note that reset in progress is enough to increment
      the counter.
      
      v2: wedged equals reset in progress (Daniel Vetter)
      
      v3: Fixed stale comments (Damien Lespiau)
      Signed-off-by: NMika Kuoppala <mika.kuoppala@intel.com>
      Reviewed-by: NDamien Lespiau <damien.lespiau@intel.com>
      Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
      2ac0f450
  8. 11 11月, 2013 1 次提交
  9. 09 11月, 2013 6 次提交
    • B
      drm/i915/bdw: Support eDP PSR · ed8546ac
      Ben Widawsky 提交于
      Broadwell PSR support is a superset of Haswell. With this simple
      register base calculation, everything that worked on HSW for eDP PSR
      should work on BDW.
      
      Note that Broadwell provides additional PSR support. This is not
      addressed at this time.
      
      v2: Make the HAS_PSR include BDW
      
      v3: Use the correct offset (I had incorrectly used one from my faulty
      brain) (Art!)
      
      v4: It helps if you git add
      
      v5: Be explicit about not setting min link entry time for BDW. This
      should be no functional change over v4 (Jani)
      Reviewed-by: NArt Runyan <arthur.j.runyan@intel.com>
      Reviewed-by: NJani Nikula <jani.nikula@intel.com>
      Signed-off-by: NBen Widawsky <ben@bwidawsk.net>
      Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
      ed8546ac
    • B
      drm/i915/bdw: Use The GT mailbox for IPS enable/disable · 2a114cc1
      Ben Widawsky 提交于
      v2: Squash in fixup from Ben to synchronize the GT mailbox commands.
      
      CC: Art Runyan <arthur.j.runyan@intel.com>
      Reviewed-by: NArt Runyan <arthur.j.runyan@intel.com>
      Signed-off-by: NBen Widawsky <ben@bwidawsk.net>
      Reviewed-by: NJani Nikula <jani.nikula@intel.com>
      Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
      2a114cc1
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      drm/i915/bdw: Broadwell also has the "power down well" · 6745a2ce
      Paulo Zanoni 提交于
      Just like Haswell, but with the small twist that the panel fitter for pipe A is
      now also in the always-on power well.
      
      v2: Use the new HAS_POWER_WELL macro.
      
      v3: Rebase on top of intel_using_power_well patches.
      
      v4: This time actually update the PFIT check correctly so that the
      pipe A pfit is in the always-on domain.
      
      v5: Rebase on top of the VGA power domain addition.
      
      v6: Rebase on top of the new power domain infrastructure. Also pimp the commit
      message a bit while at it.
      
      v7: Use IS_BROADWELL instead of IS_GEN8 (Ville).
      
      Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> (v1)
      Reviewed-by: NVille Syrjälä <ville.syrjala@linux.intel.com>
      Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
      6745a2ce
    • P
      drm/i915/bdw: add IS_BROADWELL macro · 4e8058a2
      Paulo Zanoni 提交于
      For now it's just equivalent to IS_GEN8, but in the future we might
      want to change that (e.g., on Gen 7 we have IS_VALLEYVIEW,
      IS_IVYBRIDGE and IS_HASWELL).
      Signed-off-by: NPaulo Zanoni <paulo.r.zanoni@intel.com>
      Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
      4e8058a2
    • B
      drm/i915/bdw: PPGTT init & cleanup · 37aca44a
      Ben Widawsky 提交于
      Aside from the potential size increase of the PPGTT, the primary
      difference from previous hardware is the Page Directories are no longer
      carved out of the Global GTT.
      
      Note that the PDE allocation is done as a 8MB contiguous allocation,
      this needs to be eventually fixed (since driver reloading will be a
      pain otherwise). Also, this will be a no-go for real PPGTT support.
      
      v2: Move vtable initialization
      
      v3: Resolve conflicts due to patch series reordering.
      
      v4: Rebase on top of the address space refactoring of the PPGTT
      support. Drop Imre's r-b tag for v2, too outdated by now.
      
      v5: Free the correct amount of memory, "get_order takes size not a page
      count." (Imre)
      Signed-off-by: NBen Widawsky <ben@bwidawsk.net>
      Reviewed-by: NImre Deak <imre.deak@intel.com>
      Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
      37aca44a
    • B
      drm/i915/bdw: Implement interrupt changes · abd58f01
      Ben Widawsky 提交于
      The interrupt handling implementation remains the same as previous
      generations with the 4 types of registers, status, identity, mask, and
      enable. However the layout of where the bits go have changed entirely.
      To address these changes, all of the interrupt vfuncs needed special
      gen8 code.
      
      The way it works is there is a top level status register now which
      informs the interrupt service routine which unit caused the interrupt,
      and therefore which interrupt registers to read to process the
      interrupt. For display the division is quite logical, a set of interrupt
      registers for each pipe, and in addition to those, a set each for "misc"
      and port.
      
      For GT the things get a bit hairy, as seen by the code. Each of the GT
      units has it's own bits defined. They all look *very similar* and
      resides in 16 bits of a GT register. As an example, RCS and BCS share
      register 0. To compact the code a bit, at a slight expense to
      complexity, this is exactly how the code works as well. 2 structures are
      added to the ring buffer so that our ring buffer interrupt handling code
      knows which ring shares the interrupt registers, and a shift value (ie.
      the top or bottom 16 bits of the register).
      
      The above allows us to kept the interrupt register caching scheme, the
      per interrupt enables, and the code to mask and unmask interrupts
      relatively clean (again at the cost of some more complexity).
      
      Most of the GT units mentioned above are command streamers, and so the
      symmetry should work quite well for even the yet to be implemented rings
      which Broadwell adds.
      
      v2: Fixes up a couple of bugs, and is more verbose about errors in the
      Broadwell interrupt handler.
      
      v3: fix DE_MISC IER offset
      
      v4: Simplify interrupts:
      I totally misread the docs the first time I implemented interrupts, and
      so this should greatly simplify the mess. Unlike GEN6, we never touch
      the regular mask registers in irq_get/put.
      
      v5: Rebased on to of recent pch hotplug setup changes.
      
      v6: Fixup on top of moving num_pipes to intel_info.
      
      v7: Rebased on top of Egbert Eich's hpd irq handling rework. Also
      wired up ibx_hpd_irq_setup for gen8.
      
      v8: Rebase on top of Jani's asle handling rework.
      
      v9: Rebase on top of Ben's VECS enabling for Haswell, where he
      unfortunately went OCD on the gt irq #defines. Not that they're still
      not yet fully consistent:
      - Used the GT_RENDER_ #defines + bdw shifts.
      - Dropped the shift from the L3_PARITY stuff, seemed clearer.
      - s/irq_refcount/irq_refcount.gt/
      
      v10: Squash in VECS enabling patches and the gen8_gt_irq_handler
      refactoring from Zhao Yakui <yakui.zhao@intel.com>
      
      v11: Rebase on top of the interrupt cleanups in upstream.
      
      v12: Rebase on top of Ben's DPF changes in upstream.
      
      v13: Drop bdw from the HAS_L3_DPF feature flag for now, it's unclear what
      exactly needs to be done. Requested by Ben.
      
      v14: Fix the patch.
      - Drop the mask of reserved bits and assorted logic, it doesn't match
        the spec.
      - Do the posting read inconditionally instead of commenting it out.
      - Add a GEN8_MASTER_IRQ_CONTROL definition and use it.
      - Fix up the GEN8_PIPE interrupt defines and give the GEN8_ prefixes -
        we actually will need to use them.
      - Enclose macros in do {} while (0) (checkpatch).
      - Clear DE_MISC interrupt bits only after having processed them.
      - Fix whitespace fail (checkpatch).
      - Fix overtly long lines where appropriate (checkpatch).
      - Don't use typedef'ed private_t (maintainer-scripts).
      - Align the function parameter list correctly.
      
      Signed-off-by: Ben Widawsky <ben@bwidawsk.net> (v4)
      Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
      
      bikeshed
      abd58f01
  10. 07 11月, 2013 1 次提交
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