- 28 3月, 2013 1 次提交
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由 Haojian Zhuang 提交于
pinctrl-pxa driver doesn't support well on DT mode. Now pinctrl-single could support DT mode & pin configuration. Use pinctrl-single driver to support MMP/PXA silicons instead. Signed-off-by: NHaojian Zhuang <haojian.zhuang@linaro.org> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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- 05 2月, 2013 4 次提交
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由 Kukjin Kim 提交于
Since pinctrl-exynos can support exynos4 and exynos5 so changed the option name to PINCTRL_EXYNOS for more clarity. Cc: Thomas Abraham <Thomas.abraham@linaro.org> Cc: Linus Walleij <linus.walleij@linaro.org> Cc: Grant Likely <grant.likely@secretlab.ca> Signed-off-by: NKukjin Kim <kgene.kim@samsung.com> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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由 Patrice Chotard 提交于
Add AB8540 sub driver to the ABx500 family, pins, pin groups and gpio range. As the pin controller (also the ABx500 controllers) is an inherent part of the SoC and will prevent boot if not available, select this from the Ux500 SoC Kconfig. Acked-by: NOlof Johansson <olof@lixom.net> Signed-off-by: NPatrice Chotard <patrice.chotard@stericsson.com> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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由 Patrice Chotard 提交于
Add AB9540 sub driver to the ABx500 family, pins, pin groups and gpio range. As the pin controller (also the ABx500 controllers) is an inherent part of the SoC and will prevent boot if not available, select this from the Ux500 SoC Kconfig. Acked-by: NOlof Johansson <olof@lixom.net> Signed-off-by: NPatrice Chotard <patrice.chotard@stericsson.com> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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由 Patrice Chotard 提交于
Add AB8505 sub driver to the ABx5x family. As the pin controller (also the ABx500 controllers) is an inherent part of the SoC and will prevent boot if not available, select this from the Ux500 SoC Kconfig. Acked-by: NOlof Johansson <olof@lixom.net> Signed-off-by: NPatrice Chotard <patrice.chotard@stericsson.com> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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- 31 1月, 2013 2 次提交
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由 Patrice Chotard 提交于
This adds a subdriver for the AB8500 pinctrl portions. As the pin controller (also the ABx500 controllers) is an inherent part of the SoC and will prevent boot if not available, select this from the Ux500 SoC Kconfig. Acked-by: NOlof Johansson <olof@lixom.net> Reviewed-by: NStephen Warren <swarren@nvidia.com> Signed-off-by: NPatrice Chotard <patrice.chotard@st.com> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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由 Patrice Chotard 提交于
This adds the AB8500 core driver, which will be utilized by the follow-on drivers for different ABx500 variants. Sselect the driver from the DBX500_SOC, as this chip is powering and clocking that SoC. Cc: Samuel Ortiz <sameo@linux.intel.com> Signed-off-by: NPatrice Chotard <patrice.chotard@st.com> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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- 25 1月, 2013 1 次提交
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由 Laurent Pinchart 提交于
Signed-off-by: NLaurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Acked-by: NPaul Mundt <lethal@linux-sh.org> Acked-by: NLinus Walleij <linus.walleij@linaro.org> Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>
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- 22 1月, 2013 1 次提交
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由 Maxime Ripard 提交于
The Allwinner SoCs have an IP module that handle both the muxing and the GPIOs. This IP has 8 banks of 32 bits, with a number of pins actually useful for each of these banks varying from one to another, and depending on the SoC used on the board. This driver only implements the pinctrl part, the gpio part will come eventually. Acked-by: NArnd Bergmann <arnd@arndb.de> Acked-by: NOlof Johansson <olof@lixom.net> Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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- 19 1月, 2013 1 次提交
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由 Kukjin Kim 提交于
Since pinctrl-exynos can support exynos4 and exynos5 so changed the option name to PINCTRL_EXYNOS for more clarity. Cc: Thomas Abraham <Thomas.abraham@linaro.org> Cc: Linus Walleij <linus.walleij@linaro.org> Cc: Grant Likely <grant.likely@secretlab.ca> Signed-off-by: NKukjin Kim <kgene.kim@samsung.com> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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- 18 1月, 2013 1 次提交
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由 Pritesh Raithatha 提交于
This adds a driver for the Tegra114 pinmux, and required parameterization data for Tegra114. The driver uses the common Tegra pincontrol driver utility functions to implement the majority of the driver. This driver is not compatible with the earlier NVIDIA's SoCs, hence add new compatibile as "nvidia,tegra114-pinmux". Originally written by Pritesh. ldewangan: - cleanup the patches, - remove non-require tables. - Use module_platform_driver() for driver registartion. Signed-off-by: NPritesh Raithatha <praithatha@nvidia.com> Signed-off-by: NLaxman Dewangan <ldewangan@nvidia.com> Reviewed-by: NStephen Warren <swarren@nvidia.com> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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- 22 11月, 2012 1 次提交
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由 Thomas Abraham 提交于
Add a new pinctrl driver for Samsung EXYNOS5440 SoC. The pin controller module in EXYNOS5440 is different from the pin controller found on other Samsung SoC. Hence, the pin controller driver for EXYNOS5440 SoC is independent of the Samsung pinctrl framework. Signed-off-by: NThomas Abraham <thomas.abraham@linaro.org> Acked-by: NLinus Walleij <linus.walleij@linaro.org> Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>
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- 12 11月, 2012 1 次提交
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由 Thomas Petazzoni 提交于
Like the spear platform, the mvebu platform has multiple files: one core file, and then one file per SoC family. More files will be added later, as support for mach-orion5x and mach-mv78xx0 SoCs is added to pinctrl-mvebu. For those reasons, having a separate subdirectory, drivers/pinctrl/mvebu/ makes sense, and it had already been suggested by Linus Wallej when the driver was originally submitted. Signed-off-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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- 13 10月, 2012 1 次提交
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This is also include the gpio controller as the IP share both. Each soc will have to describe the SoC limitation and pin configuration via DT. This will allow to do not need to touch the C code when adding new SoC if the IP version is supported. Signed-off-by: NJean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
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- 01 10月, 2012 1 次提交
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由 Simon Arlott 提交于
The BCM2835 GPIO module is a combined GPIO controller, (GPIO) interrupt controller, and pinmux/control device. Original driver by Simon Arlott. Rewrite including GPIO chip device by Chris Boot. Upstreaming changes by Stephen Warren: * Wrote DT binding documentation. * Changed brcm,function to an integer to more directly match the datasheet, and to match brcm,pins being an integer. * Implemented pull-up/down pin config. * Removed read-only DT property and related code. The restriction this implemented are driven by the board, not the GPIO HW block, so don't really make sense of a HW block binding, were in general incomplete (since they could only know about the few pins hard-coded into the Raspberry Pi B board design and not the uncommitted GPIOS), and are better represented simply by not writing incorrect data into pin configuration nodes. * Don't set GPIO_IN function select in gpio_request_enable() to avoid glitches; defer this to gpio_set_direction(). Consequently, removed empty bcm2835_pmx_gpio_request_enable(). * Simplified enabled_irq_map[]; make it explicitly 1 entry per bank. * Lifted use of enabled_irq_map[] outside the per-interrupt loop in IRQ handler, thus fixing an issue where the code was indexing into enabled_irq_map[] by intra-bank GPIO ID, not global GPIO ID. * Removed locking in IRQ handler, since all other code uses spin_lock_irqsave() and so guarantees it doesn't run concurrently with the handler. * Moved duplicated BUILD_BUG_ON()s into probe(). Also check size of bcm2835_gpio_pins[]. * Remove range-checking from bcm2835_pctl_get_groups_count() since we've decided to trust the pinctrl core. * Made bcm2835_pmx_gpio_disable_free() call bcm2835_pinctrl_fsel_set() directly for simplicity. * Fixed body of dt_free_map() to match latest dt_node_to_map(). * Removed GPIO ownership check from bcm2835_pmx_enable() since the pinctrl core owns doing this. * Made irq_chip and pinctrl_gpio_range .name == MODULE_NAME so it's more descriptive. * Simplified remove(); removed call to non-existent pinctrl_remove_gpio_range(), remove early return on error. * Don't force gpiochip's base to 0. Set gpio_range.base to gpiochip's base GPIO number. * Error-handling cleanups in probe(). * Switched to module_platform_driver() rather than open-coding. * Made pin, group, and function names lower-case. * s/broadcom/brcm/ in DT property names. * s/2708/2835/. * Fixed a couple minor checkpatch warnings, and other minor cleanup. Signed-off-by: NSimon Arlott <simon@fire.lp0.eu> Signed-off-by: NChris Boot <bootc@bootc.net> Signed-off-by: NStephen Warren <swarren@wwwdotorg.org> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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- 22 9月, 2012 5 次提交
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由 Thomas Petazzoni 提交于
This pinctrl driver is not a full-blown pinctrl driver from scratch: it relies on the common pinctrl-mvebu driver, which is used for all Marvell EBU SoCs. Signed-off-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com> Acked-by: NLinus Walleij <linus.walleij@linaro.org> Acked-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com> Tested-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com> Reviewed-by: NStephen Warren <swarren@wwwdotorg.org> Signed-off-by: NJason Cooper <jason@lakedaemon.net>
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由 Thomas Petazzoni 提交于
This pinctrl driver is not a full-blown pinctrl driver from scratch: it relies on the common pinctrl-mvebu driver, which is used for all Marvell EBU SoCs. Signed-off-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com> Acked-by: NLinus Walleij <linus.walleij@linaro.org> Acked-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com> Tested-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com> Reviewed-by: NStephen Warren <swarren@wwwdotorg.org> Signed-off-by: NJason Cooper <jason@lakedaemon.net>
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由 Sebastian Hesselbarth 提交于
This patch adds a SoC specific pinctrl driver for Marvell Kirkwood SoCs plus DT binding documentation. This driver will use the mvebu pinctrl driver core. Signed-off-by: NSebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Acked-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com> Tested-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com> Reviewed-by: NStephen Warren <swarren@wwwdotorg.org> Tested-by: NAndrew Lunn <andrew@lunn.ch> Signed-off-by: NJason Cooper <jason@lakedaemon.net>
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由 Sebastian Hesselbarth 提交于
This patch adds a SoC specific pinctrl driver for Marvell Dove SoCs plus DT binding documentation. This driver will use the mvebu pinctrl driver core. Signed-off-by: NSebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Acked-by: NLinus Walleij <linus.walleij@linaro.org> Acked-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com> Tested-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com> Reviewed-by: NStephen Warren <swarren@wwwdotorg.org> Signed-off-by: NJason Cooper <jason@lakedaemon.net>
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由 Sebastian Hesselbarth 提交于
This patch adds a pinctrl driver core for Marvell SoCs plus DT binding documentation. This core driver will be used by SoC family specific drivers, i.e. Armada XP, Armada 370, Dove, Kirkwood, aso. Signed-off-by: NSebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Signed-off-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com> Acked-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com> Tested-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com> Reviewed-by: NStephen Warren <swarren@wwwdotorg.org> Signed-off-by: NJason Cooper <jason@lakedaemon.net> Conflicts: arch/arm/Kconfig
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- 13 9月, 2012 2 次提交
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由 John Crispin 提交于
Implement support for pinctrl on lantiq/falcon socs. The FALCON has 5 banks of up to 32 pins. Signed-off-by: NJohn Crispin <blogic@openwrt.org> Signed-off-by: NThomas Langer <thomas.langer@lantiq.com> Acked-by: NLinus Walleij <linus.walleij@linaro.org> Cc: devicetree-discuss@lists.ozlabs.org Cc: linux-kernel@vger.kernel.org
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由 John Crispin 提交于
Implement support for pinctrl on lantiq/xway socs. The IO core found on these socs has the registers for pinctrl, pinconf and gpio mixed up in the same register range. As the gpio_chip handling is only a few lines, the driver also implements the gpio functionality. This obseletes the old gpio driver that was located in the arch/ folder. Signed-off-by: NJohn Crispin <blogic@openwrt.org> Acked-by: NLinus Walleij <linus.walleij@linaro.org> Cc: devicetree-discuss@lists.ozlabs.org Cc: linux-kernel@vger.kernel.org
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- 07 9月, 2012 2 次提交
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由 Thomas Abraham 提交于
Add information about the Exynos4210 pin banks and driver data which is used by the Samsung pinctrl driver. In addition to this, the support for external gpio and wakeup interrupt support is included and hooked up with the Samsung pinctrl driver. Signed-off-by: NThomas Abraham <thomas.abraham@linaro.org> Reviewed-by: NLinus Walleij <linus.walleij@linaro.org> Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>
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由 Thomas Abraham 提交于
Add a new device tree enabled pinctrl and gpiolib driver for Samsung SoC's. This driver provides a common and extensible framework for all Samsung SoC's to interface with the pinctrl and gpiolib subsystems. This driver supports only device tree based instantiation and hence can be used only on those Samsung platforms that have device tree enabled. This driver is split into two parts: the pinctrl interface and the gpiolib interface. The pinctrl interface registers pinctrl devices with the pinctrl subsystem and gpiolib interface registers gpio chips with the gpiolib subsystem. The information about the pins, pin groups, pin functions and gpio chips, which are SoC specific, are parsed from device tree node. Signed-off-by: NThomas Abraham <thomas.abraham@linaro.org> Reviewed-by: NLinus Walleij <linus.walleij@linaro.org> Acked-by: NStephen Warren <swarren@nvidia.com> Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>
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- 03 9月, 2012 3 次提交
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由 Uwe Kleine-König 提交于
This is mostly cut'n'paste from the imx51 pinctrl driver. The data was generated using sed and awk on arch/arm/plat-mxc/include/mach/iomux-mx35.h. Changes since (implicit) v1 - remove references to file names in binding documentation - remove sed commands from comments in driver - add explicit numbers for pins and functions Acked-by: NShawn Guo <shawn.guo@linaro.org> Acked-by: NStephen Warren <swarren@wwwdotorg.org> Acked-by: NDong Aisheng <dong.aisheng@linaro.org> Signed-off-by: NUwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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由 Linus Walleij 提交于
This adds support for the STN8815 ASIC for the Nomadik pin controller. Acked-by: NStephen Warren <swarren@wwwdotorg.org> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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由 Patrice Chotard 提交于
This implements a subdriver for the DB8540 ASIC for the Nomadik pin controller. Signed-off-by: NPatrice Chotard <patrice.chotard@stericsson.com> Reviewed-by: NStephen Warren <swarren@wwwdotorg.org> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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- 15 7月, 2012 1 次提交
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由 Tony Lindgren 提交于
Add one-register-per-pin type device tree based pinctrl driver. This driver has been tested on omap2+ series of processors, where there is either an 8 or 16-bit padconf register for each pin. Support for other similar pinmux controllers can be added. Signed-off-by: NTony Lindgren <tony@atomide.com> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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- 21 5月, 2012 2 次提交
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由 Dong Aisheng 提交于
ChangeLog v1->v2: * change PIN_FUNC_ID base in binding doc to 0 from 1. Acked-by: NShawn Guo <shawn.guo@linaro.org> Acked-by: NStephen Warren <swarren@wwwdotorg.org> Signed-off-by: NDong Aisheng <dong.aisheng@linaro.org> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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由 Dong Aisheng 提交于
ChangeLog v1->v2: * change PIN_FUNC_ID base in binding doc to 0 from 1. Acked-by: NShawn Guo <shawn.guo@linaro.org> Acked-by: NStephen Warren <swarren@wwwdotorg.org> Signed-off-by: NDong Aisheng <dong.aisheng@linaro.org> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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- 11 5月, 2012 2 次提交
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由 Linus Walleij 提交于
This adds a scratch pin control interface to the Nomadik pinctrl driver, and defines the pins and groups in the DB8500 ASIC. We define GPIO ranges to cover the pins exposed. The DB8500 has more pins than this but we restrict the driver to the pins that can be controlled from the combined GPIO and pin control hardware to begin with. ChangeLog v1->v2: - Base on the latest pinctrl development from pinctrl-mergebase-20120418 so we can get rid of legacy group count mechanism. Also drop the range checks for group index, this is handled by the core now. Acked-by: NStephen Warren <swarren@wwwdotorg.org> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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由 Linus Walleij 提交于
I'm moving this driver over to the pinctrl subsystem to convert the custom pin mux/config scheme over to use pinctrl. Acked-by: NStephen Warren <swarren@wwwdotorg.org> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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- 02 5月, 2012 3 次提交
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由 Shawn Guo 提交于
Add pinctrl support for Freescale MXS SoCs, i.MX23 and i.MX28. The driver supports device tree probe only. Signed-off-by: NShawn Guo <shawn.guo@linaro.org> Acked-by: NStephen Warren <swarren@wwwdotorg.org> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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由 Dong Aisheng 提交于
Acked-by: NStephen Warren <swarren@wwwdotorg.org> Acked-by: NShawn Guo <shawn.guo@linaro.org> Signed-off-by: NDong Aisheng <dong.aisheng@linaro.org> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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由 Dong Aisheng 提交于
The driver has mux and config support while the gpio is still not supported. For select input setting, the driver will handle it internally and do not need user to take care of it. The pinctrl-imx core driver will parse the dts file and dynamically create the pinmux functions and groups. Each IMX SoC pinctrl driver should register pins with a pin register map including mux register and config register and select input map to core for proper operations. Acked-by: NStephen Warren <swarren@wwwdotorg.org> Acked-by: NShawn Guo <shawn.guo@linaro.org> Signed-off-by: NDong Aisheng <dong.aisheng@linaro.org> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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- 23 4月, 2012 1 次提交
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由 Viresh Kumar 提交于
This adds pinctrl driver for SPEAr platform. It also updates MAINTAINERS file for SPEAr pinctrl drivers. Signed-off-by: NViresh Kumar <viresh.kumar@st.com> Acked-by: NLinus Walleij <linus.walleij@linaro.org> Reviewed-by: NStephen Warren <swarren@wwwdotorg.org>
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- 18 4月, 2012 2 次提交
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由 Stephen Warren 提交于
pinctrl/devicetree.c won't compile when !CONFIG_PINCTRL, since the pinctrl headers don't declare some types when !PINCTRL. Make sure pinctrl/Makefile only attempts to compile devicetree.c when OF && PINCTRL. Acked-by: NDong Aisheng <dong.aisheng@linaro.org> Signed-off-by: NStephen Warren <swarren@nvidia.com> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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由 Stephen Warren 提交于
During pinctrl_get(), if the client device has a device tree node, look for the common pinctrl properties there. If found, parse the referenced device tree nodes, with the help of the pinctrl drivers, and generate mapping table entries from them. During pinctrl_put(), free any results of device tree parsing. Acked-by: NDong Aisheng <dong.aisheng@linaro.org> Signed-off-by: NStephen Warren <swarren@wwwdotorg.org> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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- 13 3月, 2012 1 次提交
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由 Linus Walleij 提交于
This is a split-off from the earlier patch set which adds generic pin configuration for the pin controllers that want it. Since we may have a system with mixed generic and custom pin controllers, we pass a boolean in the pin controller ops vtable to indicate if it is generic. ChangeLog v1->v5: - Follow parent patch versioning number system. - Document the semantic meaning of return values from pin config get functions, so we can iterate over pins and check their properties from debugfs as part of the generic config code. - Use proper cast functions in the generic debugfs pin config file. - Expand generic config to optionally cover groups too. ChangeLog v5->v6: - Update to match underlying changes. ChangeLog v6->v7: - Drop DRIVE_OFF parameter, use bias high impedance for this - Delete argument for drive modes push-pull, od and os. These are now just state transitions. - Delete slew rate rising/falling due to discussions on on proper semantics - Drop config wakeup, struct irq_chip does this for now, add back if need be. - Set PIN_CONFIG_END to 0x7fff making room for custom config parameters from 0x8000 and up. - Prefix accessor functions with pinconf_
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- 06 3月, 2012 1 次提交
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由 Stephen Warren 提交于
This adds a driver for the Tegra pinmux, and required parameterization data for Tegra20 and Tegra30. The driver is initially added with driver name and device tree compatible value that won't cause this driver to be used. A later change will switch the pinctrl driver to use the correct values, switch the old pinmux driver to be disabled, and update all code that uses the old pinmux APIs to use the new pinctrl APIs. Signed-off-by: NStephen Warren <swarren@nvidia.com> Acked-by: NOlof Johansson <olof@lixom.net> [squashed "fix case of Tegra30's foo_groups[] arrays"] Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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