Signed-off-by: NMike Frysinger <vapier@gentoo.org>

Signed-off-by: NMike Frysinger <vapier@gentoo.org>

When CoreB wakes up, it needs to read variables that CoreA might have
modified, and might be in CoreB's cache.  So kill CoreB's cache before
going to sleep so that when we wake up, we are in a coherent state.
Signed-off-by: NGraf Yang <graf.yang@analog.com>
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

The previous commit that changed this code to the common GPIO layers
forgot to delete the local and now unused "i" variable.
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

No code uses these, and the short define names are polluting the global
namespace where they collide with things like common irq files.  So just
punt the damned things.  If in the future we need HDMA support, we can
make a standalone header for these things.
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

Hook up name_to_handle_at, open_by_handle_at, and clock_adjtime.
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

This patch fixes the Blackfin irqflags to make them I-pipe aware anew,
after the introduction of the hard_local_irq_*() API.
Signed-off-by: NPhilippe Gerum <rpm@xenomai.org>
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

This patch makes sure to sync the pipeline for the root stage only
from the outer interrupt level, when resuming kernel code after an
interrupt.

This fixes a bug causing EVT15 to be spuriously popped off upon nested
interrupts, which in turn would cause the preempted kernel code to
resume without supervisor privileges.
Signed-off-by: NPhilippe Gerum <rpm@xenomai.org>
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

This patch introduces Blackfin-specific bits to support the current
tip of the interrupt pipeline development, mainly:

- 2/3-level interrupt maps (sparse IRQs)
- generic virq handling
- sysinfo v2 format for ipipe_get_sysinfo()
Signed-off-by: NPhilippe Gerum <rpm@xenomai.org>
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

No functional changes here.
Signed-off-by: NMichael Hennerich <michael.hennerich@analog.com>
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

All chips converted.
Signed-off-by: NThomas Gleixner <tglx@linutronix.de>
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

Signed-off-by: NMike Frysinger <vapier@gentoo.org>

Signed-off-by: NThomas Gleixner <tglx@linutronix.de>
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

Signed-off-by: NThomas Gleixner <tglx@linutronix.de>
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

Signed-off-by: NThomas Gleixner <tglx@linutronix.de>
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

Signed-off-by: NThomas Gleixner <tglx@linutronix.de>
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

Signed-off-by: NThomas Gleixner <tglx@linutronix.de>
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

Signed-off-by: NThomas Gleixner <tglx@linutronix.de>
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

Signed-off-by: NThomas Gleixner <tglx@linutronix.de>
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

Fixup the open coded access to irq_desc and use the proper wrappers.
Signed-off-by: NThomas Gleixner <tglx@linutronix.de>
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

Take advantage of more Blackfin-specific insns, and only initialize
registers required by the ABI.
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

In order to safely work around anomaly 05000491, we have to execute IFLUSH
from L1 instruction sram.  The trouble with multi-core systems is that all
L1 sram is visible only to the active core.  So we can't just place the
functions into L1 and call it directly.  We need to setup a jump table and
place the entry point in external memory.  This will call the right func
based on the active core.

In the process, convert from the manual relocation of a small bit of code
into Core B's L1 to the more general framework we already have in place
for loading arbitrary pieces of code into L1.
Signed-off-by: NSonic Zhang <sonic.zhang@analog.com>
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

Re-use some of the existing cpu hotplugging code in the process.
Signed-off-by: NGraf Yang <graf.yang@analog.com>
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

We need to place icache flush funcs into L1 inst sram to work around a
hardware anomaly.  But this currently breaks SMP support as the L1 inst
sram is per-core and cannot be called directly.  So in preparation for
making that work, split the two options.

Further, split out the SMP depend so that we can allow some for SMP.
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

The smp_processor_id() API requires that preempt be disabled when calling
it, so make sure it is when we go to send messages to other processors.
Signed-off-by: NSonic Zhang <sonic.zhang@analog.com>
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

Defer bfin_setup_caches(cpu) to avoid unexpected faults due to the cpu
state not yet being fully initialized.
Signed-off-by: Nsteven miao <realmz6@gmail.com>
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

Signed-off-by: NMike Frysinger <vapier@gentoo.org>

Common code checks the alignment of some of the variables and calls BUG()
if they aren't page aligned.
Signed-off-by: Nsteven miao <realmz6@gmail.com>
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

We use these insns when testing, so enable them by default for all
of our development boards.
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

Common code no longer defines this, so stop using it.
Signed-off-by: NSonic Zhang <sonic.zhang@analog.com>
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

The board doesn't actually have a pin hooked up to do card detection,
so punt the code for it.
Signed-off-by: NAndreas Schallenberg <Andreas.Schallenberg@3alitydigital.de>
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

Signed-off-by: NMike Frysinger <vapier@gentoo.org>

Signed-off-by: NAaron Wu <aaronwu06@gmail.com>
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

The BF54x lacks dedicated DMA channels for the UART peripherals and need
to be muxed between others.  So add a kconfig option so people can select
which channels the UARTs will use so they can pick between SPORTs and the
less commonly used EPPI/PIXC peripherals.
Signed-off-by: Nsteven miao <realmz6@gmail.com>
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

Since coreb_trampoline_start() calls coreb_start(), they need to be in
the same section.
Signed-off-by: NSonic Zhang <sonic.zhang@analog.com>
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

Recent feedback from design says we need three NOPs in the hardware loop.
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

Some devices will use the outs* funcs with a length of zero, so make sure
we do not write any data in that case.
Reported-by: NGilbert Inho <gneny@edevice.com>
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

The RX lock is used to protect the RX buffer from concurrent access in DMA
mode between the timer and RX interrupt routines.  It is independent from
the uart lock which is used to protect the TX buffer.  It is possible for
a uart TX transfer to be started up from the RX interrupt handler if low
latency is enabled.  So we need to split the locks to avoid deadlocking in
this situation.

In PIO mode, the RX lock is not necessary because the handle_simple_irq
and handle_level_irq functions ensure driver interrupt handlers are called
once on one core.

And now that the RX path has its own lock, the TX interrupt has nothing to
do with the RX path, so disabling it at the same time.
Signed-off-by: NSonic Zhang <sonic.zhang@analog.com>
Signed-off-by: NMike Frysinger <vapier@gentoo.org>
Signed-off-by: NGreg Kroah-Hartman <gregkh@suse.de>

xtime_update() takes the xtime_lock itself.
Signed-off-by: NTorben Hohn <torbenh@gmx.de>
Cc: Mike Frysinger <vapier@gentoo.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: johnstul@us.ibm.com
Cc: hch@infradead.org
Cc: yong.zhang0@gmail.com
LKML-Reference: <20110127145931.23248.33917.stgit@localhost>
Signed-off-by: NThomas Gleixner <tglx@linutronix.de>

Currently percpu readmostly subsection may share cachelines with other
percpu subsections which may result in unnecessary cacheline bounce
and performance degradation.

This patch adds @cacheline parameter to PERCPU() and PERCPU_VADDR()
linker macros, makes each arch linker scripts specify its cacheline
size and use it to align percpu subsections.

This is based on Shaohua's x86 only patch.
Signed-off-by: NTejun Heo <tj@kernel.org>
Cc: Shaohua Li <shaohua.li@intel.com>