Blackfin: SMP: flush CoreB cache when shutting down

When CoreB wakes up, it needs to read variables that CoreA might have
modified, and might be in CoreB's cache.  So kill CoreB's cache before
going to sleep so that when we wake up, we are in a coherent state.
Signed-off-by: NGraf Yang <graf.yang@analog.com>
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

arch/blackfin/mach-bf561/hotplug.c

@@ -7,6 +7,7 @@
 
 #include <linux/smp.h>
 #include <asm/blackfin.h>
+#include <asm/cacheflush.h>
 #include <mach/pll.h>
 
 int hotplug_coreb;
@@ -14,8 +15,16 @@ int hotplug_coreb;
 void platform_cpu_die(void)
 {
 	unsigned long iwr;
+
 	hotplug_coreb = 1;
 
+	/*
+	 * When CoreB wakes up, the code in _coreb_trampoline_start cannot
+	 * turn off the data cache. This causes the CoreB failed to boot.
+	 * As a workaround, we invalidate all the data cache before sleep.
+	 */
+	blackfin_invalidate_entire_dcache();
+
 	/* disable core timer */
 	bfin_write_TCNTL(0);