1. 04 7月, 2016 2 次提交
  2. 02 7月, 2016 10 次提交
    • C
      drm/i915: Embed signaling node into the GEM request · b3850855
      Chris Wilson 提交于
      Under the assumption that enabling signaling will be a frequent
      operation, lets preallocate our attachments for signaling inside the
      (rather large) request struct (and so benefiting from the slab cache).
      
      v2: Convert from void * to more meaningful names and types.
      Signed-off-by: NChris Wilson <chris@chris-wilson.co.uk>
      Reviewed-by: NTvrtko Ursulin <tvrtko.ursulin@intel.com>
      Link: http://patchwork.freedesktop.org/patch/msgid/1467390209-3576-17-git-send-email-chris@chris-wilson.co.uk
      b3850855
    • C
      drm/i915: Convert trace-irq to the breadcrumb waiter · c81d4613
      Chris Wilson 提交于
      If we convert the tracing over from direct use of ring->irq_get() and
      over to the breadcrumb infrastructure, we only have a single user of the
      ring->irq_get and so we will be able to simplify the driver routines
      (eliminating the redundant validation and irq refcounting).
      
      Process context is preferred over softirq (or even hardirq) for a couple
      of reasons:
      
       - we already utilize process context to have fast wakeup of a single
         client (i.e. the client waiting for the GPU inspects the seqno for
         itself following an interrupt to avoid the overhead of a context
         switch before it returns to userspace)
      
       - engine->irq_seqno() is not suitable for use from an softirq/hardirq
         context as we may require long waits (100-250us) to ensure the seqno
         write is posted before we read it from the CPU
      
      A signaling framework is a requirement for enabling dma-fences.
      
      v2: Move to a signaling framework based upon the waiter.
      v3: Track the first-signal to avoid having to walk the rbtree everytime.
      v4: Mark the signaler thread as RT priority to reduce latency in the
      indirect wakeups.
      v5: Make failure to allocate the thread fatal.
      v6: Rename kthreads to i915/signal:%u
      Signed-off-by: NChris Wilson <chris@chris-wilson.co.uk>
      Reviewed-by: NTvrtko Ursulin <tvrtko.ursulin@intel.com>
      Link: http://patchwork.freedesktop.org/patch/msgid/1467390209-3576-16-git-send-email-chris@chris-wilson.co.uk
      c81d4613
    • C
      drm/i915: Only apply one barrier after a breadcrumb interrupt is posted · 3d5564e9
      Chris Wilson 提交于
      If we flag the seqno as potentially stale upon receiving an interrupt,
      we can use that information to reduce the frequency that we apply the
      heavyweight coherent seqno read (i.e. if we wake up a chain of waiters).
      
      v2: Use cmpxchg to replace READ_ONCE/WRITE_ONCE for more explicit
      control of the ordering wrt to interrupt generation and interrupt
      checking in the bottom-half.
      Signed-off-by: NChris Wilson <chris@chris-wilson.co.uk>
      Reviewed-by: NTvrtko Ursulin <tvrtko.ursulin@intel.com>
      Link: http://patchwork.freedesktop.org/patch/msgid/1467390209-3576-14-git-send-email-chris@chris-wilson.co.uk
      3d5564e9
    • C
      drm/i915: Check the CPU cached value in HWS of seqno after waking the waiter · 7ec2c73b
      Chris Wilson 提交于
      If we have multiple waiters, we may find that many complete on the same
      wake up. If we first inspect the seqno from the CPU cache, we may reduce
      the number of heavyweight coherent seqno reads we require.
      Signed-off-by: NChris Wilson <chris@chris-wilson.co.uk>
      Reviewed-by: NTvrtko Ursulin <tvrtko.ursulin@intel.com>
      Link: http://patchwork.freedesktop.org/patch/msgid/1467390209-3576-13-git-send-email-chris@chris-wilson.co.uk
      7ec2c73b
    • C
      drm/i915: Use HWS for seqno tracking everywhere · 1b7744e7
      Chris Wilson 提交于
      By using the same address for storing the HWS on every platform, we can
      remove the platform specific vfuncs and reduce the get-seqno routine to
      a single read of a cached memory location.
      
      v2: Fix semaphore_passed() to look at the signaling engine (not the
      waiter's)
      Signed-off-by: NChris Wilson <chris@chris-wilson.co.uk>
      Reviewed-by: NTvrtko Ursulin <tvrtko.ursulin@intel.com>
      Link: http://patchwork.freedesktop.org/patch/msgid/1467390209-3576-8-git-send-email-chris@chris-wilson.co.uk
      1b7744e7
    • C
      drm/i915: Spin after waking up for an interrupt · f69a02c9
      Chris Wilson 提交于
      When waiting for an interrupt (waiting for the engine to complete some
      work), we know we are the only waiter to be woken on this engine. We also
      know when the GPU has nearly completed our request (or at least started
      processing it), so after being woken and we detect that the GPU is
      active and working on our request, allow us the bottom-half (the first
      waiter who wakes up to handle checking the seqno after the interrupt) to
      spin for a very short while to reduce client latencies.
      
      The impact is minimal, there was an improvement to the realtime-vs-many
      clients case, but exporting the function proves useful later. However,
      it is tempting to adjust irq_seqno_barrier to include the spin. The
      problem is first ensuring that the "start-of-request" seqno is coherent
      as we use that as our basis for judging when it is ok to spin. If we
      could, spinning there could dramatically shorten some sleeps, and allow
      us to make the barriers more conservative to handle missed seqno writes
      on more platforms (all gen7+ are known to have the occasional issue, at
      least).
      Signed-off-by: NChris Wilson <chris@chris-wilson.co.uk>
      Reviewed-by: NTvrtko Ursulin <tvrtko.ursulin@intel.com>
      Link: http://patchwork.freedesktop.org/patch/msgid/1467390209-3576-7-git-send-email-chris@chris-wilson.co.uk
      f69a02c9
    • C
      drm/i915: Slaughter the thundering i915_wait_request herd · 688e6c72
      Chris Wilson 提交于
      One particularly stressful scenario consists of many independent tasks
      all competing for GPU time and waiting upon the results (e.g. realtime
      transcoding of many, many streams). One bottleneck in particular is that
      each client waits on its own results, but every client is woken up after
      every batchbuffer - hence the thunder of hooves as then every client must
      do its heavyweight dance to read a coherent seqno to see if it is the
      lucky one.
      
      Ideally, we only want one client to wake up after the interrupt and
      check its request for completion. Since the requests must retire in
      order, we can select the first client on the oldest request to be woken.
      Once that client has completed his wait, we can then wake up the
      next client and so on. However, all clients then incur latency as every
      process in the chain may be delayed for scheduling - this may also then
      cause some priority inversion. To reduce the latency, when a client
      is added or removed from the list, we scan the tree for completed
      seqno and wake up all the completed waiters in parallel.
      
      Using igt/benchmarks/gem_latency, we can demonstrate this effect. The
      benchmark measures the number of GPU cycles between completion of a
      batch and the client waking up from a call to wait-ioctl. With many
      concurrent waiters, with each on a different request, we observe that
      the wakeup latency before the patch scales nearly linearly with the
      number of waiters (before external factors kick in making the scaling much
      worse). After applying the patch, we can see that only the single waiter
      for the request is being woken up, providing a constant wakeup latency
      for every operation. However, the situation is not quite as rosy for
      many waiters on the same request, though to the best of my knowledge this
      is much less likely in practice. Here, we can observe that the
      concurrent waiters incur extra latency from being woken up by the
      solitary bottom-half, rather than directly by the interrupt. This
      appears to be scheduler induced (having discounted adverse effects from
      having a rbtree walk/erase in the wakeup path), each additional
      wake_up_process() costs approximately 1us on big core. Another effect of
      performing the secondary wakeups from the first bottom-half is the
      incurred delay this imposes on high priority threads - rather than
      immediately returning to userspace and leaving the interrupt handler to
      wake the others.
      
      To offset the delay incurred with additional waiters on a request, we
      could use a hybrid scheme that did a quick read in the interrupt handler
      and dequeued all the completed waiters (incurring the overhead in the
      interrupt handler, not the best plan either as we then incur GPU
      submission latency) but we would still have to wake up the bottom-half
      every time to do the heavyweight slow read. Or we could only kick the
      waiters on the seqno with the same priority as the current task (i.e. in
      the realtime waiter scenario, only it is woken up immediately by the
      interrupt and simply queues the next waiter before returning to userspace,
      minimising its delay at the expense of the chain, and also reducing
      contention on its scheduler runqueue). This is effective at avoid long
      pauses in the interrupt handler and at avoiding the extra latency in
      realtime/high-priority waiters.
      
      v2: Convert from a kworker per engine into a dedicated kthread for the
      bottom-half.
      v3: Rename request members and tweak comments.
      v4: Use a per-engine spinlock in the breadcrumbs bottom-half.
      v5: Fix race in locklessly checking waiter status and kicking the task on
      adding a new waiter.
      v6: Fix deciding when to force the timer to hide missing interrupts.
      v7: Move the bottom-half from the kthread to the first client process.
      v8: Reword a few comments
      v9: Break the busy loop when the interrupt is unmasked or has fired.
      v10: Comments, unnecessary churn, better debugging from Tvrtko
      v11: Wake all completed waiters on removing the current bottom-half to
      reduce the latency of waking up a herd of clients all waiting on the
      same request.
      v12: Rearrange missed-interrupt fault injection so that it works with
      igt/drv_missed_irq_hang
      v13: Rename intel_breadcrumb and friends to intel_wait in preparation
      for signal handling.
      v14: RCU commentary, assert_spin_locked
      v15: Hide BUG_ON behind the compiler; report on gem_latency findings.
      v16: Sort seqno-groups by priority so that first-waiter has the highest
      task priority (and so avoid priority inversion).
      v17: Add waiters to post-mortem GPU hang state.
      v18: Return early for a completed wait after acquiring the spinlock.
      Avoids adding ourselves to the tree if the is already complete, and
      skips the awkward question of why we don't do completion wakeups for
      waits earlier than or equal to ourselves.
      v19: Prepare for init_breadcrumbs to fail. Later patches may want to
      allocate during init, so be prepared to propagate back the error code.
      
      Testcase: igt/gem_concurrent_blit
      Testcase: igt/benchmarks/gem_latency
      Signed-off-by: NChris Wilson <chris@chris-wilson.co.uk>
      Cc: "Rogozhkin, Dmitry V" <dmitry.v.rogozhkin@intel.com>
      Cc: "Gong, Zhipeng" <zhipeng.gong@intel.com>
      Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
      Cc: Dave Gordon <david.s.gordon@intel.com>
      Cc: "Goel, Akash" <akash.goel@intel.com>
      Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com> #v18
      Link: http://patchwork.freedesktop.org/patch/msgid/1467390209-3576-6-git-send-email-chris@chris-wilson.co.uk
      688e6c72
    • C
      drm/i915: Separate GPU hang waitqueue from advance · 1f15b76f
      Chris Wilson 提交于
      Currently __i915_wait_request uses a per-engine wait_queue_t for the dual
      purpose of waking after the GPU advances or for waking after an error.
      In the future, we may add even more wake sources and require greater
      separation, but for now we can conceptually simplify wakeups by separating
      the two sources. In particular, this allows us to use different wait-queues
      (e.g. one on the engine advancement, a global one for errors and one on
      each requests) without any hassle.
      Signed-off-by: NChris Wilson <chris@chris-wilson.co.uk>
      Reviewed-by: NTvrtko Ursulin <tvrtko.ursulin@intel.com>
      Link: http://patchwork.freedesktop.org/patch/msgid/1467390209-3576-5-git-send-email-chris@chris-wilson.co.uk
      1f15b76f
    • C
      drm/i915: Make queueing the hangcheck work inline · 26a02b8f
      Chris Wilson 提交于
      Since the function is a small wrapper around schedule_delayed_work(),
      move it inline to remove the function call overhead for the principle
      caller.
      Signed-off-by: NChris Wilson <chris@chris-wilson.co.uk>
      Reviewed-by: NTvrtko Ursulin <tvrtko.ursulin@intel.com>
      Link: http://patchwork.freedesktop.org/patch/msgid/1467390209-3576-4-git-send-email-chris@chris-wilson.co.uk
      26a02b8f
    • C
      drm/i915: Remove the dedicated hangcheck workqueue · 77740025
      Chris Wilson 提交于
      The queue only ever contains at most one item and has no special flags.
      It is just a very simple wrapper around the system-wq - a complication
      with no benefits.
      
      v2: Use the system_long_wq as we may wish to capture the error state
      after detecting the hang - which may take a bit of time.
      Signed-off-by: NChris Wilson <chris@chris-wilson.co.uk>
      Reviewed-by: NTvrtko Ursulin <tvrtko.ursulin@intel.com>
      Link: http://patchwork.freedesktop.org/patch/msgid/1467390209-3576-3-git-send-email-chris@chris-wilson.co.uk
      77740025
  3. 30 6月, 2016 3 次提交
  4. 28 6月, 2016 1 次提交
  5. 24 6月, 2016 10 次提交
  6. 22 6月, 2016 1 次提交
  7. 21 6月, 2016 2 次提交
  8. 20 6月, 2016 2 次提交
  9. 19 6月, 2016 1 次提交
  10. 18 6月, 2016 6 次提交
    • Z
      drm/i915: Introduce GVT context creation API · c8c35799
      Zhi Wang 提交于
      GVT workload scheduler needs special host LRC contexts, the so called
      "shadow LRC context" to submit guest workload to host i915. During the
      guest workload submission, workload scheduler fills the shadow LRC
      context with the content of guest LRC context: engine context is copied
      without changes, ring context is mostly owned by host i915.
      
      v8:
      
      - Remove the graph temporarily. (Chris)
      - Use interruptible mutex_lock. (Chris)
      - Rename the function name of creating a GVT context. (Chris)
      - Add the missing declaration in i915_drv.h (Chris)
      
      v7:
      
      - Move chart to a better place. (Joonas)
      
      v6:
      
      - Make GVT code as dead code when !CONFIG_DRM_I915_GVT. (Chris)
      
      v5:
      - Only compile this feature when CONFIG_DRM_I915_GVT is enabled. (Tvrtko)
      - Rebase the code into new repo.
      - Add a comment about the ring buffer size. (Joonas)
      
      v2:
      
      Mostly based on Daniel's idea. Call the refactored core logic of GEM
      context creation service and LRC context creation service to create the GVT
      context.
      Reviewed-by: NJoonas Lahtinen <joonas.lahtinen@linux.intel.com>
      Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
      Cc: Chris Wilson <chris@chris-wilson.co.uk>
      Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
      Signed-off-by: NZhi Wang <zhi.a.wang@intel.com>
      Signed-off-by: NChris Wilson <chris@chris-wilson.co.uk>
      Link: http://patchwork.freedesktop.org/patch/msgid/1466078825-6662-10-git-send-email-zhi.a.wang@intel.com
      c8c35799
    • Z
      drm/i915: Support LRC context single submission · 80a9a8db
      Zhi Wang 提交于
      This patch introduces the support of LRC context single submission.
      As GVT context may come from different guests, which require different
      configuration of render registers. It can't be combined into a dual ELSP
      submission combo.
      
      Only GVT-g will create this kinds of GEM context currently.
      
      v8:
      
      - Rename the data member in struct i915_gem_context. (Chris)
      
      v7:
      
      - Fix typos in commit message. (Joonas)
      
      v6:
      - Make GVT code as dead code when !CONFIG_DRM_I915_GVT. (Chris)
      
      v5:
      
      - Only compile this feature when CONFIG_DRM_I915_GVT=y. (Tvrtko)
      Reviewed-by: NJoonas Lahtinen <joonas.lahtinen@linux.intel.com>
      Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
      Cc: Chris Wilson <chris@chris-wilson.co.uk>
      Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
      Signed-off-by: NZhi Wang <zhi.a.wang@intel.com>
      Signed-off-by: NChris Wilson <chris@chris-wilson.co.uk>
      Link: http://patchwork.freedesktop.org/patch/msgid/1466078825-6662-9-git-send-email-zhi.a.wang@intel.com
      80a9a8db
    • Z
      drm/i915: Introduce execlist context status change notification · 3c7ba635
      Zhi Wang 提交于
      This patch introduces an approach to track the execlist context status
      change.
      
      GVT-g uses GVT context as the "shadow context". The content inside GVT
      context will be copied back to guest after the context is idle. And GVT-g
      has to know the status of the execlist context.
      
      This function is configurable when creating a new GEM context. Currently,
      Only GVT-g will create the "status-change-notification" enabled GEM
      context.
      
      v10:
      
      - Fix the identation. (Joonas)
      
      v8:
      
      - Remove the boolean flag in struct i915_gem_context. (Joonas)
      
      v7:
      
      - Remove per-engine ctx status notifiers. Use one status notifier for all
      engines. (Joonas)
      - Add prefix "INTEL_" for related definitions. (Joonas)
      - Refine the comments in execlists_context_status_change(). (Joonas)
      
      v6:
      
      - When !CONFIG_DRM_I915_GVT, make GVT code as dead code then compiler
      could automatically eliminate them for us. (Chris)
      - Always initialize the notifier header, so it could be switched on/off
      at runtime. (Chris)
      
      v5:
      
      - Only compile this feature when CONFIG_DRM_I915_GVT is enabled.(Tvrtko)
      
      Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> (v8)
      Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
      Cc: Chris Wilson <chris@chris-wilson.co.uk>
      Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
      Signed-off-by: NZhi Wang <zhi.a.wang@intel.com>
      Link: http://patchwork.freedesktop.org/patch/msgid/1466078825-6662-8-git-send-email-zhi.a.wang@intel.comSigned-off-by: NChris Wilson <chris@chris-wilson.co.uk>
      3c7ba635
    • Z
      drm/i915: Make addressing mode bits in context descriptor configurable · c01fc532
      Zhi Wang 提交于
      Currently the addressing mode bit in context descriptor is statically
      generated from the configuration of system-wide PPGTT usage model.
      
      GVT-g will load the PPGTT shadow page table by itself and probably one
      guest is using a different addressing mode with i915 host. The addressing
      mode bits of a LRC context should be configurable under this case.
      
      v10:
      
      - Fix the identation. (Joonas)
      
      v9:
      - Rename the data member in struct i915_gem_context. (Chris)
      
      v8:
      - Rename the data member in struct i915_gem_context. (Chris)
      
      v7:
      - Move context addressing mode bit into i915_reg.h. (Joonas/Chris)
      - Add prefix "INTEL_" for related definitions. (Joonas)
      
      v6:
      - Directly save the addressing mode bits inside i915_gem_context. (Chris)
      - Move the LRC context addressing mode bits into intel_lrc.h. (Chris)
      
      v5:
      - Change USES_FULL_48BIT(dev) to USES_FULL_48BIT(dev_priv) (Tvrtko)
      
      Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> (v9)
      Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
      Cc: Chris Wilson <chris@chris-wilson.co.uk>
      Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
      Signed-off-by: NZhi Wang <zhi.a.wang@intel.com>
      Signed-off-by: NChris Wilson <chris@chris-wilson.co.uk>
      Link: http://patchwork.freedesktop.org/patch/msgid/1466078825-6662-7-git-send-email-zhi.a.wang@intel.com
      c01fc532
    • Z
      drm/i915: Make ring buffer size of a LRC context configurable · bcd794c2
      Zhi Wang 提交于
      This patch introduces an option for configuring the ring buffer size
      of a LRC context after the context creation.
      
      v9:
      - Fix an identation issue. (Chris)
      
      v8:
      - Rename the data member in i915_gem_context. (Chris)
      Reviewed-by: NJoonas Lahtinen <joonas.lahtinen@linux.intel.com>
      Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
      Cc: Chris Wilson <chris@chris-wilson.co.uk>
      Signed-off-by: NZhi Wang <zhi.a.wang@intel.com>
      Signed-off-by: NChris Wilson <chris@chris-wilson.co.uk>
      Link: http://patchwork.freedesktop.org/patch/msgid/1466078825-6662-6-git-send-email-zhi.a.wang@intel.com
      bcd794c2
    • Z
      drm/i915: gvt: Introduce the basic architecture of GVT-g · 0ad35fed
      Zhi Wang 提交于
      This patch introduces the very basic framework of GVT-g device model,
      includes basic prototypes, definitions, initialization.
      
      v12:
      - Call intel_gvt_init() in driver early initialization stage. (Chris)
      
      v8:
      - Remove the GVT idr and mutex in intel_gvt_host. (Joonas)
      
      v7:
      - Refine the URL link in Kconfig. (Joonas)
      - Refine the introduction of GVT-g host support in Kconfig. (Joonas)
      - Remove the macro GVT_ALIGN(), use round_down() instead. (Joonas)
      - Make "struct intel_gvt" a data member in struct drm_i915_private.(Joonas)
      	- Remove {alloc, free}_gvt_device()
      	- Rename intel_gvt_{create, destroy}_gvt_device()
      	- Expost intel_gvt_init_host()
      - Remove the dummy "struct intel_gvt" declaration in intel_gvt.h (Joonas)
      
      v6:
      - Refine introduction in Kconfig. (Chris)
      - The exposed API functions will take struct intel_gvt * instead of
      void *. (Chris/Tvrtko)
      - Remove most memebers of strct intel_gvt_device_info. Will add them
      in the device model patches.(Chris)
      - Remove gvt_info() and gvt_err() in debug.h. (Chris)
      - Move GVT kernel parameter into i915_params. (Chris)
      - Remove include/drm/i915_gvt.h, as GVT-g will be built within i915.
      - Remove the redundant struct i915_gvt *, as the functions in i915
      will directly take struct intel_gvt *.
      - Add more comments for reviewer.
      
      v5:
      Take Tvrtko's comments:
      - Fix the misspelled words in Kconfig
      - Let functions take drm_i915_private * instead of struct drm_device *
      - Remove redundant prints/local varible initialization
      
      v3:
      Take Joonas' comments:
      - Change file name i915_gvt.* to intel_gvt.*
      - Move GVT kernel parameter into intel_gvt.c
      - Remove redundant debug macros
      - Change error handling style
      - Add introductions for some stub functions
      - Introduce drm/i915_gvt.h.
      
      Take Kevin's comments:
      - Move GVT-g host/guest check into intel_vgt_balloon in i915_gem_gtt.c
      
      v2:
      - Introduce i915_gvt.c.
      It's necessary to introduce the stubs between i915 driver and GVT-g host,
      as GVT-g components is configurable in kernel config. When disabled, the
      stubs here do nothing.
      
      Take Joonas' comments:
      - Replace boolean return value with int.
      - Replace customized info/warn/debug macros with DRM macros.
      - Document all non-static functions like i915.
      - Remove empty and unused functions.
      - Replace magic number with marcos.
      - Set GVT-g in kernel config to "n" by default.
      Reviewed-by: NJoonas Lahtinen <joonas.lahtinen@linux.intel.com>
      Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
      Cc: Chris Wilson <chris@chris-wilson.co.uk>
      Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
      Cc: Kevin Tian <kevin.tian@intel.com>
      Signed-off-by: NZhi Wang <zhi.a.wang@intel.com>
      Link: http://patchwork.freedesktop.org/patch/msgid/1466078825-6662-5-git-send-email-zhi.a.wang@intel.comSigned-off-by: NChris Wilson <chris@chris-wilson.co.uk>
      0ad35fed
  11. 14 6月, 2016 1 次提交
    • A
      drm/i915:bxt: Enable Pooled EU support · 33e141ed
      arun.siluvery@linux.intel.com 提交于
      This mode allows to assign EUs to pools which can process work collectively.
      The command to enable this mode should be issued as part of context initialization.
      
      The pooled mode is global, once enabled it has to stay the same across all
      contexts until HW reset hence this is sent in auxiliary golden context batch.
      Thanks to Mika for the preliminary review and comments.
      
      v2: explain why this is enabled in golden context, use feature flag while
      enabling the support (Chris)
      
      v3: Include only kernel support as userspace support is not available yet.
      
      User space clients need to know when the pooled EU feature is present
      and enabled on the hardware so that they can adapt work submissions.
      Create a new device info flag for this purpose.
      
      Set has_pooled_eu to true in the Broxton static device info - Broxton
      supports the feature in hardware and the driver will enable it by
      default.
      
      We need to add getparam ioctls to enable userspace to query availability of
      this feature and to retrieve min. no of eus in a pool but we will expose
      them once userspace support is available. Opensource users for this feature
      are mesa, libva and beignet.
      
      Beignet team is currently working on adding userspace support.
      
      Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> (v2)
      Cc: Winiarski, Michal <michal.winiarski@intel.com>
      Cc: Zou, Nanhai <nanhai.zou@intel.com>
      Cc: Yang, Rong R <rong.r.yang@intel.com>
      Cc: Mika Kuoppala <mika.kuoppala@intel.com>
      Cc: Chris Wilson <chris@chris-wilson.co.uk>
      Cc: Armin Reese <armin.c.reese@intel.com>
      Cc: Tim Gore <tim.gore@intel.com>
      Signed-off-by: NJeff McGee <jeff.mcgee@intel.com>
      Signed-off-by: NArun Siluvery <arun.siluvery@linux.intel.com>
      Reviewed-by: NMichał Winiarski <michal.winiarski@intel.com>
      Signed-off-by: NTvrtko Ursulin <tvrtko.ursulin@intel.com>
      33e141ed
  12. 13 6月, 2016 1 次提交