This new implemenatation avoids that two physical pins are claimed by
the same driver (also with the the gpr hardware modes).
The gpio kernel lib is also called when a capable gpio pin is assigned
its gpio function.
The mxc_iomux_mode function is still here for backward compatibility but
should not be used anymore.

V2:

In the precendent revision, the iomux code was claiming a pin when its
hardware mode was changed. This was uncorrect: when the hardware mode is
changed, the pin must still be claimed through the iomux.

In order to have a pin working in mode hw2, we must fist issue the
mxc_iomux_set_gpr call and then the corresponding mxc_iomux_mode calls
with the FUNC mode (usually done with mxc_iomux_setup_multiple_pins).
The reverse calls must be done to fee the pins.
Signed-off-by: NValentin Longchamp <valentin.longchamp@epfl.ch>
Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>

... from both mx27ads.c and pcm038.c
Signed-off-by: NUwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>
Cc: Holger Schurig <hs4233@mail.mn-solutions.de>
Cc: Russell King <rmk+kernel@arm.linux.org.uk>
Cc: Sascha Hauer <s.hauer@pengutronix.de>
Cc: Martin Fuzzey <mfuzzey@gmail.com>

Add a return 0 analogous to uart_mxc_port[0-2]_exit.
Signed-off-by: NUwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>
Cc: Holger Schurig <hs4233@mail.mn-solutions.de>
Cc: Russell King <rmk+kernel@arm.linux.org.uk>
Cc: Sascha Hauer <s.hauer@pengutronix.de>
Cc: Martin Fuzzey <mfuzzey@gmail.com>

Keeps sparse happy.
Signed-off-by: NMark Brown <broonie@opensource.wolfsonmicro.com>
Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>

Several of the macros in mx31ads.h depend on mx31.h which is no longer
included in quite so many standard headers as it once was. Include it
directly so we can build.
Signed-off-by: NMark Brown <broonie@opensource.wolfsonmicro.com>
Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>

The i.MX I2C driver has not yet been merged into mainline but it is
near to that and the device defintions don't depend directly on it
so we can add the devices now.
Signed-off-by: NMark Brown <broonie@opensource.wolfsonmicro.com>
Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>

This patch mimicks what Martin wrote on the mailing list:

* move arch/arm/mach-imx/include/mach/imxfb.h into
  arch/arm/mach-mxc/include/mach/imxfb.h
* changes Kconfig so that CONFIG_FB_IMX is selectable
* adds a platform device (copied from some pengutronix
  patches)
Signed-off-by: NHolger Schurig <hs4233@mail.mn-solutions.de>
Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>

Based on code from "Martin Fuzzey" <mfuzzey@gmail.com>
Signed-off-by: NHolger Schurig <hs4233@mail.mn-solutions.de>
Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>

* define new CONFIG_ARCH_MX21 (this one is currently mutually exclusive to
  CONFIG_ARCH_MX27, but this might change)
* splits one header file. Memory definitions, interrupt sources,
  DMA channels are split into common part, i.MX27 specific and i.MX21
  specific.
* guard access to UART5/UART6, which don't exist on i.MX21
Signed-off-by: NHolger Schurig <hs4233@mail.mn-solutions.de>
Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>

Here are some of the warnings that get fixed by this:

> 200 times: warning: cast adds address space to expression (<asn:2>)
twelve times: warning: symbol 'xxx' was not declared. Should it be static
two times: warning: symbol 'clock' shadows an earlier one
five times: warning: incorrect type in initializer (different address spaces)
Signed-off-by: NHolger Schurig <hs4233@mail.mn-solutions.de>
Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>

This changes MX27 to use common clkdev. It also cleans up MX27 clock
support to be more readable.
Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>

This patch only adds general clkdev support without actually switching
any MXC architecture to clkdev.
Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>

The context makes it clear already that these are clocks, so there's
no need for such a suffix. This patch only changes the clocks actually
used in the tree. The remaining clocks are renamed in the subsequent
architecture specific patches.
Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>

- rename mxc_clocks_init to architecture specific versions. This
  allows us to have more than one architecture compiled in.
- call mxc_timer_init from clock initialisation instead from board
  code
Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>

We had 3 versions of this function in clock support for MX1/2/3
Use a single one instead. I picked the one from the MX3 as it seems
to calculate more accurate as the other ones. Also, on MX27 and MX31 mfn
can be negative, this hasn't been handled correctly on MX27 since now.

This patch has been tested on MX27 and MX31 and produces the same clock
frequencies for me.
Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>

* adds Kconfig variables
* specifies different physical address for i.MX21 because of the
  different memory layouts
* disables support for UART5/UART6 in the i.MX serial driver
  (the i.MX21 doesn't have those modules)

Based on code from "Martin Fuzzey" <mfuzzey@gmail.com>
Signed-off-by: NHolger Schurig <hs4233@mail.mn-solutions.de>
Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>

* removed iomux-mx1-mx2.h completely
* distributes the former contents to four different files (iomux-mx1.h,
  iomux-mx21.h, iomux-mx27.h and the file iomux-mx2x.h, which is common to
  both i.MX21 and i.MX27).
* adds all documented IOMUX definitions for i.MX21 and i.MX27
* fixes a few that were wrong (PD14_AOUT_FEC_CLR, PE16_AF_RTCK).
* don't silenly include <linux/io.h>
* and fixes all collateral damage from above
Signed-off-by: NHolger Schurig <hs4233@mail.mn-solutions.de>
Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>

Signed-off-by: NStanislaw Gruszka <stf_xl@wp.pl>
Cc: Andrew Victor <avictor.za@gmail.com>
Acked-by: NSergei Shtylyov <sshtylyov@ru.mvista.com>
Acked-by: NAndrew Victor <linux@maxim.org.za>
Signed-off-by: NBartlomiej Zolnierkiewicz <bzolnier@gmail.com>

This is IDE host driver for AT91 (SAM9, CAP9, AT572D940HF) Static Memory
Controller with Compact Flash True IDE Mode logic.

Driver have to switch 8/16 bit bus width when accessing Task Tile or Data
Register. Moreover some extra things need to be done when setting PIO mode.
Only PIO mode is used, hardware have no DMA support. If interrupt line is
connected through GPIO extra quirk is needed to cope with fake interrupts.
Signed-off-by: NStanislaw Gruszka <stf_xl@wp.pl>
Cc: Andrew Victor <avictor.za@gmail.com>
Acked-by: NSergei Shtylyov <sshtylyov@ru.mvista.com>
Signed-off-by: NBartlomiej Zolnierkiewicz <bzolnier@gmail.com>

The cacheid_init() function assumes that if cpu_architecture() returns
7, the caches are VIPT_NONALIASING. The cpu_architecture() function
returns the version of the supported MMU features (e.g. TEX remapping)
but it doesn't make any assumptions about the cache type. The patch adds
the checking of the Cache Type Register for the ARMv7 format.
Signed-off-by: NCatalin Marinas <catalin.marinas@arm.com>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

The target of the strex instruction to clear the exlusive monitor
is currently the top of the stack.  If the store succeeeds this
corrupts r0 in pt_regs.  Use the next stack location instead of
the current one to prevent any chance of corrupting an in-use
address.
Signed-off-by: NSeth Forshee <seth.forshee@gmail.com>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

The following patch enables SMC911x support to work on the OMAP LDP
board.  Although the SMC911x driver will eventually be obsoleted, the
smsc911x patches are rather invasive for the -rc kernels.

Rather than risk destablising smsc911x, this simpler patch is preferred
to allow the network interface to work.
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
Acked-by: NTony Lindgren <tony@atomide.com>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>

Now that the musb build fixes for DaVinci got merged (RC3?), kick in
the other bits needed to get it finally *working* in mainline:

 - Use clk_enable()/clk_disable() ... the "always enable USB clocks"
   code this originally relied on has since been removed.

 - Initialize the USB device only after the relevant I2C GPIOs are
   available, so the host side can properly enable VBUS.

 - Tweak init sequencing to cope with mainline's relatively late init
   of the I2C system bus for power switches, transceivers, and so on.

Sanity tested on DM6664 EVM for host and peripheral modes; that system
won't boot with CONFIG_PM enabled, so OTG can't yet be tested.  Also
verified on OMAP3.

(Unrelated:  correct the MODULE_PARM_DESC spelling of musb_debug.)
Signed-off-by: NDavid Brownell <dbrownell@users.sourceforge.net>
Cc: Felipe Balbi <me@felipebalbi.com>
Signed-off-by: NGreg Kroah-Hartman <gregkh@suse.de>

Currently the unmask function for EINT interrupts was setting the mask
bit rather than clearing it.  This was also previously reported and
fixed by Kyungmin Park <kyungmin.park@samsung.com> and others.
Acked-By: NBen Dooks <ben-linux@fluff.org>
Signed-off-by: NMark Brown <broonie@opensource.wolfsonmicro.com>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

Add the necessary i2c_board_info structure to fix the lack of PCF8583
RTC on RiscPC.
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: NJean Delvare <khali@linux-fr.org>
Cc: Alessandro Zummo <a.zummo@towertech.it>

We've discovered that our AT91SAM9260 board consumed too much power when
returning from a slowclock low-power mode.  RAM self-refresh is enabled in
a bootloader in our case, this is how we saw a difference.  Estimated ca.
30mA more on 4V battery than the same state before powersaving.

After a small research we found that there seems to be a bogus
sdram_selfrefresh_disable() call at the end of at91_pm_enter() call, which
overwrites the LPR register with uninitialized value.  Please find the
suggested patch attached.

This patch fixes correct restoring of LPR register of the Atmel AT91 SDRAM
controller when returning from a power saving mode.
Signed-off-by: NAndrei Birjukov <andrei.birjukov@artecdesign.ee>
Acked-by: NAndrew Victor <linux@maxim.org.za>
Signed-off-by: NAndrew Morton <akpm@linux-foundation.org>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

Remove the gesbc9312.h header since it is unused.
Signed-off-by: NH Hartley Sweeten <hsweeten@visionengravers.com>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

READ_IMPLIES_EXEC must be set when:
o binary _is_ an executable stack (i.e. not EXSTACK_DISABLE_X)
o processor architecture is _under_ ARMv6 (XN bit is supported from ARMv6)
Signed-off-by: NMakito SHIOKAWA <lkhmkt@gmail.com>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

When changing the parent of a clock, it is necessary to keep the
clock use counts balanced otherwise things the parent state will
get corrupted.  Since we already disable and re-enable the clock,
we might as well use the recursive versions instead.
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

In the non highmem case, if two memory banks of 1GB each are provided,
the second bank would evade suppression since its virtual base would
be 0.  Fix this by disallowing any memory bank which virtual base
address is found to be lower than PAGE_OFFSET.
Reported-by: NLennert Buytenhek <buytenh@marvell.com>
Signed-off-by: NNicolas Pitre <nico@marvell.com>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

The GPIO interrupts can be configured as either level triggered or edge
triggered, with a default of level triggered.  When an edge triggered
interrupt is requested, the gpio_irq_set_type method is called which
currently switches the given IRQ descriptor between two struct irq_chip
instances: orion_gpio_irq_level_chip and orion_gpio_irq_edge_chip. This
happens via __setup_irq() which also calls irq_chip_set_defaults() to
assign default methods to uninitialized ones.  The problem is that
irq_chip_set_defaults() is called before the irq_chip reference is
switched, leaving the new irq_chip (orion_gpio_irq_edge_chip in this
case) with uninitialized methods such as chip->startup() causing a kernel
oops.

Many solutions are possible, such as making irq_chip_set_defaults() global
and calling it from gpio_irq_set_type(), or calling __irq_set_trigger()
before irq_chip_set_defaults() in __setup_irq().  But those require
modifications to the generic IRQ code which might have adverse effect on
other architectures, and that would still be a fragile arrangement.
Manually copying the missing methods from within gpio_irq_set_type()
would be really ugly and it would break again the day new methods with
automatic defaults are added.

A better solution is to have a single irq_chip instance which can deal
with both edge and level triggered interrupts.  It is also a good idea
to switch the IRQ handler instead, as the edge IRQ handler allows for
one edge IRQ event to be queued as the IRQ is actually masked only when
that second IRQ is received, at which point the hardware can queue an
additional IRQ event, making edge triggered interrupts a bit more
reliable.
Tested-by: NMartin Michlmayr <tbm@cyrius.com>
Signed-off-by: NNicolas Pitre <nico@marvell.com>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

Add support for inverted rdy_busy pin for Atmel nand device controller
It will fix building error on NeoCore926 board.
Acked-by: NAndrew Victor <linux@maxim.org.za>
Acked-by: NDavid Woodhouse <David.Woodhouse@intel.com>
Signed-off-by: NGregory CLEMENT <gclement@adeneo.adetelgroup.com>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

Enable the GPIO clocks earlier in the initialization sequence.  This
allow the board-setup code to read and set GPIO pins.
Signed-off-by: NMarc Pignat <marc.pignat@hevs.ch>
Signed-off-by: NAndrew Victor <linux@maxim.org.za>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

The recently merged AT91SAM9 watchdog driver uses the
AT91SAM9X_WATCHDOG config variable, whereas the original version of
the driver (and the platform support code) used AT91SAM9_WATCHDOG.
This causes the watchdog platform_device to never be registered, and
therefore the driver not to be initialized.

This patch:
- updates the platform support code to use AT91SAM9X_WATCHDOG.
- includes <linux/io.h> to fix compile error (same fix as was applied
to at91rm9200_wdt.c)
- fixes comment regarding watchdog clock-rates in at91rm9200.
Signed-off-by: NAndrew Victor <linux@maxim.org.za>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

_omap2_clksel_get_src_field() was returning the first entry which was
either the default _or_ applicable to the SoC.  This is wrong - we
should be returning the first default which is applicable to the SoC.
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

The error checks for omap2_divisor_to_clksel() and comment disagree with
the actual value returned on error.  Fix this to return the correct error
value.
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

The C99 specification states in section 6.11.5:

The placement of a storage-class specifier other than at the beginning of the
declaration specifiers in a declaration is an obsolescent feature.
Signed-off-by: NTobias Klauser <tklauser@distanz.ch>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

This patch adds a MX2/MX3 specific SDHC driver. The hardware is basically
the same as in the MX1, but unlike the MX1 controller the MX2
controller just works as expected. Since the MX1 driver has more
workarounds for bugs than anything else I had no success with supporting
MX1 and MX2 in a sane way in one driver.
Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: NPierre Ossman <drzeus@drzeus.cx>

"flash" is a very generic name for a platform_driver that is only
available on SA11x0.
Signed-off-by: NUwe Kleine-König <u.kleine-koenig@pengutronix.de>
Cc: Nicolas Pitre <nico@marvell.com>

Signed-off-by: NUwe Kleine-König <u.kleine-koenig@pengutronix.de>