- 20 10月, 2017 3 次提交
-
-
由 Geert Uytterhoeven 提交于
Move R-Car M3-W I/O voltage support over to the generic way to describe IOCTRL registers, which will be needed for suspend/resume support. Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>
-
由 Geert Uytterhoeven 提交于
Move R-Car M3-W bias support over to the generic way to describe bias registers, which will be needed for suspend/resume support. As the new description is more compact, this decreases kernel size by ca. 304 bytes. Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>
-
由 Geert Uytterhoeven 提交于
On modern Renesas SoCs, all PFC registers are 32-bit, and all callers of sh_pfc_{read,write}_reg() already operate on 32-bit registers only. Hence make the 32-bit width implicit, and rename the functions to sh_pfc_{read,write}() to shorten lines. All accesses to 8-bit or 16-bit registers are still done using sh_pfc_{read,write}_raw_reg(). Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: NLaurent Pinchart <laurent.pinchart@ideasonboard.com>
-
- 11 10月, 2017 2 次提交
-
-
由 Wolfram Sang 提交于
Signed-off-by: NWolfram Sang <wsa+renesas@sang-engineering.com> Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>
-
由 Takeshi Kihara 提交于
Most pins on the r8a7796 SoC can be configured in GPIO mode for interrupt and GPIO functionality, while a couple of them can also be routed to the INTC-EX hardware block (formerly known as IRQC). On r8a7795 the INTC-EX hardware handles pins IRQ0 -> IRQ5 and this patch adds support for them to the PFC driver as "intc_ex_irqN". [takeshi.kihara.df: Ported from commit bb46f6f3 ("pinctrl: sh-pfc: r8a7795: Add support for INTC-EX IRQ pins") to drivers/pinctrl/sh-pfc/pfc-r8a7796.c] Signed-off-by: NTakeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>
-
- 16 8月, 2017 2 次提交
-
-
由 Takeshi Kihara 提交于
This patch adds USB30 (USB3.0 host) pin, group and function to R8A7796 SoC. Signed-off-by: NTakeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: NYoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>
-
由 Takeshi Kihara 提交于
This patch adds USB{0,1} (USB2.0 host) pins, groups and functions to R8A7796 SoC. Signed-off-by: NTakeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: NYoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>
-
- 17 7月, 2017 14 次提交
-
-
由 Takeshi Kihara 提交于
This patch renames the pin function macro definitions of the GPSR1 and IPSR4 registers value for the CS1# pin. This is a correction because GPSR and IPSR register specification for R8A7796 SoC was changed in R-Car Gen3 Hardware User's Manual Rev.0.54E. Fixes: f9aece73 ("pinctrl: sh-pfc: Initial R8A7796 PFC support") Signed-off-by: NTakeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: NYoshihiro Kaneko <ykaneko0929@gmail.com> Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>
-
由 Takeshi Kihara 提交于
This patch fixes IPSR{12,17,18} and MOD_SEL0 pin assignment for FSO pins group. This is a correction because GPSR and IPSR register specification for R8A7796 SoC was changed in R-Car Gen3 Hardware User's Manual Rev.0.54E. Fixes: f9aece73 ("pinctrl: sh-pfc: Initial R8A7796 PFC support") Signed-off-by: NTakeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: NYoshihiro Kaneko <ykaneko0929@gmail.com> Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>
-
由 Takeshi Kihara 提交于
This patch fixes the macro definitions of MOD_SEL0 bit2 register deleted. This is a correction because MOD_SEL register specification for R8A7796 SoC was changed in R-Car Gen3 Hardware User's Manual Rev.0.53E. Fixes: f9aece73 ("pinctrl: sh-pfc: Initial R8A7796 PFC support") Signed-off-by: NTakeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: NYoshihiro Kaneko <ykaneko0929@gmail.com> Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>
-
由 Takeshi Kihara 提交于
This patch fixes the macro definitions of SATA_DEVSLP_B pins function deleted. This is a correction to the incorrect implementation of IPSR register pin assignment for R8A7796 SoC specification of R-Car Gen3 Hardware User's Manual Rev.0.51E or later. Fixes: f9aece73 ("pinctrl: sh-pfc: Initial R8A7796 PFC support") Signed-off-by: NTakeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: NYoshihiro Kaneko <ykaneko0929@gmail.com> Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>
-
由 Takeshi Kihara 提交于
This patch fixes the macro definitions of FSCLKST pins function and IPSR7 bit[15:12] register deleted. This is a correction because IPSR register specification for R8A7796 SoC was changed in R-Car Gen3 Hardware User's Manual Rev.0.53E or later. Fixes: f9aece73 ("pinctrl: sh-pfc: Initial R8A7796 PFC support") Signed-off-by: NTakeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: NYoshihiro Kaneko <ykaneko0929@gmail.com> Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>
-
由 Takeshi Kihara 提交于
This patch fixes to set MOD_SEL2 bit19 when using TCLK2_A pin function is selected for IPSR16 bit[23:20] or using TCLK2_B pin function is selected for IPSR17 bit[27:24]. This is a correction to the incorrect implementation of MOD_SEL register pin assignment for R8A7796 SoC specification of R-Car Gen3 Hardware User's Manual Rev.0.51E or later. Fixes: f9aece73 ("pinctrl: sh-pfc: Initial R8A7796 PFC support") Signed-off-by: NTakeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: NYoshihiro Kaneko <ykaneko0929@gmail.com> Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>
-
由 Takeshi Kihara 提交于
This patch fixes the implementation incorrect of IPSR register value definitions for NFDATA{0..13} and NF{ALE,CLE,WE_N,RE_N} pins function. This is a correction to the incorrect implementation of IPSR register pin assignment for R8A7796 SoC specification of R-Car Gen3 Hardware User's Manual Rev.0.51E or later. Fixes: f9aece73 ("pinctrl: sh-pfc: Initial R8A7796 PFC support") Signed-off-by: NTakeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: NYoshihiro Kaneko <ykaneko0929@gmail.com> Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>
-
由 Takeshi Kihara 提交于
This patch fixes the implementation incorrect of IPSR register value definitions for FMCLK{_C,_D} and FMIN{_C,_D} pins function. This is a correction to the incorrect implementation of IPSR register pin assignment for R8A7796 SoC specification of R-Car Gen3 Hardware User's Manual Rev.0.51E or later. Fixes: f9aece73 ("pinctrl: sh-pfc: Initial R8A7796 PFC support") Signed-off-by: NTakeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: NYoshihiro Kaneko <ykaneko0929@gmail.com> Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>
-
由 Takeshi Kihara 提交于
This patch fixes SCIF_CLK_{A,B} pin's MOD_SEL assignment from MOD_SEL1 bit11 to MOD_SEL1 bit10. This is a correction to the incorrect implementation of IPSR register pin assignment for R8A7796 SoC specification of R-Car Gen3 Hardware User's Manual Rev.0.51E or later. Fixes: f9aece73 ("pinctrl: sh-pfc: Initial R8A7796 PFC support") Signed-off-by: NTakeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: NYoshihiro Kaneko <ykaneko0929@gmail.com> Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>
-
由 Takeshi Kihara 提交于
This patch fixes the implementation incorrect of MOD_SEL2 bit26 value when SCK5_A pin function is selected for IPSR16 bit[31:28]. This is a correction to the incorrect implementation of MOD_SEL register pin assignment for R8A7796 SoC specification of R-Car Gen3 Hardware User's Manual Rev.0.51E or later. Fixes: f9aece73 ("pinctrl: sh-pfc: Initial R8A7796 PFC support") Signed-off-by: NTakeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: NYoshihiro Kaneko <ykaneko0929@gmail.com> Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>
-
由 Takeshi Kihara 提交于
This patch fixes the implementation incorrect of MOD_SEL1 bit[25:24] value when STP_ISEN_1_D pin function is selected for IPSR17 bit[27:24]. This is a correction to the incorrect implementation of MOD_SEL register pin assignment for R8A7796 SoC specification of R-Car Gen3 Hardware User's Manual Rev.0.51E or later. Fixes: f9aece73 ("pinctrl: sh-pfc: Initial R8A7796 PFC support") Signed-off-by: NTakeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: NYoshihiro Kaneko <ykaneko0929@gmail.com> Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>
-
由 Geert Uytterhoeven 提交于
Fix a copy-and-paste bug in the MSIOF3 SS2_E mux array. Fixes: 4753231c ("pinctrl: sh-pfc: r8a7796: Add MSIOF pins, groups and functions") Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>
-
由 Takeshi Kihara 提交于
This patch fixes the IPSR register setting when the MSIOF3_SS1_E pin function is selected. This is a correction to the incorrect implementation of IPSR register pin assignment for R8A7796 SoC specification of R-Car Gen3 Hardware User's Manual Rev.0.51E or later. Fixes: f9aece73 ("pinctrl: sh-pfc: Initial R8A7796 PFC support") Signed-off-by: NTakeshi Kihara <takeshi.kihara.df@renesas.com> [geert: Reword] Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>
-
由 Takeshi Kihara 提交于
This patch fixes the incorrect IPSR register value definitions for MSIOF3_{SS1,SS2}_E pin functions. This is a correction to the incorrect implementation of IPSR register pin assignment for R8A7796 SoC specification of R-Car Gen3 Hardware User's Manual Rev.0.51E or later. Fixes: f9aece73 ("pinctrl: sh-pfc: Initial R8A7796 PFC support") Signed-off-by: NTakeshi Kihara <takeshi.kihara.df@renesas.com> [geert: Reword] Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>
-
- 16 5月, 2017 3 次提交
-
-
由 Kuninori Morimoto 提交于
Signed-off-by: NKuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>
-
由 Kuninori Morimoto 提交于
Signed-off-by: NKuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>
-
由 Kuninori Morimoto 提交于
R-Car Gen3 is using SSI_{WS,SCK}349 instead of SSI_{WS,SCK}34. But, current code is based on old datasheet which had typo. This patch fixes this typo. Signed-off-by: NKuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>
-
- 15 5月, 2017 3 次提交
-
-
由 Kuninori Morimoto 提交于
Based on Rev 0.50 or later R-Car Gen3 datasheet. Signed-off-by: NKuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>
-
由 Geert Uytterhoeven 提交于
Group the AVB pins into similar groups as found in other sh-pfc drivers. The pins can not be muxed between functions other than AVB, but their drive strengths can be controlled. The group avb_mdc containing ADV_MDC and ADV_MDIO is called avb_mdio on R-Car Gen2 SoCs. In pfc-r8a7796 the avb_mdc group already existed and is in use in DT. Therefore add the ADV_MDIO pin to the existing group instead of renaming it. Based on commit b25719eb ("pinctrl: sh-pfc: r8a7795: Add group for AVB MDIO and MII pins"). Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: NNiklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
-
由 Takeshi Kihara 提交于
This patch adds PWM{0,1,2,3,4,5,6} pins, groups and functions to R8A7796 SoC. Signed-off-by: NTakeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: NUlrich Hecht <ulrich.hecht+renesas@gmail.com> Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>
-
- 27 12月, 2016 6 次提交
-
-
由 Ulrich Hecht 提交于
Signed-off-by: NUlrich Hecht <ulrich.hecht+renesas@gmail.com> [geert: Fix hscif2_clk_[bc]_mux[] and hscif4_ctrl_mux[]] Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>
-
由 Takeshi Kihara 提交于
This patch adds MSIOF{0,1,2,3} pins, groups and functions to R8A7796 SoC. Signed-off-by: NTakeshi Kihara <takeshi.kihara.df@renesas.com> [geert: Correct MSIOF3 SS1_E/SS2_E pins] Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>
-
由 Chris Paterson 提交于
This patch adds CAN FD[0-1] pinmux support to r8a7796 SoC. Based on a patch for r8a7795 by Ramesh Shanmugasundaram. Signed-off-by: NChris Paterson <chris.paterson2@renesas.com> Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>
-
由 Chris Paterson 提交于
This patch adds CAN[0-1] pinmux support to r8a7796 SoC. Based on a patch for r8a7795 by Ramesh Shanmugasundaram. Signed-off-by: NChris Paterson <chris.paterson2@renesas.com> Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>
-
由 Niklas Söderlund 提交于
Implements pull-up and pull-down. On this SoC there is no simple mapping of GP pins to bias register bits, so we need a table. Signed-off-by: NNiklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>
-
由 Niklas Söderlund 提交于
Define the drive strength registers for the R8A7796. Add pins which are not part of a GPIO bank nor can be muxed between different functions but which still allow for their drive-strength to be configured. Signed-off-by: NNiklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>
-
- 15 11月, 2016 2 次提交
-
-
由 Niklas Söderlund 提交于
Only the DU parallel RGB output signals are included, HDMI and TCON pins will be added in separate groups. Based on a similar patch from Laurent Pinchart for the r8a7795 PFC driver. Signed-off-by: NNiklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Reviewed-by: NLaurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>
-
由 Takeshi Kihara 提交于
This patch adds AVB_LINK, AVB_MAGIC, AVB_PHY_INT, AVB_MDC, AVB_AVTP_PPS, AVB_AVTP_MATCH, AVB_AVTP_CAPTURE pins, groups and functions to R8A7796 SoC. Signed-off-by: NTakeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>
-
- 07 11月, 2016 1 次提交
-
-
由 Geert Uytterhoeven 提交于
Fix off-by-one (row and/or register) errors in links to Peripheral Function Select Register bitfields from GPIO/Peripheral Function Select Register 4 macros for SDHI2 and SDHI3 pins. Based on rev. 0.52E of the R-Car Gen3 User's Manual. Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be> Tested-by: NSimon Horman <horms+renesas@verge.net.au>
-
- 17 10月, 2016 2 次提交
-
-
由 Ramesh Shanmugasundaram 提交于
This patch adds DRIF[0-3] pinmux support for r8a7796 SoC. Signed-off-by: NRamesh Shanmugasundaram <ramesh.shanmugasundaram@bp.renesas.com> Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>
-
由 Ulrich Hecht 提交于
Signed-off-by: NUlrich Hecht <ulrich.hecht+renesas@gmail.com> Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>
-
- 12 9月, 2016 1 次提交
-
-
由 Simon Horman 提交于
This patch supports the {get,set}_io_voltage operations of SDHI. This operates the POCCTRL0 register on R8A7796 SoC and makes 1.8v/3.3v voltage switch. Based on work by Takeshi Kihara and Wolfram Sang. Cc: Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: NSimon Horman <horms+renesas@verge.net.au> Reviewed-by: NWolfram Sang <wsa+renesas@sang-engineering.com> Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>
-
- 19 8月, 2016 1 次提交
-
-
由 Takeshi Kihara 提交于
This patch adds SDHI pins, groups and functions to R8A7796 SoC. Signed-off-by: NTakeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: NSimon Horman <horms+renesas@verge.net.au> Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>
-